1 /* 2 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA, 3 * All Rights Reserved. 4 * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA, 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sub license, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #include <subdev/fb.h> 28 #include <subdev/vm.h> 29 #include <subdev/instmem.h> 30 31 #include "nouveau_drm.h" 32 #include "nouveau_ttm.h" 33 #include "nouveau_gem.h" 34 35 static int 36 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) 37 { 38 struct nouveau_drm *drm = nouveau_bdev(man->bdev); 39 struct nouveau_fb *pfb = nouveau_fb(drm->device); 40 man->priv = pfb; 41 return 0; 42 } 43 44 static int 45 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man) 46 { 47 man->priv = NULL; 48 return 0; 49 } 50 51 static inline void 52 nouveau_mem_node_cleanup(struct nouveau_mem *node) 53 { 54 if (node->vma[0].node) { 55 nouveau_vm_unmap(&node->vma[0]); 56 nouveau_vm_put(&node->vma[0]); 57 } 58 59 if (node->vma[1].node) { 60 nouveau_vm_unmap(&node->vma[1]); 61 nouveau_vm_put(&node->vma[1]); 62 } 63 } 64 65 static void 66 nouveau_vram_manager_del(struct ttm_mem_type_manager *man, 67 struct ttm_mem_reg *mem) 68 { 69 struct nouveau_drm *drm = nouveau_bdev(man->bdev); 70 struct nouveau_fb *pfb = nouveau_fb(drm->device); 71 nouveau_mem_node_cleanup(mem->mm_node); 72 pfb->ram->put(pfb, (struct nouveau_mem **)&mem->mm_node); 73 } 74 75 static int 76 nouveau_vram_manager_new(struct ttm_mem_type_manager *man, 77 struct ttm_buffer_object *bo, 78 struct ttm_placement *placement, 79 struct ttm_mem_reg *mem) 80 { 81 struct nouveau_drm *drm = nouveau_bdev(man->bdev); 82 struct nouveau_fb *pfb = nouveau_fb(drm->device); 83 struct nouveau_bo *nvbo = nouveau_bo(bo); 84 struct nouveau_mem *node; 85 u32 size_nc = 0; 86 int ret; 87 88 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) 89 size_nc = 1 << nvbo->page_shift; 90 91 ret = pfb->ram->get(pfb, mem->num_pages << PAGE_SHIFT, 92 mem->page_alignment << PAGE_SHIFT, size_nc, 93 (nvbo->tile_flags >> 8) & 0x3ff, &node); 94 if (ret) { 95 mem->mm_node = NULL; 96 return (ret == -ENOSPC) ? 0 : ret; 97 } 98 99 node->page_shift = nvbo->page_shift; 100 101 mem->mm_node = node; 102 mem->start = node->offset >> PAGE_SHIFT; 103 return 0; 104 } 105 106 static void 107 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) 108 { 109 struct nouveau_fb *pfb = man->priv; 110 struct nouveau_mm *mm = &pfb->vram; 111 struct nouveau_mm_node *r; 112 u32 total = 0, free = 0; 113 114 mutex_lock(&nv_subdev(pfb)->mutex); 115 list_for_each_entry(r, &mm->nodes, nl_entry) { 116 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n", 117 prefix, r->type, ((u64)r->offset << 12), 118 (((u64)r->offset + r->length) << 12)); 119 120 total += r->length; 121 if (!r->type) 122 free += r->length; 123 } 124 mutex_unlock(&nv_subdev(pfb)->mutex); 125 126 printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n", 127 prefix, (u64)total << 12, (u64)free << 12); 128 printk(KERN_DEBUG "%s block: 0x%08x\n", 129 prefix, mm->block_size << 12); 130 } 131 132 const struct ttm_mem_type_manager_func nouveau_vram_manager = { 133 nouveau_vram_manager_init, 134 nouveau_vram_manager_fini, 135 nouveau_vram_manager_new, 136 nouveau_vram_manager_del, 137 nouveau_vram_manager_debug 138 }; 139 140 static int 141 nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) 142 { 143 return 0; 144 } 145 146 static int 147 nouveau_gart_manager_fini(struct ttm_mem_type_manager *man) 148 { 149 return 0; 150 } 151 152 static void 153 nouveau_gart_manager_del(struct ttm_mem_type_manager *man, 154 struct ttm_mem_reg *mem) 155 { 156 nouveau_mem_node_cleanup(mem->mm_node); 157 kfree(mem->mm_node); 158 mem->mm_node = NULL; 159 } 160 161 static int 162 nouveau_gart_manager_new(struct ttm_mem_type_manager *man, 163 struct ttm_buffer_object *bo, 164 struct ttm_placement *placement, 165 struct ttm_mem_reg *mem) 166 { 167 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 168 struct nouveau_bo *nvbo = nouveau_bo(bo); 169 struct nouveau_mem *node; 170 171 node = kzalloc(sizeof(*node), GFP_KERNEL); 172 if (!node) 173 return -ENOMEM; 174 node->page_shift = 12; 175 176 switch (nv_device(drm->device)->card_type) { 177 case NV_50: 178 if (nv_device(drm->device)->chipset != 0x50) 179 node->memtype = (nvbo->tile_flags & 0x7f00) >> 8; 180 break; 181 case NV_C0: 182 case NV_D0: 183 case NV_E0: 184 node->memtype = (nvbo->tile_flags & 0xff00) >> 8; 185 break; 186 default: 187 break; 188 } 189 190 mem->mm_node = node; 191 mem->start = 0; 192 return 0; 193 } 194 195 static void 196 nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) 197 { 198 } 199 200 const struct ttm_mem_type_manager_func nouveau_gart_manager = { 201 nouveau_gart_manager_init, 202 nouveau_gart_manager_fini, 203 nouveau_gart_manager_new, 204 nouveau_gart_manager_del, 205 nouveau_gart_manager_debug 206 }; 207 208 #include <core/subdev/vm/nv04.h> 209 static int 210 nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) 211 { 212 struct nouveau_drm *drm = nouveau_bdev(man->bdev); 213 struct nouveau_vmmgr *vmm = nouveau_vmmgr(drm->device); 214 struct nv04_vmmgr_priv *priv = (void *)vmm; 215 struct nouveau_vm *vm = NULL; 216 nouveau_vm_ref(priv->vm, &vm, NULL); 217 man->priv = vm; 218 return 0; 219 } 220 221 static int 222 nv04_gart_manager_fini(struct ttm_mem_type_manager *man) 223 { 224 struct nouveau_vm *vm = man->priv; 225 nouveau_vm_ref(NULL, &vm, NULL); 226 man->priv = NULL; 227 return 0; 228 } 229 230 static void 231 nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) 232 { 233 struct nouveau_mem *node = mem->mm_node; 234 if (node->vma[0].node) 235 nouveau_vm_put(&node->vma[0]); 236 kfree(mem->mm_node); 237 mem->mm_node = NULL; 238 } 239 240 static int 241 nv04_gart_manager_new(struct ttm_mem_type_manager *man, 242 struct ttm_buffer_object *bo, 243 struct ttm_placement *placement, 244 struct ttm_mem_reg *mem) 245 { 246 struct nouveau_mem *node; 247 int ret; 248 249 node = kzalloc(sizeof(*node), GFP_KERNEL); 250 if (!node) 251 return -ENOMEM; 252 253 node->page_shift = 12; 254 255 ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, 256 NV_MEM_ACCESS_RW, &node->vma[0]); 257 if (ret) { 258 kfree(node); 259 return ret; 260 } 261 262 mem->mm_node = node; 263 mem->start = node->vma[0].offset >> PAGE_SHIFT; 264 return 0; 265 } 266 267 static void 268 nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) 269 { 270 } 271 272 const struct ttm_mem_type_manager_func nv04_gart_manager = { 273 nv04_gart_manager_init, 274 nv04_gart_manager_fini, 275 nv04_gart_manager_new, 276 nv04_gart_manager_del, 277 nv04_gart_manager_debug 278 }; 279 280 int 281 nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma) 282 { 283 struct drm_file *file_priv = filp->private_data; 284 struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev); 285 286 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 287 return drm_mmap(filp, vma); 288 289 return ttm_bo_mmap(filp, vma, &drm->ttm.bdev); 290 } 291 292 static int 293 nouveau_ttm_mem_global_init(struct drm_global_reference *ref) 294 { 295 return ttm_mem_global_init(ref->object); 296 } 297 298 static void 299 nouveau_ttm_mem_global_release(struct drm_global_reference *ref) 300 { 301 ttm_mem_global_release(ref->object); 302 } 303 304 int 305 nouveau_ttm_global_init(struct nouveau_drm *drm) 306 { 307 struct drm_global_reference *global_ref; 308 int ret; 309 310 global_ref = &drm->ttm.mem_global_ref; 311 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 312 global_ref->size = sizeof(struct ttm_mem_global); 313 global_ref->init = &nouveau_ttm_mem_global_init; 314 global_ref->release = &nouveau_ttm_mem_global_release; 315 316 ret = drm_global_item_ref(global_ref); 317 if (unlikely(ret != 0)) { 318 DRM_ERROR("Failed setting up TTM memory accounting\n"); 319 drm->ttm.mem_global_ref.release = NULL; 320 return ret; 321 } 322 323 drm->ttm.bo_global_ref.mem_glob = global_ref->object; 324 global_ref = &drm->ttm.bo_global_ref.ref; 325 global_ref->global_type = DRM_GLOBAL_TTM_BO; 326 global_ref->size = sizeof(struct ttm_bo_global); 327 global_ref->init = &ttm_bo_global_init; 328 global_ref->release = &ttm_bo_global_release; 329 330 ret = drm_global_item_ref(global_ref); 331 if (unlikely(ret != 0)) { 332 DRM_ERROR("Failed setting up TTM BO subsystem\n"); 333 drm_global_item_unref(&drm->ttm.mem_global_ref); 334 drm->ttm.mem_global_ref.release = NULL; 335 return ret; 336 } 337 338 return 0; 339 } 340 341 void 342 nouveau_ttm_global_release(struct nouveau_drm *drm) 343 { 344 if (drm->ttm.mem_global_ref.release == NULL) 345 return; 346 347 drm_global_item_unref(&drm->ttm.bo_global_ref.ref); 348 drm_global_item_unref(&drm->ttm.mem_global_ref); 349 drm->ttm.mem_global_ref.release = NULL; 350 } 351 352 int 353 nouveau_ttm_init(struct nouveau_drm *drm) 354 { 355 struct drm_device *dev = drm->dev; 356 u32 bits; 357 int ret; 358 359 bits = nouveau_vmmgr(drm->device)->dma_bits; 360 if ( drm->agp.stat == ENABLED || 361 !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) 362 bits = 32; 363 364 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits)); 365 if (ret) 366 return ret; 367 368 ret = pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(bits)); 369 if (ret) 370 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(32)); 371 372 ret = nouveau_ttm_global_init(drm); 373 if (ret) 374 return ret; 375 376 ret = ttm_bo_device_init(&drm->ttm.bdev, 377 drm->ttm.bo_global_ref.ref.object, 378 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET, 379 bits <= 32 ? true : false); 380 if (ret) { 381 NV_ERROR(drm, "error initialising bo driver, %d\n", ret); 382 return ret; 383 } 384 385 /* VRAM init */ 386 drm->gem.vram_available = nouveau_fb(drm->device)->ram->size; 387 drm->gem.vram_available -= nouveau_instmem(drm->device)->reserved; 388 389 ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM, 390 drm->gem.vram_available >> PAGE_SHIFT); 391 if (ret) { 392 NV_ERROR(drm, "VRAM mm init failed, %d\n", ret); 393 return ret; 394 } 395 396 drm->ttm.mtrr = arch_phys_wc_add(pci_resource_start(dev->pdev, 1), 397 pci_resource_len(dev->pdev, 1)); 398 399 /* GART init */ 400 if (drm->agp.stat != ENABLED) { 401 drm->gem.gart_available = nouveau_vmmgr(drm->device)->limit; 402 } else { 403 drm->gem.gart_available = drm->agp.size; 404 } 405 406 ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT, 407 drm->gem.gart_available >> PAGE_SHIFT); 408 if (ret) { 409 NV_ERROR(drm, "GART mm init failed, %d\n", ret); 410 return ret; 411 } 412 413 NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20)); 414 NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20)); 415 return 0; 416 } 417 418 void 419 nouveau_ttm_fini(struct nouveau_drm *drm) 420 { 421 mutex_lock(&drm->dev->struct_mutex); 422 ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM); 423 ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT); 424 mutex_unlock(&drm->dev->struct_mutex); 425 426 ttm_bo_device_release(&drm->ttm.bdev); 427 428 nouveau_ttm_global_release(drm); 429 430 arch_phys_wc_del(drm->ttm.mtrr); 431 drm->ttm.mtrr = 0; 432 } 433