1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "nouveau_svm.h" 23 #include "nouveau_drv.h" 24 #include "nouveau_chan.h" 25 #include "nouveau_dmem.h" 26 27 #include <nvif/notify.h> 28 #include <nvif/object.h> 29 #include <nvif/vmm.h> 30 31 #include <nvif/class.h> 32 #include <nvif/clb069.h> 33 #include <nvif/ifc00d.h> 34 35 #include <linux/sched/mm.h> 36 #include <linux/sort.h> 37 #include <linux/hmm.h> 38 39 struct nouveau_svm { 40 struct nouveau_drm *drm; 41 struct mutex mutex; 42 struct list_head inst; 43 44 struct nouveau_svm_fault_buffer { 45 int id; 46 struct nvif_object object; 47 u32 entries; 48 u32 getaddr; 49 u32 putaddr; 50 u32 get; 51 u32 put; 52 struct nvif_notify notify; 53 54 struct nouveau_svm_fault { 55 u64 inst; 56 u64 addr; 57 u64 time; 58 u32 engine; 59 u8 gpc; 60 u8 hub; 61 u8 access; 62 u8 client; 63 u8 fault; 64 struct nouveau_svmm *svmm; 65 } **fault; 66 int fault_nr; 67 } buffer[1]; 68 }; 69 70 #define SVM_DBG(s,f,a...) NV_DEBUG((s)->drm, "svm: "f"\n", ##a) 71 #define SVM_ERR(s,f,a...) NV_WARN((s)->drm, "svm: "f"\n", ##a) 72 73 struct nouveau_ivmm { 74 struct nouveau_svmm *svmm; 75 u64 inst; 76 struct list_head head; 77 }; 78 79 static struct nouveau_ivmm * 80 nouveau_ivmm_find(struct nouveau_svm *svm, u64 inst) 81 { 82 struct nouveau_ivmm *ivmm; 83 list_for_each_entry(ivmm, &svm->inst, head) { 84 if (ivmm->inst == inst) 85 return ivmm; 86 } 87 return NULL; 88 } 89 90 struct nouveau_svmm { 91 struct mmu_notifier notifier; 92 struct nouveau_vmm *vmm; 93 struct { 94 unsigned long start; 95 unsigned long limit; 96 } unmanaged; 97 98 struct mutex mutex; 99 }; 100 101 #define SVMM_DBG(s,f,a...) \ 102 NV_DEBUG((s)->vmm->cli->drm, "svm-%p: "f"\n", (s), ##a) 103 #define SVMM_ERR(s,f,a...) \ 104 NV_WARN((s)->vmm->cli->drm, "svm-%p: "f"\n", (s), ##a) 105 106 int 107 nouveau_svmm_bind(struct drm_device *dev, void *data, 108 struct drm_file *file_priv) 109 { 110 struct nouveau_cli *cli = nouveau_cli(file_priv); 111 struct drm_nouveau_svm_bind *args = data; 112 unsigned target, cmd, priority; 113 unsigned long addr, end, size; 114 struct mm_struct *mm; 115 116 args->va_start &= PAGE_MASK; 117 args->va_end &= PAGE_MASK; 118 119 /* Sanity check arguments */ 120 if (args->reserved0 || args->reserved1) 121 return -EINVAL; 122 if (args->header & (~NOUVEAU_SVM_BIND_VALID_MASK)) 123 return -EINVAL; 124 if (args->va_start >= args->va_end) 125 return -EINVAL; 126 if (!args->npages) 127 return -EINVAL; 128 129 cmd = args->header >> NOUVEAU_SVM_BIND_COMMAND_SHIFT; 130 cmd &= NOUVEAU_SVM_BIND_COMMAND_MASK; 131 switch (cmd) { 132 case NOUVEAU_SVM_BIND_COMMAND__MIGRATE: 133 break; 134 default: 135 return -EINVAL; 136 } 137 138 priority = args->header >> NOUVEAU_SVM_BIND_PRIORITY_SHIFT; 139 priority &= NOUVEAU_SVM_BIND_PRIORITY_MASK; 140 141 /* FIXME support CPU target ie all target value < GPU_VRAM */ 142 target = args->header >> NOUVEAU_SVM_BIND_TARGET_SHIFT; 143 target &= NOUVEAU_SVM_BIND_TARGET_MASK; 144 switch (target) { 145 case NOUVEAU_SVM_BIND_TARGET__GPU_VRAM: 146 break; 147 default: 148 return -EINVAL; 149 } 150 151 /* 152 * FIXME: For now refuse non 0 stride, we need to change the migrate 153 * kernel function to handle stride to avoid to create a mess within 154 * each device driver. 155 */ 156 if (args->stride) 157 return -EINVAL; 158 159 size = ((unsigned long)args->npages) << PAGE_SHIFT; 160 if ((args->va_start + size) <= args->va_start) 161 return -EINVAL; 162 if ((args->va_start + size) > args->va_end) 163 return -EINVAL; 164 165 /* 166 * Ok we are ask to do something sane, for now we only support migrate 167 * commands but we will add things like memory policy (what to do on 168 * page fault) and maybe some other commands. 169 */ 170 171 mm = get_task_mm(current); 172 down_read(&mm->mmap_sem); 173 174 for (addr = args->va_start, end = args->va_start + size; addr < end;) { 175 struct vm_area_struct *vma; 176 unsigned long next; 177 178 vma = find_vma_intersection(mm, addr, end); 179 if (!vma) 180 break; 181 182 next = min(vma->vm_end, end); 183 /* This is a best effort so we ignore errors */ 184 nouveau_dmem_migrate_vma(cli->drm, vma, addr, next); 185 addr = next; 186 } 187 188 /* 189 * FIXME Return the number of page we have migrated, again we need to 190 * update the migrate API to return that information so that we can 191 * report it to user space. 192 */ 193 args->result = 0; 194 195 up_read(&mm->mmap_sem); 196 mmput(mm); 197 198 return 0; 199 } 200 201 /* Unlink channel instance from SVMM. */ 202 void 203 nouveau_svmm_part(struct nouveau_svmm *svmm, u64 inst) 204 { 205 struct nouveau_ivmm *ivmm; 206 if (svmm) { 207 mutex_lock(&svmm->vmm->cli->drm->svm->mutex); 208 ivmm = nouveau_ivmm_find(svmm->vmm->cli->drm->svm, inst); 209 if (ivmm) { 210 list_del(&ivmm->head); 211 kfree(ivmm); 212 } 213 mutex_unlock(&svmm->vmm->cli->drm->svm->mutex); 214 } 215 } 216 217 /* Link channel instance to SVMM. */ 218 int 219 nouveau_svmm_join(struct nouveau_svmm *svmm, u64 inst) 220 { 221 struct nouveau_ivmm *ivmm; 222 if (svmm) { 223 if (!(ivmm = kmalloc(sizeof(*ivmm), GFP_KERNEL))) 224 return -ENOMEM; 225 ivmm->svmm = svmm; 226 ivmm->inst = inst; 227 228 mutex_lock(&svmm->vmm->cli->drm->svm->mutex); 229 list_add(&ivmm->head, &svmm->vmm->cli->drm->svm->inst); 230 mutex_unlock(&svmm->vmm->cli->drm->svm->mutex); 231 } 232 return 0; 233 } 234 235 /* Invalidate SVMM address-range on GPU. */ 236 static void 237 nouveau_svmm_invalidate(struct nouveau_svmm *svmm, u64 start, u64 limit) 238 { 239 if (limit > start) { 240 bool super = svmm->vmm->vmm.object.client->super; 241 svmm->vmm->vmm.object.client->super = true; 242 nvif_object_mthd(&svmm->vmm->vmm.object, NVIF_VMM_V0_PFNCLR, 243 &(struct nvif_vmm_pfnclr_v0) { 244 .addr = start, 245 .size = limit - start, 246 }, sizeof(struct nvif_vmm_pfnclr_v0)); 247 svmm->vmm->vmm.object.client->super = super; 248 } 249 } 250 251 static int 252 nouveau_svmm_invalidate_range_start(struct mmu_notifier *mn, 253 const struct mmu_notifier_range *update) 254 { 255 struct nouveau_svmm *svmm = 256 container_of(mn, struct nouveau_svmm, notifier); 257 unsigned long start = update->start; 258 unsigned long limit = update->end; 259 260 if (!mmu_notifier_range_blockable(update)) 261 return -EAGAIN; 262 263 SVMM_DBG(svmm, "invalidate %016lx-%016lx", start, limit); 264 265 mutex_lock(&svmm->mutex); 266 if (unlikely(!svmm->vmm)) 267 goto out; 268 269 if (limit > svmm->unmanaged.start && start < svmm->unmanaged.limit) { 270 if (start < svmm->unmanaged.start) { 271 nouveau_svmm_invalidate(svmm, start, 272 svmm->unmanaged.limit); 273 } 274 start = svmm->unmanaged.limit; 275 } 276 277 nouveau_svmm_invalidate(svmm, start, limit); 278 279 out: 280 mutex_unlock(&svmm->mutex); 281 return 0; 282 } 283 284 static void nouveau_svmm_free_notifier(struct mmu_notifier *mn) 285 { 286 kfree(container_of(mn, struct nouveau_svmm, notifier)); 287 } 288 289 static const struct mmu_notifier_ops nouveau_mn_ops = { 290 .invalidate_range_start = nouveau_svmm_invalidate_range_start, 291 .free_notifier = nouveau_svmm_free_notifier, 292 }; 293 294 void 295 nouveau_svmm_fini(struct nouveau_svmm **psvmm) 296 { 297 struct nouveau_svmm *svmm = *psvmm; 298 if (svmm) { 299 mutex_lock(&svmm->mutex); 300 svmm->vmm = NULL; 301 mutex_unlock(&svmm->mutex); 302 mmu_notifier_put(&svmm->notifier); 303 *psvmm = NULL; 304 } 305 } 306 307 int 308 nouveau_svmm_init(struct drm_device *dev, void *data, 309 struct drm_file *file_priv) 310 { 311 struct nouveau_cli *cli = nouveau_cli(file_priv); 312 struct nouveau_svmm *svmm; 313 struct drm_nouveau_svm_init *args = data; 314 int ret; 315 316 /* Allocate tracking for SVM-enabled VMM. */ 317 if (!(svmm = kzalloc(sizeof(*svmm), GFP_KERNEL))) 318 return -ENOMEM; 319 svmm->vmm = &cli->svm; 320 svmm->unmanaged.start = args->unmanaged_addr; 321 svmm->unmanaged.limit = args->unmanaged_addr + args->unmanaged_size; 322 mutex_init(&svmm->mutex); 323 324 /* Check that SVM isn't already enabled for the client. */ 325 mutex_lock(&cli->mutex); 326 if (cli->svm.cli) { 327 ret = -EBUSY; 328 goto out_free; 329 } 330 331 /* Allocate a new GPU VMM that can support SVM (managed by the 332 * client, with replayable faults enabled). 333 * 334 * All future channel/memory allocations will make use of this 335 * VMM instead of the standard one. 336 */ 337 ret = nvif_vmm_init(&cli->mmu, cli->vmm.vmm.object.oclass, true, 338 args->unmanaged_addr, args->unmanaged_size, 339 &(struct gp100_vmm_v0) { 340 .fault_replay = true, 341 }, sizeof(struct gp100_vmm_v0), &cli->svm.vmm); 342 if (ret) 343 goto out_free; 344 345 down_write(¤t->mm->mmap_sem); 346 svmm->notifier.ops = &nouveau_mn_ops; 347 ret = __mmu_notifier_register(&svmm->notifier, current->mm); 348 if (ret) 349 goto out_mm_unlock; 350 /* Note, ownership of svmm transfers to mmu_notifier */ 351 352 cli->svm.svmm = svmm; 353 cli->svm.cli = cli; 354 up_write(¤t->mm->mmap_sem); 355 mutex_unlock(&cli->mutex); 356 return 0; 357 358 out_mm_unlock: 359 up_write(¤t->mm->mmap_sem); 360 out_free: 361 mutex_unlock(&cli->mutex); 362 kfree(svmm); 363 return ret; 364 } 365 366 static const u64 367 nouveau_svm_pfn_flags[HMM_PFN_FLAG_MAX] = { 368 [HMM_PFN_VALID ] = NVIF_VMM_PFNMAP_V0_V, 369 [HMM_PFN_WRITE ] = NVIF_VMM_PFNMAP_V0_W, 370 [HMM_PFN_DEVICE_PRIVATE] = NVIF_VMM_PFNMAP_V0_VRAM, 371 }; 372 373 static const u64 374 nouveau_svm_pfn_values[HMM_PFN_VALUE_MAX] = { 375 [HMM_PFN_ERROR ] = ~NVIF_VMM_PFNMAP_V0_V, 376 [HMM_PFN_NONE ] = NVIF_VMM_PFNMAP_V0_NONE, 377 [HMM_PFN_SPECIAL] = ~NVIF_VMM_PFNMAP_V0_V, 378 }; 379 380 /* Issue fault replay for GPU to retry accesses that faulted previously. */ 381 static void 382 nouveau_svm_fault_replay(struct nouveau_svm *svm) 383 { 384 SVM_DBG(svm, "replay"); 385 WARN_ON(nvif_object_mthd(&svm->drm->client.vmm.vmm.object, 386 GP100_VMM_VN_FAULT_REPLAY, 387 &(struct gp100_vmm_fault_replay_vn) {}, 388 sizeof(struct gp100_vmm_fault_replay_vn))); 389 } 390 391 /* Cancel a replayable fault that could not be handled. 392 * 393 * Cancelling the fault will trigger recovery to reset the engine 394 * and kill the offending channel (ie. GPU SIGSEGV). 395 */ 396 static void 397 nouveau_svm_fault_cancel(struct nouveau_svm *svm, 398 u64 inst, u8 hub, u8 gpc, u8 client) 399 { 400 SVM_DBG(svm, "cancel %016llx %d %02x %02x", inst, hub, gpc, client); 401 WARN_ON(nvif_object_mthd(&svm->drm->client.vmm.vmm.object, 402 GP100_VMM_VN_FAULT_CANCEL, 403 &(struct gp100_vmm_fault_cancel_v0) { 404 .hub = hub, 405 .gpc = gpc, 406 .client = client, 407 .inst = inst, 408 }, sizeof(struct gp100_vmm_fault_cancel_v0))); 409 } 410 411 static void 412 nouveau_svm_fault_cancel_fault(struct nouveau_svm *svm, 413 struct nouveau_svm_fault *fault) 414 { 415 nouveau_svm_fault_cancel(svm, fault->inst, 416 fault->hub, 417 fault->gpc, 418 fault->client); 419 } 420 421 static int 422 nouveau_svm_fault_cmp(const void *a, const void *b) 423 { 424 const struct nouveau_svm_fault *fa = *(struct nouveau_svm_fault **)a; 425 const struct nouveau_svm_fault *fb = *(struct nouveau_svm_fault **)b; 426 int ret; 427 if ((ret = (s64)fa->inst - fb->inst)) 428 return ret; 429 if ((ret = (s64)fa->addr - fb->addr)) 430 return ret; 431 /*XXX: atomic? */ 432 return (fa->access == 0 || fa->access == 3) - 433 (fb->access == 0 || fb->access == 3); 434 } 435 436 static void 437 nouveau_svm_fault_cache(struct nouveau_svm *svm, 438 struct nouveau_svm_fault_buffer *buffer, u32 offset) 439 { 440 struct nvif_object *memory = &buffer->object; 441 const u32 instlo = nvif_rd32(memory, offset + 0x00); 442 const u32 insthi = nvif_rd32(memory, offset + 0x04); 443 const u32 addrlo = nvif_rd32(memory, offset + 0x08); 444 const u32 addrhi = nvif_rd32(memory, offset + 0x0c); 445 const u32 timelo = nvif_rd32(memory, offset + 0x10); 446 const u32 timehi = nvif_rd32(memory, offset + 0x14); 447 const u32 engine = nvif_rd32(memory, offset + 0x18); 448 const u32 info = nvif_rd32(memory, offset + 0x1c); 449 const u64 inst = (u64)insthi << 32 | instlo; 450 const u8 gpc = (info & 0x1f000000) >> 24; 451 const u8 hub = (info & 0x00100000) >> 20; 452 const u8 client = (info & 0x00007f00) >> 8; 453 struct nouveau_svm_fault *fault; 454 455 //XXX: i think we're supposed to spin waiting */ 456 if (WARN_ON(!(info & 0x80000000))) 457 return; 458 459 nvif_mask(memory, offset + 0x1c, 0x80000000, 0x00000000); 460 461 if (!buffer->fault[buffer->fault_nr]) { 462 fault = kmalloc(sizeof(*fault), GFP_KERNEL); 463 if (WARN_ON(!fault)) { 464 nouveau_svm_fault_cancel(svm, inst, hub, gpc, client); 465 return; 466 } 467 buffer->fault[buffer->fault_nr] = fault; 468 } 469 470 fault = buffer->fault[buffer->fault_nr++]; 471 fault->inst = inst; 472 fault->addr = (u64)addrhi << 32 | addrlo; 473 fault->time = (u64)timehi << 32 | timelo; 474 fault->engine = engine; 475 fault->gpc = gpc; 476 fault->hub = hub; 477 fault->access = (info & 0x000f0000) >> 16; 478 fault->client = client; 479 fault->fault = (info & 0x0000001f); 480 481 SVM_DBG(svm, "fault %016llx %016llx %02x", 482 fault->inst, fault->addr, fault->access); 483 } 484 485 struct svm_notifier { 486 struct mmu_interval_notifier notifier; 487 struct nouveau_svmm *svmm; 488 }; 489 490 static bool nouveau_svm_range_invalidate(struct mmu_interval_notifier *mni, 491 const struct mmu_notifier_range *range, 492 unsigned long cur_seq) 493 { 494 struct svm_notifier *sn = 495 container_of(mni, struct svm_notifier, notifier); 496 497 /* 498 * serializes the update to mni->invalidate_seq done by caller and 499 * prevents invalidation of the PTE from progressing while HW is being 500 * programmed. This is very hacky and only works because the normal 501 * notifier that does invalidation is always called after the range 502 * notifier. 503 */ 504 if (mmu_notifier_range_blockable(range)) 505 mutex_lock(&sn->svmm->mutex); 506 else if (!mutex_trylock(&sn->svmm->mutex)) 507 return false; 508 mmu_interval_set_seq(mni, cur_seq); 509 mutex_unlock(&sn->svmm->mutex); 510 return true; 511 } 512 513 static const struct mmu_interval_notifier_ops nouveau_svm_mni_ops = { 514 .invalidate = nouveau_svm_range_invalidate, 515 }; 516 517 static int nouveau_range_fault(struct nouveau_svmm *svmm, 518 struct nouveau_drm *drm, void *data, u32 size, 519 u64 *pfns, struct svm_notifier *notifier) 520 { 521 unsigned long timeout = 522 jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); 523 /* Have HMM fault pages within the fault window to the GPU. */ 524 struct hmm_range range = { 525 .notifier = ¬ifier->notifier, 526 .start = notifier->notifier.interval_tree.start, 527 .end = notifier->notifier.interval_tree.last + 1, 528 .pfns = pfns, 529 .flags = nouveau_svm_pfn_flags, 530 .values = nouveau_svm_pfn_values, 531 .pfn_shift = NVIF_VMM_PFNMAP_V0_ADDR_SHIFT, 532 }; 533 struct mm_struct *mm = notifier->notifier.mm; 534 long ret; 535 536 while (true) { 537 if (time_after(jiffies, timeout)) 538 return -EBUSY; 539 540 range.notifier_seq = mmu_interval_read_begin(range.notifier); 541 range.default_flags = 0; 542 range.pfn_flags_mask = -1UL; 543 down_read(&mm->mmap_sem); 544 ret = hmm_range_fault(&range, 0); 545 up_read(&mm->mmap_sem); 546 if (ret <= 0) { 547 if (ret == 0 || ret == -EBUSY) 548 continue; 549 return ret; 550 } 551 552 mutex_lock(&svmm->mutex); 553 if (mmu_interval_read_retry(range.notifier, 554 range.notifier_seq)) { 555 mutex_unlock(&svmm->mutex); 556 continue; 557 } 558 break; 559 } 560 561 nouveau_dmem_convert_pfn(drm, &range); 562 563 svmm->vmm->vmm.object.client->super = true; 564 ret = nvif_object_ioctl(&svmm->vmm->vmm.object, data, size, NULL); 565 svmm->vmm->vmm.object.client->super = false; 566 mutex_unlock(&svmm->mutex); 567 568 return ret; 569 } 570 571 static int 572 nouveau_svm_fault(struct nvif_notify *notify) 573 { 574 struct nouveau_svm_fault_buffer *buffer = 575 container_of(notify, typeof(*buffer), notify); 576 struct nouveau_svm *svm = 577 container_of(buffer, typeof(*svm), buffer[buffer->id]); 578 struct nvif_object *device = &svm->drm->client.device.object; 579 struct nouveau_svmm *svmm; 580 struct { 581 struct { 582 struct nvif_ioctl_v0 i; 583 struct nvif_ioctl_mthd_v0 m; 584 struct nvif_vmm_pfnmap_v0 p; 585 } i; 586 u64 phys[16]; 587 } args; 588 struct vm_area_struct *vma; 589 u64 inst, start, limit; 590 int fi, fn, pi, fill; 591 int replay = 0, ret; 592 593 /* Parse available fault buffer entries into a cache, and update 594 * the GET pointer so HW can reuse the entries. 595 */ 596 SVM_DBG(svm, "fault handler"); 597 if (buffer->get == buffer->put) { 598 buffer->put = nvif_rd32(device, buffer->putaddr); 599 buffer->get = nvif_rd32(device, buffer->getaddr); 600 if (buffer->get == buffer->put) 601 return NVIF_NOTIFY_KEEP; 602 } 603 buffer->fault_nr = 0; 604 605 SVM_DBG(svm, "get %08x put %08x", buffer->get, buffer->put); 606 while (buffer->get != buffer->put) { 607 nouveau_svm_fault_cache(svm, buffer, buffer->get * 0x20); 608 if (++buffer->get == buffer->entries) 609 buffer->get = 0; 610 } 611 nvif_wr32(device, buffer->getaddr, buffer->get); 612 SVM_DBG(svm, "%d fault(s) pending", buffer->fault_nr); 613 614 /* Sort parsed faults by instance pointer to prevent unnecessary 615 * instance to SVMM translations, followed by address and access 616 * type to reduce the amount of work when handling the faults. 617 */ 618 sort(buffer->fault, buffer->fault_nr, sizeof(*buffer->fault), 619 nouveau_svm_fault_cmp, NULL); 620 621 /* Lookup SVMM structure for each unique instance pointer. */ 622 mutex_lock(&svm->mutex); 623 for (fi = 0, svmm = NULL; fi < buffer->fault_nr; fi++) { 624 if (!svmm || buffer->fault[fi]->inst != inst) { 625 struct nouveau_ivmm *ivmm = 626 nouveau_ivmm_find(svm, buffer->fault[fi]->inst); 627 svmm = ivmm ? ivmm->svmm : NULL; 628 inst = buffer->fault[fi]->inst; 629 SVM_DBG(svm, "inst %016llx -> svm-%p", inst, svmm); 630 } 631 buffer->fault[fi]->svmm = svmm; 632 } 633 mutex_unlock(&svm->mutex); 634 635 /* Process list of faults. */ 636 args.i.i.version = 0; 637 args.i.i.type = NVIF_IOCTL_V0_MTHD; 638 args.i.m.version = 0; 639 args.i.m.method = NVIF_VMM_V0_PFNMAP; 640 args.i.p.version = 0; 641 642 for (fi = 0; fn = fi + 1, fi < buffer->fault_nr; fi = fn) { 643 struct svm_notifier notifier; 644 struct mm_struct *mm; 645 646 /* Cancel any faults from non-SVM channels. */ 647 if (!(svmm = buffer->fault[fi]->svmm)) { 648 nouveau_svm_fault_cancel_fault(svm, buffer->fault[fi]); 649 continue; 650 } 651 SVMM_DBG(svmm, "addr %016llx", buffer->fault[fi]->addr); 652 653 /* We try and group handling of faults within a small 654 * window into a single update. 655 */ 656 start = buffer->fault[fi]->addr; 657 limit = start + (ARRAY_SIZE(args.phys) << PAGE_SHIFT); 658 if (start < svmm->unmanaged.limit) 659 limit = min_t(u64, limit, svmm->unmanaged.start); 660 else 661 if (limit > svmm->unmanaged.start) 662 start = max_t(u64, start, svmm->unmanaged.limit); 663 SVMM_DBG(svmm, "wndw %016llx-%016llx", start, limit); 664 665 mm = svmm->notifier.mm; 666 if (!mmget_not_zero(mm)) { 667 nouveau_svm_fault_cancel_fault(svm, buffer->fault[fi]); 668 continue; 669 } 670 671 /* Intersect fault window with the CPU VMA, cancelling 672 * the fault if the address is invalid. 673 */ 674 down_read(&mm->mmap_sem); 675 vma = find_vma_intersection(mm, start, limit); 676 if (!vma) { 677 SVMM_ERR(svmm, "wndw %016llx-%016llx", start, limit); 678 up_read(&mm->mmap_sem); 679 mmput(mm); 680 nouveau_svm_fault_cancel_fault(svm, buffer->fault[fi]); 681 continue; 682 } 683 start = max_t(u64, start, vma->vm_start); 684 limit = min_t(u64, limit, vma->vm_end); 685 up_read(&mm->mmap_sem); 686 SVMM_DBG(svmm, "wndw %016llx-%016llx", start, limit); 687 688 if (buffer->fault[fi]->addr != start) { 689 SVMM_ERR(svmm, "addr %016llx", buffer->fault[fi]->addr); 690 mmput(mm); 691 nouveau_svm_fault_cancel_fault(svm, buffer->fault[fi]); 692 continue; 693 } 694 695 /* Prepare the GPU-side update of all pages within the 696 * fault window, determining required pages and access 697 * permissions based on pending faults. 698 */ 699 args.i.p.page = PAGE_SHIFT; 700 args.i.p.addr = start; 701 for (fn = fi, pi = 0;;) { 702 /* Determine required permissions based on GPU fault 703 * access flags. 704 *XXX: atomic? 705 */ 706 if (buffer->fault[fn]->access != 0 /* READ. */ && 707 buffer->fault[fn]->access != 3 /* PREFETCH. */) { 708 args.phys[pi++] = NVIF_VMM_PFNMAP_V0_V | 709 NVIF_VMM_PFNMAP_V0_W; 710 } else { 711 args.phys[pi++] = NVIF_VMM_PFNMAP_V0_V; 712 } 713 args.i.p.size = pi << PAGE_SHIFT; 714 715 /* It's okay to skip over duplicate addresses from the 716 * same SVMM as faults are ordered by access type such 717 * that only the first one needs to be handled. 718 * 719 * ie. WRITE faults appear first, thus any handling of 720 * pending READ faults will already be satisfied. 721 */ 722 while (++fn < buffer->fault_nr && 723 buffer->fault[fn]->svmm == svmm && 724 buffer->fault[fn ]->addr == 725 buffer->fault[fn - 1]->addr); 726 727 /* If the next fault is outside the window, or all GPU 728 * faults have been dealt with, we're done here. 729 */ 730 if (fn >= buffer->fault_nr || 731 buffer->fault[fn]->svmm != svmm || 732 buffer->fault[fn]->addr >= limit) 733 break; 734 735 /* Fill in the gap between this fault and the next. */ 736 fill = (buffer->fault[fn ]->addr - 737 buffer->fault[fn - 1]->addr) >> PAGE_SHIFT; 738 while (--fill) 739 args.phys[pi++] = NVIF_VMM_PFNMAP_V0_NONE; 740 } 741 742 SVMM_DBG(svmm, "wndw %016llx-%016llx covering %d fault(s)", 743 args.i.p.addr, 744 args.i.p.addr + args.i.p.size, fn - fi); 745 746 notifier.svmm = svmm; 747 ret = mmu_interval_notifier_insert(¬ifier.notifier, 748 svmm->notifier.mm, 749 args.i.p.addr, args.i.p.size, 750 &nouveau_svm_mni_ops); 751 if (!ret) { 752 ret = nouveau_range_fault( 753 svmm, svm->drm, &args, 754 sizeof(args.i) + pi * sizeof(args.phys[0]), 755 args.phys, ¬ifier); 756 mmu_interval_notifier_remove(¬ifier.notifier); 757 } 758 mmput(mm); 759 760 /* Cancel any faults in the window whose pages didn't manage 761 * to keep their valid bit, or stay writeable when required. 762 * 763 * If handling failed completely, cancel all faults. 764 */ 765 while (fi < fn) { 766 struct nouveau_svm_fault *fault = buffer->fault[fi++]; 767 pi = (fault->addr - args.i.p.addr) >> PAGE_SHIFT; 768 if (ret || 769 !(args.phys[pi] & NVIF_VMM_PFNMAP_V0_V) || 770 (!(args.phys[pi] & NVIF_VMM_PFNMAP_V0_W) && 771 fault->access != 0 && fault->access != 3)) { 772 nouveau_svm_fault_cancel_fault(svm, fault); 773 continue; 774 } 775 replay++; 776 } 777 } 778 779 /* Issue fault replay to the GPU. */ 780 if (replay) 781 nouveau_svm_fault_replay(svm); 782 return NVIF_NOTIFY_KEEP; 783 } 784 785 static void 786 nouveau_svm_fault_buffer_fini(struct nouveau_svm *svm, int id) 787 { 788 struct nouveau_svm_fault_buffer *buffer = &svm->buffer[id]; 789 nvif_notify_put(&buffer->notify); 790 } 791 792 static int 793 nouveau_svm_fault_buffer_init(struct nouveau_svm *svm, int id) 794 { 795 struct nouveau_svm_fault_buffer *buffer = &svm->buffer[id]; 796 struct nvif_object *device = &svm->drm->client.device.object; 797 buffer->get = nvif_rd32(device, buffer->getaddr); 798 buffer->put = nvif_rd32(device, buffer->putaddr); 799 SVM_DBG(svm, "get %08x put %08x (init)", buffer->get, buffer->put); 800 return nvif_notify_get(&buffer->notify); 801 } 802 803 static void 804 nouveau_svm_fault_buffer_dtor(struct nouveau_svm *svm, int id) 805 { 806 struct nouveau_svm_fault_buffer *buffer = &svm->buffer[id]; 807 int i; 808 809 if (buffer->fault) { 810 for (i = 0; buffer->fault[i] && i < buffer->entries; i++) 811 kfree(buffer->fault[i]); 812 kvfree(buffer->fault); 813 } 814 815 nouveau_svm_fault_buffer_fini(svm, id); 816 817 nvif_notify_fini(&buffer->notify); 818 nvif_object_fini(&buffer->object); 819 } 820 821 static int 822 nouveau_svm_fault_buffer_ctor(struct nouveau_svm *svm, s32 oclass, int id) 823 { 824 struct nouveau_svm_fault_buffer *buffer = &svm->buffer[id]; 825 struct nouveau_drm *drm = svm->drm; 826 struct nvif_object *device = &drm->client.device.object; 827 struct nvif_clb069_v0 args = {}; 828 int ret; 829 830 buffer->id = id; 831 832 ret = nvif_object_init(device, 0, oclass, &args, sizeof(args), 833 &buffer->object); 834 if (ret < 0) { 835 SVM_ERR(svm, "Fault buffer allocation failed: %d", ret); 836 return ret; 837 } 838 839 nvif_object_map(&buffer->object, NULL, 0); 840 buffer->entries = args.entries; 841 buffer->getaddr = args.get; 842 buffer->putaddr = args.put; 843 844 ret = nvif_notify_init(&buffer->object, nouveau_svm_fault, true, 845 NVB069_V0_NTFY_FAULT, NULL, 0, 0, 846 &buffer->notify); 847 if (ret) 848 return ret; 849 850 buffer->fault = kvzalloc(sizeof(*buffer->fault) * buffer->entries, GFP_KERNEL); 851 if (!buffer->fault) 852 return -ENOMEM; 853 854 return nouveau_svm_fault_buffer_init(svm, id); 855 } 856 857 void 858 nouveau_svm_resume(struct nouveau_drm *drm) 859 { 860 struct nouveau_svm *svm = drm->svm; 861 if (svm) 862 nouveau_svm_fault_buffer_init(svm, 0); 863 } 864 865 void 866 nouveau_svm_suspend(struct nouveau_drm *drm) 867 { 868 struct nouveau_svm *svm = drm->svm; 869 if (svm) 870 nouveau_svm_fault_buffer_fini(svm, 0); 871 } 872 873 void 874 nouveau_svm_fini(struct nouveau_drm *drm) 875 { 876 struct nouveau_svm *svm = drm->svm; 877 if (svm) { 878 nouveau_svm_fault_buffer_dtor(svm, 0); 879 kfree(drm->svm); 880 drm->svm = NULL; 881 } 882 } 883 884 void 885 nouveau_svm_init(struct nouveau_drm *drm) 886 { 887 static const struct nvif_mclass buffers[] = { 888 { VOLTA_FAULT_BUFFER_A, 0 }, 889 { MAXWELL_FAULT_BUFFER_A, 0 }, 890 {} 891 }; 892 struct nouveau_svm *svm; 893 int ret; 894 895 /* Disable on Volta and newer until channel recovery is fixed, 896 * otherwise clients will have a trivial way to trash the GPU 897 * for everyone. 898 */ 899 if (drm->client.device.info.family > NV_DEVICE_INFO_V0_PASCAL) 900 return; 901 902 if (!(drm->svm = svm = kzalloc(sizeof(*drm->svm), GFP_KERNEL))) 903 return; 904 905 drm->svm->drm = drm; 906 mutex_init(&drm->svm->mutex); 907 INIT_LIST_HEAD(&drm->svm->inst); 908 909 ret = nvif_mclass(&drm->client.device.object, buffers); 910 if (ret < 0) { 911 SVM_DBG(svm, "No supported fault buffer class"); 912 nouveau_svm_fini(drm); 913 return; 914 } 915 916 ret = nouveau_svm_fault_buffer_ctor(svm, buffers[ret].oclass, 0); 917 if (ret) { 918 nouveau_svm_fini(drm); 919 return; 920 } 921 922 SVM_DBG(svm, "Initialised"); 923 } 924