1 2 3 #define NV03_BOOT_0 0x00100000 4 # define NV03_BOOT_0_RAM_AMOUNT 0x00000003 5 # define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000 6 # define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001 7 # define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002 8 # define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003 9 # define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000 10 # define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001 11 # define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002 12 # define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003 13 14 #define NV04_FIFO_DATA 0x0010020c 15 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 16 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 17 18 #define NV_RAMIN 0x00700000 19 20 #define NV_RAMHT_HANDLE_OFFSET 0 21 #define NV_RAMHT_CONTEXT_OFFSET 4 22 # define NV_RAMHT_CONTEXT_VALID (1<<31) 23 # define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24 24 # define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16 25 # define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0 26 # define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1 27 # define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0 28 # define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23 29 # define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20 30 # define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0 31 32 /* DMA object defines */ 33 #define NV_DMA_ACCESS_RW 0 34 #define NV_DMA_ACCESS_RO 1 35 #define NV_DMA_ACCESS_WO 2 36 #define NV_DMA_TARGET_VIDMEM 0 37 #define NV_DMA_TARGET_PCI 2 38 #define NV_DMA_TARGET_AGP 3 39 /* The following is not a real value used by the card, it's changed by 40 * nouveau_object_dma_create */ 41 #define NV_DMA_TARGET_PCI_NONLINEAR 8 42 43 /* Some object classes we care about in the drm */ 44 #define NV_CLASS_DMA_FROM_MEMORY 0x00000002 45 #define NV_CLASS_DMA_TO_MEMORY 0x00000003 46 #define NV_CLASS_NULL 0x00000030 47 #define NV_CLASS_DMA_IN_MEMORY 0x0000003D 48 49 #define NV03_USER(i) (0x00800000+(i*NV03_USER_SIZE)) 50 #define NV03_USER__SIZE 16 51 #define NV10_USER__SIZE 32 52 #define NV03_USER_SIZE 0x00010000 53 #define NV03_USER_DMA_PUT(i) (0x00800040+(i*NV03_USER_SIZE)) 54 #define NV03_USER_DMA_PUT__SIZE 16 55 #define NV10_USER_DMA_PUT__SIZE 32 56 #define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE)) 57 #define NV03_USER_DMA_GET__SIZE 16 58 #define NV10_USER_DMA_GET__SIZE 32 59 #define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE)) 60 #define NV03_USER_REF_CNT__SIZE 16 61 #define NV10_USER_REF_CNT__SIZE 32 62 63 #define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE)) 64 #define NV40_USER_SIZE 0x00001000 65 #define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE)) 66 #define NV40_USER_DMA_PUT__SIZE 32 67 #define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE)) 68 #define NV40_USER_DMA_GET__SIZE 32 69 #define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE)) 70 #define NV40_USER_REF_CNT__SIZE 32 71 72 #define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE)) 73 #define NV50_USER_SIZE 0x00002000 74 #define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE)) 75 #define NV50_USER_DMA_PUT__SIZE 128 76 #define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE)) 77 #define NV50_USER_DMA_GET__SIZE 128 78 #define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE)) 79 #define NV50_USER_REF_CNT__SIZE 128 80 81 #define NV03_FIFO_SIZE 0x8000UL 82 83 #define NV03_PMC_BOOT_0 0x00000000 84 #define NV03_PMC_BOOT_1 0x00000004 85 #define NV03_PMC_INTR_0 0x00000100 86 # define NV_PMC_INTR_0_PFIFO_PENDING (1<<8) 87 # define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12) 88 # define NV_PMC_INTR_0_NV50_I2C_PENDING (1<<21) 89 # define NV_PMC_INTR_0_CRTC0_PENDING (1<<24) 90 # define NV_PMC_INTR_0_CRTC1_PENDING (1<<25) 91 # define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26) 92 # define NV_PMC_INTR_0_CRTCn_PENDING (3<<24) 93 #define NV03_PMC_INTR_EN_0 0x00000140 94 # define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<<0) 95 #define NV03_PMC_ENABLE 0x00000200 96 # define NV_PMC_ENABLE_PFIFO (1<<8) 97 # define NV_PMC_ENABLE_PGRAPH (1<<12) 98 /* Disabling the below bit breaks newer (G7X only?) mobile chipsets, 99 * the card will hang early on in the X init process. 100 */ 101 # define NV_PMC_ENABLE_UNK13 (1<<13) 102 #define NV40_PMC_GRAPH_UNITS 0x00001540 103 #define NV40_PMC_BACKLIGHT 0x000015f0 104 # define NV40_PMC_BACKLIGHT_MASK 0x001f0000 105 #define NV40_PMC_1700 0x00001700 106 #define NV40_PMC_1704 0x00001704 107 #define NV40_PMC_1708 0x00001708 108 #define NV40_PMC_170C 0x0000170C 109 110 /* probably PMC ? */ 111 #define NV50_PUNK_BAR0_PRAMIN 0x00001700 112 #define NV50_PUNK_BAR_CFG_BASE 0x00001704 113 #define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30) 114 #define NV50_PUNK_BAR1_CTXDMA 0x00001708 115 #define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31) 116 #define NV50_PUNK_BAR3_CTXDMA 0x0000170C 117 #define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31) 118 #define NV50_PUNK_UNK1710 0x00001710 119 120 #define NV04_PBUS_PCI_NV_1 0x00001804 121 #define NV04_PBUS_PCI_NV_19 0x0000184C 122 #define NV04_PBUS_PCI_NV_20 0x00001850 123 # define NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0) 124 # define NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0) 125 126 #define NV04_PTIMER_INTR_0 0x00009100 127 #define NV04_PTIMER_INTR_EN_0 0x00009140 128 #define NV04_PTIMER_NUMERATOR 0x00009200 129 #define NV04_PTIMER_DENOMINATOR 0x00009210 130 #define NV04_PTIMER_TIME_0 0x00009400 131 #define NV04_PTIMER_TIME_1 0x00009410 132 #define NV04_PTIMER_ALARM_0 0x00009420 133 134 #define NV04_PFB_CFG0 0x00100200 135 #define NV04_PFB_CFG1 0x00100204 136 #define NV40_PFB_020C 0x0010020C 137 #define NV10_PFB_TILE(i) (0x00100240 + (i*16)) 138 #define NV10_PFB_TILE__SIZE 8 139 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) 140 #define NV10_PFB_TSIZE(i) (0x00100248 + (i*16)) 141 #define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16)) 142 #define NV10_PFB_CLOSE_PAGE2 0x0010033C 143 #define NV40_PFB_TILE(i) (0x00100600 + (i*16)) 144 #define NV40_PFB_TILE__SIZE_0 12 145 #define NV40_PFB_TILE__SIZE_1 15 146 #define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16)) 147 #define NV40_PFB_TSIZE(i) (0x00100608 + (i*16)) 148 #define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16)) 149 #define NV40_PFB_UNK_800 0x00100800 150 151 #define NV04_PGRAPH_DEBUG_0 0x00400080 152 #define NV04_PGRAPH_DEBUG_1 0x00400084 153 #define NV04_PGRAPH_DEBUG_2 0x00400088 154 #define NV04_PGRAPH_DEBUG_3 0x0040008c 155 #define NV10_PGRAPH_DEBUG_4 0x00400090 156 #define NV03_PGRAPH_INTR 0x00400100 157 #define NV03_PGRAPH_NSTATUS 0x00400104 158 # define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) 159 # define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) 160 # define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) 161 # define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) 162 # define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) 163 # define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) 164 # define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) 165 # define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) 166 #define NV03_PGRAPH_NSOURCE 0x00400108 167 # define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0) 168 # define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<<1) 169 # define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<<2) 170 # define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<<3) 171 # define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<<4) 172 # define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<<5) 173 # define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<<6) 174 # define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<<7) 175 # define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<<8) 176 # define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<<9) 177 # define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) 178 # define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) 179 # define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) 180 # define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) 181 # define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) 182 # define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) 183 # define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) 184 # define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) 185 # define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) 186 #define NV03_PGRAPH_INTR_EN 0x00400140 187 #define NV40_PGRAPH_INTR_EN 0x0040013C 188 # define NV_PGRAPH_INTR_NOTIFY (1<<0) 189 # define NV_PGRAPH_INTR_MISSING_HW (1<<4) 190 # define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) 191 # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) 192 # define NV_PGRAPH_INTR_ERROR (1<<20) 193 #define NV10_PGRAPH_CTX_CONTROL 0x00400144 194 #define NV10_PGRAPH_CTX_USER 0x00400148 195 #define NV10_PGRAPH_CTX_SWITCH1 0x0040014C 196 #define NV10_PGRAPH_CTX_SWITCH2 0x00400150 197 #define NV10_PGRAPH_CTX_SWITCH3 0x00400154 198 #define NV10_PGRAPH_CTX_SWITCH4 0x00400158 199 #define NV10_PGRAPH_CTX_SWITCH5 0x0040015C 200 #define NV04_PGRAPH_CTX_SWITCH1 0x00400160 201 #define NV10_PGRAPH_CTX_CACHE1 0x00400160 202 #define NV04_PGRAPH_CTX_SWITCH2 0x00400164 203 #define NV04_PGRAPH_CTX_SWITCH3 0x00400168 204 #define NV04_PGRAPH_CTX_SWITCH4 0x0040016C 205 #define NV04_PGRAPH_CTX_CONTROL 0x00400170 206 #define NV04_PGRAPH_CTX_USER 0x00400174 207 #define NV04_PGRAPH_CTX_CACHE1 0x00400180 208 #define NV10_PGRAPH_CTX_CACHE2 0x00400180 209 #define NV03_PGRAPH_CTX_CONTROL 0x00400190 210 #define NV03_PGRAPH_CTX_USER 0x00400194 211 #define NV04_PGRAPH_CTX_CACHE2 0x004001A0 212 #define NV10_PGRAPH_CTX_CACHE3 0x004001A0 213 #define NV04_PGRAPH_CTX_CACHE3 0x004001C0 214 #define NV10_PGRAPH_CTX_CACHE4 0x004001C0 215 #define NV04_PGRAPH_CTX_CACHE4 0x004001E0 216 #define NV10_PGRAPH_CTX_CACHE5 0x004001E0 217 #define NV40_PGRAPH_CTXCTL_0304 0x00400304 218 #define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 219 #define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 220 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 221 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 222 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff 223 #define NV40_PGRAPH_CTXCTL_0310 0x00400310 224 #define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 225 #define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 226 #define NV40_PGRAPH_CTXCTL_030C 0x0040030c 227 #define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 228 #define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 229 #define NV40_PGRAPH_CTXCTL_CUR 0x0040032c 230 #define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 231 #define NV40_PGRAPH_CTXCTL_CUR_INSTANCE 0x000FFFFF 232 #define NV40_PGRAPH_CTXCTL_NEXT 0x00400330 233 #define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE 0x000fffff 234 #define NV50_PGRAPH_CTXCTL_CUR 0x0040032c 235 #define NV50_PGRAPH_CTXCTL_CUR_LOADED 0x80000000 236 #define NV50_PGRAPH_CTXCTL_CUR_INSTANCE 0x00ffffff 237 #define NV50_PGRAPH_CTXCTL_NEXT 0x00400330 238 #define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE 0x00ffffff 239 #define NV03_PGRAPH_ABS_X_RAM 0x00400400 240 #define NV03_PGRAPH_ABS_Y_RAM 0x00400480 241 #define NV03_PGRAPH_X_MISC 0x00400500 242 #define NV03_PGRAPH_Y_MISC 0x00400504 243 #define NV04_PGRAPH_VALID1 0x00400508 244 #define NV04_PGRAPH_SOURCE_COLOR 0x0040050C 245 #define NV04_PGRAPH_MISC24_0 0x00400510 246 #define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 247 #define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 248 #define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C 249 #define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 250 #define NV03_PGRAPH_CLIPX_0 0x00400524 251 #define NV03_PGRAPH_CLIPX_1 0x00400528 252 #define NV03_PGRAPH_CLIPY_0 0x0040052C 253 #define NV03_PGRAPH_CLIPY_1 0x00400530 254 #define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 255 #define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 256 #define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C 257 #define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 258 #define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 259 #define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 260 #define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 261 #define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 262 #define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 263 #define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C 264 #define NV04_PGRAPH_MISC24_1 0x00400570 265 #define NV04_PGRAPH_MISC24_2 0x00400574 266 #define NV04_PGRAPH_VALID2 0x00400578 267 #define NV04_PGRAPH_PASSTHRU_0 0x0040057C 268 #define NV04_PGRAPH_PASSTHRU_1 0x00400580 269 #define NV04_PGRAPH_PASSTHRU_2 0x00400584 270 #define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 271 #define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C 272 #define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 273 #define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 274 #define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 275 #define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C 276 #define NV04_PGRAPH_FORMAT_0 0x004005A8 277 #define NV04_PGRAPH_FORMAT_1 0x004005AC 278 #define NV04_PGRAPH_FILTER_0 0x004005B0 279 #define NV04_PGRAPH_FILTER_1 0x004005B4 280 #define NV03_PGRAPH_MONO_COLOR0 0x00400600 281 #define NV04_PGRAPH_ROP3 0x00400604 282 #define NV04_PGRAPH_BETA_AND 0x00400608 283 #define NV04_PGRAPH_BETA_PREMULT 0x0040060C 284 #define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610 285 #define NV04_PGRAPH_FORMATS 0x00400618 286 #define NV10_PGRAPH_DEBUG_2 0x00400620 287 #define NV04_PGRAPH_BOFFSET0 0x00400640 288 #define NV04_PGRAPH_BOFFSET1 0x00400644 289 #define NV04_PGRAPH_BOFFSET2 0x00400648 290 #define NV04_PGRAPH_BOFFSET3 0x0040064C 291 #define NV04_PGRAPH_BOFFSET4 0x00400650 292 #define NV04_PGRAPH_BOFFSET5 0x00400654 293 #define NV04_PGRAPH_BBASE0 0x00400658 294 #define NV04_PGRAPH_BBASE1 0x0040065C 295 #define NV04_PGRAPH_BBASE2 0x00400660 296 #define NV04_PGRAPH_BBASE3 0x00400664 297 #define NV04_PGRAPH_BBASE4 0x00400668 298 #define NV04_PGRAPH_BBASE5 0x0040066C 299 #define NV04_PGRAPH_BPITCH0 0x00400670 300 #define NV04_PGRAPH_BPITCH1 0x00400674 301 #define NV04_PGRAPH_BPITCH2 0x00400678 302 #define NV04_PGRAPH_BPITCH3 0x0040067C 303 #define NV04_PGRAPH_BPITCH4 0x00400680 304 #define NV04_PGRAPH_BLIMIT0 0x00400684 305 #define NV04_PGRAPH_BLIMIT1 0x00400688 306 #define NV04_PGRAPH_BLIMIT2 0x0040068C 307 #define NV04_PGRAPH_BLIMIT3 0x00400690 308 #define NV04_PGRAPH_BLIMIT4 0x00400694 309 #define NV04_PGRAPH_BLIMIT5 0x00400698 310 #define NV04_PGRAPH_BSWIZZLE2 0x0040069C 311 #define NV04_PGRAPH_BSWIZZLE5 0x004006A0 312 #define NV03_PGRAPH_STATUS 0x004006B0 313 #define NV04_PGRAPH_STATUS 0x00400700 314 #define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 315 #define NV04_PGRAPH_TRAPPED_DATA 0x00400708 316 #define NV04_PGRAPH_SURFACE 0x0040070C 317 #define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C 318 #define NV04_PGRAPH_STATE 0x00400710 319 #define NV10_PGRAPH_SURFACE 0x00400710 320 #define NV04_PGRAPH_NOTIFY 0x00400714 321 #define NV10_PGRAPH_STATE 0x00400714 322 #define NV10_PGRAPH_NOTIFY 0x00400718 323 324 #define NV04_PGRAPH_FIFO 0x00400720 325 326 #define NV04_PGRAPH_BPIXEL 0x00400724 327 #define NV10_PGRAPH_RDI_INDEX 0x00400750 328 #define NV04_PGRAPH_FFINTFC_ST2 0x00400754 329 #define NV10_PGRAPH_RDI_DATA 0x00400754 330 #define NV04_PGRAPH_DMA_PITCH 0x00400760 331 #define NV10_PGRAPH_FFINTFC_ST2 0x00400764 332 #define NV04_PGRAPH_DVD_COLORFMT 0x00400764 333 #define NV04_PGRAPH_SCALED_FORMAT 0x00400768 334 #define NV10_PGRAPH_DMA_PITCH 0x00400770 335 #define NV10_PGRAPH_DVD_COLORFMT 0x00400774 336 #define NV10_PGRAPH_SCALED_FORMAT 0x00400778 337 #define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 338 #define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 339 #define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 340 #define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 341 #define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 342 #define NV04_PGRAPH_PATT_COLOR0 0x00400800 343 #define NV04_PGRAPH_PATT_COLOR1 0x00400804 344 #define NV04_PGRAPH_PATTERN 0x00400808 345 #define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 346 #define NV04_PGRAPH_CHROMA 0x00400814 347 #define NV04_PGRAPH_CONTROL0 0x00400818 348 #define NV04_PGRAPH_CONTROL1 0x0040081C 349 #define NV04_PGRAPH_CONTROL2 0x00400820 350 #define NV04_PGRAPH_BLEND 0x00400824 351 #define NV04_PGRAPH_STORED_FMT 0x00400830 352 #define NV04_PGRAPH_PATT_COLORRAM 0x00400900 353 #define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16)) 354 #define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16)) 355 #define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16)) 356 #define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16)) 357 #define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) 358 #define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) 359 #define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) 360 #define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) 361 #define NV04_PGRAPH_U_RAM 0x00400D00 362 #define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16)) 363 #define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16)) 364 #define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16)) 365 #define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16)) 366 #define NV04_PGRAPH_V_RAM 0x00400D40 367 #define NV04_PGRAPH_W_RAM 0x00400D80 368 #define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 369 #define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 370 #define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 371 #define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C 372 #define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 373 #define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 374 #define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 375 #define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C 376 #define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60 377 #define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64 378 #define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68 379 #define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C 380 #define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 381 #define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 382 #define NV10_PGRAPH_XFMODE0 0x00400F40 383 #define NV10_PGRAPH_XFMODE1 0x00400F44 384 #define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 385 #define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C 386 #define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 387 #define NV10_PGRAPH_PIPE_DATA 0x00400F54 388 #define NV04_PGRAPH_DMA_START_0 0x00401000 389 #define NV04_PGRAPH_DMA_START_1 0x00401004 390 #define NV04_PGRAPH_DMA_LENGTH 0x00401008 391 #define NV04_PGRAPH_DMA_MISC 0x0040100C 392 #define NV04_PGRAPH_DMA_DATA_0 0x00401020 393 #define NV04_PGRAPH_DMA_DATA_1 0x00401024 394 #define NV04_PGRAPH_DMA_RM 0x00401030 395 #define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040 396 #define NV04_PGRAPH_DMA_A_CONTROL 0x00401044 397 #define NV04_PGRAPH_DMA_A_LIMIT 0x00401048 398 #define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C 399 #define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050 400 #define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 401 #define NV04_PGRAPH_DMA_A_OFFSET 0x00401058 402 #define NV04_PGRAPH_DMA_A_SIZE 0x0040105C 403 #define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060 404 #define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080 405 #define NV04_PGRAPH_DMA_B_CONTROL 0x00401084 406 #define NV04_PGRAPH_DMA_B_LIMIT 0x00401088 407 #define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C 408 #define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090 409 #define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 410 #define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 411 #define NV04_PGRAPH_DMA_B_SIZE 0x0040109C 412 #define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 413 #define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16)) 414 #define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16)) 415 #define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16)) 416 #define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16)) 417 418 419 /* It's a guess that this works on NV03. Confirmed on NV04, though */ 420 #define NV04_PFIFO_DELAY_0 0x00002040 421 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044 422 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050 423 #define NV03_PFIFO_INTR_0 0x00002100 424 #define NV03_PFIFO_INTR_EN_0 0x00002140 425 # define NV_PFIFO_INTR_CACHE_ERROR (1<<0) 426 # define NV_PFIFO_INTR_RUNOUT (1<<4) 427 # define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8) 428 # define NV_PFIFO_INTR_DMA_PUSHER (1<<12) 429 # define NV_PFIFO_INTR_DMA_PT (1<<16) 430 # define NV_PFIFO_INTR_SEMAPHORE (1<<20) 431 # define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) 432 #define NV03_PFIFO_RAMHT 0x00002210 433 #define NV03_PFIFO_RAMFC 0x00002214 434 #define NV03_PFIFO_RAMRO 0x00002218 435 #define NV40_PFIFO_RAMFC 0x00002220 436 #define NV03_PFIFO_CACHES 0x00002500 437 #define NV04_PFIFO_MODE 0x00002504 438 #define NV04_PFIFO_DMA 0x00002508 439 #define NV04_PFIFO_SIZE 0x0000250c 440 #define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) 441 #define NV50_PFIFO_CTX_TABLE__SIZE 128 442 #define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) 443 #define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) 444 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF 445 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF 446 #define NV03_PFIFO_CACHE0_PUSH0 0x00003000 447 #define NV03_PFIFO_CACHE0_PULL0 0x00003040 448 #define NV04_PFIFO_CACHE0_PULL0 0x00003050 449 #define NV04_PFIFO_CACHE0_PULL1 0x00003054 450 #define NV03_PFIFO_CACHE1_PUSH0 0x00003200 451 #define NV03_PFIFO_CACHE1_PUSH1 0x00003204 452 #define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8) 453 #define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16) 454 #define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f 455 #define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f 456 #define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f 457 #define NV03_PFIFO_CACHE1_PUT 0x00003210 458 #define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 459 #define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 460 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 461 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 462 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 463 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 464 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 465 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 466 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 467 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 468 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 469 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 470 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 471 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 472 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 473 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 474 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 475 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 476 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 477 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 478 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 479 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 480 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 481 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 482 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 483 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 484 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 485 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 486 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 487 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 488 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 489 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 490 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 491 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 492 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 493 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 494 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 495 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 496 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 497 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 498 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 499 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 500 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 501 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 502 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 503 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 504 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 505 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 506 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 507 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 508 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 509 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 510 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 511 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 512 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 513 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 514 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 515 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 516 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 517 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 518 # define NV_PFIFO_CACHE1_ENDIAN 0x80000000 519 # define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF 520 # define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 521 #define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 522 #define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c 523 #define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 524 #define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 525 #define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 526 #define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 527 #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C 528 #define NV03_PFIFO_CACHE1_PULL0 0x00003240 529 #define NV04_PFIFO_CACHE1_PULL0 0x00003250 530 #define NV03_PFIFO_CACHE1_PULL1 0x00003250 531 #define NV04_PFIFO_CACHE1_PULL1 0x00003254 532 #define NV04_PFIFO_CACHE1_HASH 0x00003258 533 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 534 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 535 #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 536 #define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C 537 #define NV03_PFIFO_CACHE1_GET 0x00003270 538 #define NV04_PFIFO_CACHE1_ENGINE 0x00003280 539 #define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 540 #define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 541 #define NV40_PFIFO_UNK32E4 0x000032E4 542 #define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) 543 #define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) 544 #define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) 545 #define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) 546 547 #define NV_CRTC0_INTSTAT 0x00600100 548 #define NV_CRTC0_INTEN 0x00600140 549 #define NV_CRTC1_INTSTAT 0x00602100 550 #define NV_CRTC1_INTEN 0x00602140 551 # define NV_CRTC_INTR_VBLANK (1<<0) 552 553 #define NV04_PRAMIN 0x00700000 554 555 /* Fifo commands. These are not regs, neither masks */ 556 #define NV03_FIFO_CMD_JUMP 0x20000000 557 #define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc 558 #define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) 559 560 /* This is a partial import from rules-ng, a few things may be duplicated. 561 * Eventually we should completely import everything from rules-ng. 562 * For the moment check rules-ng for docs. 563 */ 564 565 #define NV50_PMC 0x00000000 566 #define NV50_PMC__LEN 0x1 567 #define NV50_PMC__ESIZE 0x2000 568 # define NV50_PMC_BOOT_0 0x00000000 569 # define NV50_PMC_BOOT_0_REVISION 0x000000ff 570 # define NV50_PMC_BOOT_0_REVISION__SHIFT 0 571 # define NV50_PMC_BOOT_0_ARCH 0x0ff00000 572 # define NV50_PMC_BOOT_0_ARCH__SHIFT 20 573 # define NV50_PMC_INTR_0 0x00000100 574 # define NV50_PMC_INTR_0_PFIFO (1<<8) 575 # define NV50_PMC_INTR_0_PGRAPH (1<<12) 576 # define NV50_PMC_INTR_0_PTIMER (1<<20) 577 # define NV50_PMC_INTR_0_HOTPLUG (1<<21) 578 # define NV50_PMC_INTR_0_DISPLAY (1<<26) 579 # define NV50_PMC_INTR_EN_0 0x00000140 580 # define NV50_PMC_INTR_EN_0_MASTER (1<<0) 581 # define NV50_PMC_INTR_EN_0_MASTER_DISABLED (0<<0) 582 # define NV50_PMC_INTR_EN_0_MASTER_ENABLED (1<<0) 583 # define NV50_PMC_ENABLE 0x00000200 584 # define NV50_PMC_ENABLE_PFIFO (1<<8) 585 # define NV50_PMC_ENABLE_PGRAPH (1<<12) 586 587 #define NV50_PCONNECTOR 0x0000e000 588 #define NV50_PCONNECTOR__LEN 0x1 589 #define NV50_PCONNECTOR__ESIZE 0x1000 590 # define NV50_PCONNECTOR_HOTPLUG_INTR 0x0000e050 591 # define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C0 (1<<0) 592 # define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C1 (1<<1) 593 # define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C2 (1<<2) 594 # define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C3 (1<<3) 595 # define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C0 (1<<16) 596 # define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C1 (1<<17) 597 # define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C2 (1<<18) 598 # define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C3 (1<<19) 599 # define NV50_PCONNECTOR_HOTPLUG_CTRL 0x0000e054 600 # define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C0 (1<<0) 601 # define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C1 (1<<1) 602 # define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C2 (1<<2) 603 # define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C3 (1<<3) 604 # define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C0 (1<<16) 605 # define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C1 (1<<17) 606 # define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C2 (1<<18) 607 # define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C3 (1<<19) 608 # define NV50_PCONNECTOR_HOTPLUG_STATE 0x0000e104 609 # define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C0 (1<<2) 610 # define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C1 (1<<6) 611 # define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C2 (1<<10) 612 # define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C3 (1<<14) 613 # define NV50_PCONNECTOR_I2C_PORT_0 0x0000e138 614 # define NV50_PCONNECTOR_I2C_PORT_1 0x0000e150 615 # define NV50_PCONNECTOR_I2C_PORT_2 0x0000e168 616 # define NV50_PCONNECTOR_I2C_PORT_3 0x0000e180 617 # define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240 618 # define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258 619 620 #define NV50_AUXCH_DATA_OUT(i,n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0) 621 #define NV50_AUXCH_DATA_OUT__SIZE 4 622 #define NV50_AUXCH_DATA_IN(i,n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0) 623 #define NV50_AUXCH_DATA_IN__SIZE 4 624 #define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0) 625 #define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4) 626 #define NV50_AUXCH_CTRL_LINKSTAT 0x01000000 627 #define NV50_AUXCH_CTRL_LINKSTAT_NOT_READY 0x00000000 628 #define NV50_AUXCH_CTRL_LINKSTAT_READY 0x01000000 629 #define NV50_AUXCH_CTRL_LINKEN 0x00100000 630 #define NV50_AUXCH_CTRL_LINKEN_DISABLED 0x00000000 631 #define NV50_AUXCH_CTRL_LINKEN_ENABLED 0x00100000 632 #define NV50_AUXCH_CTRL_EXEC 0x00010000 633 #define NV50_AUXCH_CTRL_EXEC_COMPLETE 0x00000000 634 #define NV50_AUXCH_CTRL_EXEC_IN_PROCESS 0x00010000 635 #define NV50_AUXCH_CTRL_CMD 0x0000f000 636 #define NV50_AUXCH_CTRL_CMD_SHIFT 12 637 #define NV50_AUXCH_CTRL_LEN 0x0000000f 638 #define NV50_AUXCH_CTRL_LEN_SHIFT 0 639 #define NV50_AUXCH_STAT(i) ((i) * 0x50 + 0x0000e4e8) 640 #define NV50_AUXCH_STAT_STATE 0x10000000 641 #define NV50_AUXCH_STAT_STATE_NOT_READY 0x00000000 642 #define NV50_AUXCH_STAT_STATE_READY 0x10000000 643 #define NV50_AUXCH_STAT_REPLY 0x000f0000 644 #define NV50_AUXCH_STAT_REPLY_AUX 0x00030000 645 #define NV50_AUXCH_STAT_REPLY_AUX_ACK 0x00000000 646 #define NV50_AUXCH_STAT_REPLY_AUX_NACK 0x00010000 647 #define NV50_AUXCH_STAT_REPLY_AUX_DEFER 0x00020000 648 #define NV50_AUXCH_STAT_REPLY_I2C 0x000c0000 649 #define NV50_AUXCH_STAT_REPLY_I2C_ACK 0x00000000 650 #define NV50_AUXCH_STAT_REPLY_I2C_NACK 0x00040000 651 #define NV50_AUXCH_STAT_REPLY_I2C_DEFER 0x00080000 652 #define NV50_AUXCH_STAT_COUNT 0x0000001f 653 654 #define NV50_PBUS 0x00088000 655 #define NV50_PBUS__LEN 0x1 656 #define NV50_PBUS__ESIZE 0x1000 657 # define NV50_PBUS_PCI_ID 0x00088000 658 # define NV50_PBUS_PCI_ID_VENDOR_ID 0x0000ffff 659 # define NV50_PBUS_PCI_ID_VENDOR_ID__SHIFT 0 660 # define NV50_PBUS_PCI_ID_DEVICE_ID 0xffff0000 661 # define NV50_PBUS_PCI_ID_DEVICE_ID__SHIFT 16 662 663 #define NV50_PFB 0x00100000 664 #define NV50_PFB__LEN 0x1 665 #define NV50_PFB__ESIZE 0x1000 666 667 #define NV50_PEXTDEV 0x00101000 668 #define NV50_PEXTDEV__LEN 0x1 669 #define NV50_PEXTDEV__ESIZE 0x1000 670 671 #define NV50_PROM 0x00300000 672 #define NV50_PROM__LEN 0x1 673 #define NV50_PROM__ESIZE 0x10000 674 675 #define NV50_PGRAPH 0x00400000 676 #define NV50_PGRAPH__LEN 0x1 677 #define NV50_PGRAPH__ESIZE 0x10000 678 679 #define NV50_PDISPLAY 0x00610000 680 #define NV50_PDISPLAY_OBJECTS 0x00610010 681 #define NV50_PDISPLAY_INTR_0 0x00610020 682 #define NV50_PDISPLAY_INTR_1 0x00610024 683 #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC 0x0000000c 684 #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_SHIFT 2 685 #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(n) (1 << ((n) + 2)) 686 #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0 0x00000004 687 #define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1 0x00000008 688 #define NV50_PDISPLAY_INTR_1_CLK_UNK10 0x00000010 689 #define NV50_PDISPLAY_INTR_1_CLK_UNK20 0x00000020 690 #define NV50_PDISPLAY_INTR_1_CLK_UNK40 0x00000040 691 #define NV50_PDISPLAY_INTR_EN 0x0061002c 692 #define NV50_PDISPLAY_INTR_EN_VBLANK_CRTC 0x0000000c 693 #define NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_(n) (1 << ((n) + 2)) 694 #define NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_0 0x00000004 695 #define NV50_PDISPLAY_INTR_EN_VBLANK_CRTC_1 0x00000008 696 #define NV50_PDISPLAY_INTR_EN_CLK_UNK10 0x00000010 697 #define NV50_PDISPLAY_INTR_EN_CLK_UNK20 0x00000020 698 #define NV50_PDISPLAY_INTR_EN_CLK_UNK40 0x00000040 699 #define NV50_PDISPLAY_UNK30_CTRL 0x00610030 700 #define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK0 0x00000200 701 #define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK1 0x00000400 702 #define NV50_PDISPLAY_UNK30_CTRL_PENDING 0x80000000 703 #define NV50_PDISPLAY_TRAPPED_ADDR 0x00610080 704 #define NV50_PDISPLAY_TRAPPED_DATA 0x00610084 705 #define NV50_PDISPLAY_CHANNEL_STAT(i) ((i) * 0x10 + 0x00610200) 706 #define NV50_PDISPLAY_CHANNEL_STAT_DMA 0x00000010 707 #define NV50_PDISPLAY_CHANNEL_STAT_DMA_DISABLED 0x00000000 708 #define NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED 0x00000010 709 #define NV50_PDISPLAY_CHANNEL_DMA_CB(i) ((i) * 0x10 + 0x00610204) 710 #define NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION 0x00000002 711 #define NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM 0x00000000 712 #define NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_SYSTEM 0x00000002 713 #define NV50_PDISPLAY_CHANNEL_DMA_CB_VALID 0x00000001 714 #define NV50_PDISPLAY_CHANNEL_UNK2(i) ((i) * 0x10 + 0x00610208) 715 #define NV50_PDISPLAY_CHANNEL_UNK3(i) ((i) * 0x10 + 0x0061020c) 716 717 #define NV50_PDISPLAY_CURSOR 0x00610270 718 #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) ((i) * 0x10 + 0x00610270) 719 #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON 0x00000001 720 #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS 0x00030000 721 #define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE 0x00010000 722 723 #define NV50_PDISPLAY_CTRL_STATE 0x00610300 724 #define NV50_PDISPLAY_CTRL_STATE_PENDING 0x80000000 725 #define NV50_PDISPLAY_CTRL_STATE_METHOD 0x00001ffc 726 #define NV50_PDISPLAY_CTRL_STATE_ENABLE 0x00000001 727 #define NV50_PDISPLAY_CTRL_VAL 0x00610304 728 #define NV50_PDISPLAY_UNK_380 0x00610380 729 #define NV50_PDISPLAY_RAM_AMOUNT 0x00610384 730 #define NV50_PDISPLAY_UNK_388 0x00610388 731 #define NV50_PDISPLAY_UNK_38C 0x0061038c 732 733 #define NV50_PDISPLAY_CRTC_P(i, r) ((i) * 0x540 + NV50_PDISPLAY_CRTC_##r) 734 #define NV50_PDISPLAY_CRTC_C(i, r) (4 + (i) * 0x540 + NV50_PDISPLAY_CRTC_##r) 735 #define NV50_PDISPLAY_CRTC_UNK_0A18 /* mthd 0x0900 */ 0x00610a18 736 #define NV50_PDISPLAY_CRTC_CLUT_MODE 0x00610a24 737 #define NV50_PDISPLAY_CRTC_INTERLACE 0x00610a48 738 #define NV50_PDISPLAY_CRTC_SCALE_CTRL 0x00610a50 739 #define NV50_PDISPLAY_CRTC_CURSOR_CTRL 0x00610a58 740 #define NV50_PDISPLAY_CRTC_UNK0A78 /* mthd 0x0904 */ 0x00610a78 741 #define NV50_PDISPLAY_CRTC_UNK0AB8 0x00610ab8 742 #define NV50_PDISPLAY_CRTC_DEPTH 0x00610ac8 743 #define NV50_PDISPLAY_CRTC_CLOCK 0x00610ad0 744 #define NV50_PDISPLAY_CRTC_COLOR_CTRL 0x00610ae0 745 #define NV50_PDISPLAY_CRTC_SYNC_START_TO_BLANK_END 0x00610ae8 746 #define NV50_PDISPLAY_CRTC_MODE_UNK1 0x00610af0 747 #define NV50_PDISPLAY_CRTC_DISPLAY_TOTAL 0x00610af8 748 #define NV50_PDISPLAY_CRTC_SYNC_DURATION 0x00610b00 749 #define NV50_PDISPLAY_CRTC_MODE_UNK2 0x00610b08 750 #define NV50_PDISPLAY_CRTC_UNK_0B10 /* mthd 0x0828 */ 0x00610b10 751 #define NV50_PDISPLAY_CRTC_FB_SIZE 0x00610b18 752 #define NV50_PDISPLAY_CRTC_FB_PITCH 0x00610b20 753 #define NV50_PDISPLAY_CRTC_FB_PITCH_LINEAR 0x00100000 754 #define NV50_PDISPLAY_CRTC_FB_POS 0x00610b28 755 #define NV50_PDISPLAY_CRTC_SCALE_CENTER_OFFSET 0x00610b38 756 #define NV50_PDISPLAY_CRTC_REAL_RES 0x00610b40 757 #define NV50_PDISPLAY_CRTC_SCALE_RES1 0x00610b48 758 #define NV50_PDISPLAY_CRTC_SCALE_RES2 0x00610b50 759 760 #define NV50_PDISPLAY_DAC_MODE_CTRL_P(i) (0x00610b58 + (i) * 0x8) 761 #define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) 762 #define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8) 763 #define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8) 764 #define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8) 765 #define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8) 766 767 #define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8) 768 #define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8) 769 #define NV90_PDISPLAY_DAC_MODE_CTRL_P(i) (0x00610b58 + (i) * 0x8) 770 #define NV90_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) 771 #define NV90_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610b80 + (i) * 0x8) 772 #define NV90_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610b84 + (i) * 0x8) 773 774 #define NV50_PDISPLAY_CRTC_CLK 0x00614000 775 #define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100) 776 #define NV50_PDISPLAY_CRTC_CLK_CTRL1_CONNECTED 0x00000600 777 #define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) ((i) * 0x800 + 0x614104) 778 #define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) ((i) * 0x800 + 0x614108) 779 #define NV50_PDISPLAY_CRTC_CLK_CTRL2(i) ((i) * 0x800 + 0x614200) 780 781 #define NV50_PDISPLAY_DAC_CLK 0x00614000 782 #define NV50_PDISPLAY_DAC_CLK_CTRL2(i) ((i) * 0x800 + 0x614280) 783 784 #define NV50_PDISPLAY_SOR_CLK 0x00614000 785 #define NV50_PDISPLAY_SOR_CLK_CTRL2(i) ((i) * 0x800 + 0x614300) 786 787 #define NV50_PDISPLAY_VGACRTC(r) ((r) + 0x619400) 788 789 #define NV50_PDISPLAY_DAC 0x0061a000 790 #define NV50_PDISPLAY_DAC_DPMS_CTRL(i) (0x0061a004 + (i) * 0x800) 791 #define NV50_PDISPLAY_DAC_DPMS_CTRL_HSYNC_OFF 0x00000001 792 #define NV50_PDISPLAY_DAC_DPMS_CTRL_VSYNC_OFF 0x00000004 793 #define NV50_PDISPLAY_DAC_DPMS_CTRL_BLANKED 0x00000010 794 #define NV50_PDISPLAY_DAC_DPMS_CTRL_OFF 0x00000040 795 #define NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING 0x80000000 796 #define NV50_PDISPLAY_DAC_LOAD_CTRL(i) (0x0061a00c + (i) * 0x800) 797 #define NV50_PDISPLAY_DAC_LOAD_CTRL_ACTIVE 0x00100000 798 #define NV50_PDISPLAY_DAC_LOAD_CTRL_PRESENT 0x38000000 799 #define NV50_PDISPLAY_DAC_LOAD_CTRL_DONE 0x80000000 800 #define NV50_PDISPLAY_DAC_CLK_CTRL1(i) (0x0061a010 + (i) * 0x800) 801 #define NV50_PDISPLAY_DAC_CLK_CTRL1_CONNECTED 0x00000600 802 803 #define NV50_PDISPLAY_SOR 0x0061c000 804 #define NV50_PDISPLAY_SOR_DPMS_CTRL(i) (0x0061c004 + (i) * 0x800) 805 #define NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING 0x80000000 806 #define NV50_PDISPLAY_SOR_DPMS_CTRL_ON 0x00000001 807 #define NV50_PDISPLAY_SOR_CLK_CTRL1(i) (0x0061c008 + (i) * 0x800) 808 #define NV50_PDISPLAY_SOR_CLK_CTRL1_CONNECTED 0x00000600 809 #define NV50_PDISPLAY_SOR_DPMS_STATE(i) (0x0061c030 + (i) * 0x800) 810 #define NV50_PDISPLAY_SOR_DPMS_STATE_ACTIVE 0x00030000 811 #define NV50_PDISPLAY_SOR_DPMS_STATE_BLANKED 0x00080000 812 #define NV50_PDISPLAY_SOR_DPMS_STATE_WAIT 0x10000000 813 #define NV50_PDISPLAY_SOR_BACKLIGHT 0x0061c084 814 #define NV50_PDISPLAY_SOR_BACKLIGHT_ENABLE 0x80000000 815 #define NV50_PDISPLAY_SOR_BACKLIGHT_LEVEL 0x00000fff 816 #define NV50_SOR_DP_CTRL(i,l) (0x0061c10c + (i) * 0x800 + (l) * 0x80) 817 #define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000 818 #define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000 819 #define NV50_SOR_DP_CTRL_LANE_0_ENABLED 0x00010000 820 #define NV50_SOR_DP_CTRL_LANE_1_ENABLED 0x00020000 821 #define NV50_SOR_DP_CTRL_LANE_2_ENABLED 0x00040000 822 #define NV50_SOR_DP_CTRL_LANE_3_ENABLED 0x00080000 823 #define NV50_SOR_DP_CTRL_TRAINING_PATTERN 0x0f000000 824 #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED 0x00000000 825 #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 0x01000000 826 #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000 827 #define NV50_SOR_DP_UNK118(i,l) (0x0061c118 + (i) * 0x800 + (l) * 0x80) 828 #define NV50_SOR_DP_UNK120(i,l) (0x0061c120 + (i) * 0x800 + (l) * 0x80) 829 #define NV50_SOR_DP_UNK130(i,l) (0x0061c130 + (i) * 0x800 + (l) * 0x80) 830 831 #define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000) 832 #define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000) 833 #define NV50_PDISPLAY_USER_GET(i) ((i) * 0x1000 + 0x00640004) 834 835 #define NV50_PDISPLAY_CURSOR_USER 0x00647000 836 #define NV50_PDISPLAY_CURSOR_USER_POS_CTRL(i) ((i) * 0x1000 + 0x00647080) 837 #define NV50_PDISPLAY_CURSOR_USER_POS(i) ((i) * 0x1000 + 0x00647084) 838