1 /* 2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 * Copyright 2005 Stephane Marchesin 4 * 5 * The Weather Channel (TM) funded Tungsten Graphics to develop the 6 * initial release of the Radeon 8500 driver under the XFree86 license. 7 * This notice must be preserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the next 17 * paragraph) shall be included in all copies or substantial portions of the 18 * Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 * 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33 #include "drmP.h" 34 #include "drm.h" 35 #include "drm_sarea.h" 36 #include "nouveau_drv.h" 37 38 static struct mem_block * 39 split_block(struct mem_block *p, uint64_t start, uint64_t size, 40 struct drm_file *file_priv) 41 { 42 /* Maybe cut off the start of an existing block */ 43 if (start > p->start) { 44 struct mem_block *newblock = 45 kmalloc(sizeof(*newblock), GFP_KERNEL); 46 if (!newblock) 47 goto out; 48 newblock->start = start; 49 newblock->size = p->size - (start - p->start); 50 newblock->file_priv = NULL; 51 newblock->next = p->next; 52 newblock->prev = p; 53 p->next->prev = newblock; 54 p->next = newblock; 55 p->size -= newblock->size; 56 p = newblock; 57 } 58 59 /* Maybe cut off the end of an existing block */ 60 if (size < p->size) { 61 struct mem_block *newblock = 62 kmalloc(sizeof(*newblock), GFP_KERNEL); 63 if (!newblock) 64 goto out; 65 newblock->start = start + size; 66 newblock->size = p->size - size; 67 newblock->file_priv = NULL; 68 newblock->next = p->next; 69 newblock->prev = p; 70 p->next->prev = newblock; 71 p->next = newblock; 72 p->size = size; 73 } 74 75 out: 76 /* Our block is in the middle */ 77 p->file_priv = file_priv; 78 return p; 79 } 80 81 struct mem_block * 82 nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size, 83 int align2, struct drm_file *file_priv, int tail) 84 { 85 struct mem_block *p; 86 uint64_t mask = (1 << align2) - 1; 87 88 if (!heap) 89 return NULL; 90 91 if (tail) { 92 list_for_each_prev(p, heap) { 93 uint64_t start = ((p->start + p->size) - size) & ~mask; 94 95 if (p->file_priv == NULL && start >= p->start && 96 start + size <= p->start + p->size) 97 return split_block(p, start, size, file_priv); 98 } 99 } else { 100 list_for_each(p, heap) { 101 uint64_t start = (p->start + mask) & ~mask; 102 103 if (p->file_priv == NULL && 104 start + size <= p->start + p->size) 105 return split_block(p, start, size, file_priv); 106 } 107 } 108 109 return NULL; 110 } 111 112 void nouveau_mem_free_block(struct mem_block *p) 113 { 114 p->file_priv = NULL; 115 116 /* Assumes a single contiguous range. Needs a special file_priv in 117 * 'heap' to stop it being subsumed. 118 */ 119 if (p->next->file_priv == NULL) { 120 struct mem_block *q = p->next; 121 p->size += q->size; 122 p->next = q->next; 123 p->next->prev = p; 124 kfree(q); 125 } 126 127 if (p->prev->file_priv == NULL) { 128 struct mem_block *q = p->prev; 129 q->size += p->size; 130 q->next = p->next; 131 q->next->prev = q; 132 kfree(p); 133 } 134 } 135 136 /* Initialize. How to check for an uninitialized heap? 137 */ 138 int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start, 139 uint64_t size) 140 { 141 struct mem_block *blocks = kmalloc(sizeof(*blocks), GFP_KERNEL); 142 143 if (!blocks) 144 return -ENOMEM; 145 146 *heap = kmalloc(sizeof(**heap), GFP_KERNEL); 147 if (!*heap) { 148 kfree(blocks); 149 return -ENOMEM; 150 } 151 152 blocks->start = start; 153 blocks->size = size; 154 blocks->file_priv = NULL; 155 blocks->next = blocks->prev = *heap; 156 157 memset(*heap, 0, sizeof(**heap)); 158 (*heap)->file_priv = (struct drm_file *) -1; 159 (*heap)->next = (*heap)->prev = blocks; 160 return 0; 161 } 162 163 /* 164 * Free all blocks associated with the releasing file_priv 165 */ 166 void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap) 167 { 168 struct mem_block *p; 169 170 if (!heap || !heap->next) 171 return; 172 173 list_for_each(p, heap) { 174 if (p->file_priv == file_priv) 175 p->file_priv = NULL; 176 } 177 178 /* Assumes a single contiguous range. Needs a special file_priv in 179 * 'heap' to stop it being subsumed. 180 */ 181 list_for_each(p, heap) { 182 while ((p->file_priv == NULL) && 183 (p->next->file_priv == NULL) && 184 (p->next != heap)) { 185 struct mem_block *q = p->next; 186 p->size += q->size; 187 p->next = q->next; 188 p->next->prev = p; 189 kfree(q); 190 } 191 } 192 } 193 194 /* 195 * NV10-NV40 tiling helpers 196 */ 197 198 static void 199 nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, 200 uint32_t size, uint32_t pitch) 201 { 202 struct drm_nouveau_private *dev_priv = dev->dev_private; 203 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; 204 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 205 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 206 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; 207 208 tile->addr = addr; 209 tile->size = size; 210 tile->used = !!pitch; 211 nouveau_fence_unref((void **)&tile->fence); 212 213 if (!pfifo->cache_flush(dev)) 214 return; 215 216 pfifo->reassign(dev, false); 217 pfifo->cache_flush(dev); 218 pfifo->cache_pull(dev, false); 219 220 nouveau_wait_for_idle(dev); 221 222 pgraph->set_region_tiling(dev, i, addr, size, pitch); 223 pfb->set_region_tiling(dev, i, addr, size, pitch); 224 225 pfifo->cache_pull(dev, true); 226 pfifo->reassign(dev, true); 227 } 228 229 struct nouveau_tile_reg * 230 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size, 231 uint32_t pitch) 232 { 233 struct drm_nouveau_private *dev_priv = dev->dev_private; 234 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 235 struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL; 236 int i; 237 238 spin_lock(&dev_priv->tile.lock); 239 240 for (i = 0; i < pfb->num_tiles; i++) { 241 if (tile[i].used) 242 /* Tile region in use. */ 243 continue; 244 245 if (tile[i].fence && 246 !nouveau_fence_signalled(tile[i].fence, NULL)) 247 /* Pending tile region. */ 248 continue; 249 250 if (max(tile[i].addr, addr) < 251 min(tile[i].addr + tile[i].size, addr + size)) 252 /* Kill an intersecting tile region. */ 253 nv10_mem_set_region_tiling(dev, i, 0, 0, 0); 254 255 if (pitch && !found) { 256 /* Free tile region. */ 257 nv10_mem_set_region_tiling(dev, i, addr, size, pitch); 258 found = &tile[i]; 259 } 260 } 261 262 spin_unlock(&dev_priv->tile.lock); 263 264 return found; 265 } 266 267 void 268 nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile, 269 struct nouveau_fence *fence) 270 { 271 if (fence) { 272 /* Mark it as pending. */ 273 tile->fence = fence; 274 nouveau_fence_ref(fence); 275 } 276 277 tile->used = false; 278 } 279 280 /* 281 * NV50 VM helpers 282 */ 283 int 284 nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, 285 uint32_t flags, uint64_t phys) 286 { 287 struct drm_nouveau_private *dev_priv = dev->dev_private; 288 struct nouveau_gpuobj *pgt; 289 unsigned block; 290 int i; 291 292 virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1; 293 size = (size >> 16) << 1; 294 295 phys |= ((uint64_t)flags << 32); 296 phys |= 1; 297 if (dev_priv->vram_sys_base) { 298 phys += dev_priv->vram_sys_base; 299 phys |= 0x30; 300 } 301 302 dev_priv->engine.instmem.prepare_access(dev, true); 303 while (size) { 304 unsigned offset_h = upper_32_bits(phys); 305 unsigned offset_l = lower_32_bits(phys); 306 unsigned pte, end; 307 308 for (i = 7; i >= 0; i--) { 309 block = 1 << (i + 1); 310 if (size >= block && !(virt & (block - 1))) 311 break; 312 } 313 offset_l |= (i << 7); 314 315 phys += block << 15; 316 size -= block; 317 318 while (block) { 319 pgt = dev_priv->vm_vram_pt[virt >> 14]; 320 pte = virt & 0x3ffe; 321 322 end = pte + block; 323 if (end > 16384) 324 end = 16384; 325 block -= (end - pte); 326 virt += (end - pte); 327 328 while (pte < end) { 329 nv_wo32(dev, pgt, pte++, offset_l); 330 nv_wo32(dev, pgt, pte++, offset_h); 331 } 332 } 333 } 334 dev_priv->engine.instmem.finish_access(dev); 335 336 nv_wr32(dev, 0x100c80, 0x00050001); 337 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { 338 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); 339 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); 340 return -EBUSY; 341 } 342 343 nv_wr32(dev, 0x100c80, 0x00000001); 344 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { 345 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); 346 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); 347 return -EBUSY; 348 } 349 350 return 0; 351 } 352 353 void 354 nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) 355 { 356 struct drm_nouveau_private *dev_priv = dev->dev_private; 357 struct nouveau_gpuobj *pgt; 358 unsigned pages, pte, end; 359 360 virt -= dev_priv->vm_vram_base; 361 pages = (size >> 16) << 1; 362 363 dev_priv->engine.instmem.prepare_access(dev, true); 364 while (pages) { 365 pgt = dev_priv->vm_vram_pt[virt >> 29]; 366 pte = (virt & 0x1ffe0000ULL) >> 15; 367 368 end = pte + pages; 369 if (end > 16384) 370 end = 16384; 371 pages -= (end - pte); 372 virt += (end - pte) << 15; 373 374 while (pte < end) 375 nv_wo32(dev, pgt, pte++, 0); 376 } 377 dev_priv->engine.instmem.finish_access(dev); 378 379 nv_wr32(dev, 0x100c80, 0x00050001); 380 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { 381 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); 382 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); 383 return; 384 } 385 386 nv_wr32(dev, 0x100c80, 0x00000001); 387 if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { 388 NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); 389 NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); 390 } 391 } 392 393 /* 394 * Cleanup everything 395 */ 396 void nouveau_mem_takedown(struct mem_block **heap) 397 { 398 struct mem_block *p; 399 400 if (!*heap) 401 return; 402 403 for (p = (*heap)->next; p != *heap;) { 404 struct mem_block *q = p; 405 p = p->next; 406 kfree(q); 407 } 408 409 kfree(*heap); 410 *heap = NULL; 411 } 412 413 void nouveau_mem_close(struct drm_device *dev) 414 { 415 struct drm_nouveau_private *dev_priv = dev->dev_private; 416 417 nouveau_bo_unpin(dev_priv->vga_ram); 418 nouveau_bo_ref(NULL, &dev_priv->vga_ram); 419 420 ttm_bo_device_release(&dev_priv->ttm.bdev); 421 422 nouveau_ttm_global_release(dev_priv); 423 424 if (drm_core_has_AGP(dev) && dev->agp && 425 drm_core_check_feature(dev, DRIVER_MODESET)) { 426 struct drm_agp_mem *entry, *tempe; 427 428 /* Remove AGP resources, but leave dev->agp 429 intact until drv_cleanup is called. */ 430 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) { 431 if (entry->bound) 432 drm_unbind_agp(entry->memory); 433 drm_free_agp(entry->memory, entry->pages); 434 kfree(entry); 435 } 436 INIT_LIST_HEAD(&dev->agp->memory); 437 438 if (dev->agp->acquired) 439 drm_agp_release(dev); 440 441 dev->agp->acquired = 0; 442 dev->agp->enabled = 0; 443 } 444 445 if (dev_priv->fb_mtrr) { 446 drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1), 447 drm_get_resource_len(dev, 1), DRM_MTRR_WC); 448 dev_priv->fb_mtrr = 0; 449 } 450 } 451 452 /*XXX won't work on BSD because of pci_read_config_dword */ 453 static uint32_t 454 nouveau_mem_fb_amount_igp(struct drm_device *dev) 455 { 456 struct drm_nouveau_private *dev_priv = dev->dev_private; 457 struct pci_dev *bridge; 458 uint32_t mem; 459 460 bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); 461 if (!bridge) { 462 NV_ERROR(dev, "no bridge device\n"); 463 return 0; 464 } 465 466 if (dev_priv->flags&NV_NFORCE) { 467 pci_read_config_dword(bridge, 0x7C, &mem); 468 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; 469 } else 470 if (dev_priv->flags&NV_NFORCE2) { 471 pci_read_config_dword(bridge, 0x84, &mem); 472 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; 473 } 474 475 NV_ERROR(dev, "impossible!\n"); 476 return 0; 477 } 478 479 /* returns the amount of FB ram in bytes */ 480 uint64_t nouveau_mem_fb_amount(struct drm_device *dev) 481 { 482 struct drm_nouveau_private *dev_priv = dev->dev_private; 483 uint32_t boot0; 484 485 switch (dev_priv->card_type) { 486 case NV_04: 487 boot0 = nv_rd32(dev, NV03_BOOT_0); 488 if (boot0 & 0x00000100) 489 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; 490 491 switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) { 492 case NV04_BOOT_0_RAM_AMOUNT_32MB: 493 return 32 * 1024 * 1024; 494 case NV04_BOOT_0_RAM_AMOUNT_16MB: 495 return 16 * 1024 * 1024; 496 case NV04_BOOT_0_RAM_AMOUNT_8MB: 497 return 8 * 1024 * 1024; 498 case NV04_BOOT_0_RAM_AMOUNT_4MB: 499 return 4 * 1024 * 1024; 500 } 501 break; 502 case NV_10: 503 case NV_20: 504 case NV_30: 505 case NV_40: 506 case NV_50: 507 default: 508 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { 509 return nouveau_mem_fb_amount_igp(dev); 510 } else { 511 uint64_t mem; 512 mem = (nv_rd32(dev, NV04_FIFO_DATA) & 513 NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >> 514 NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT; 515 return mem * 1024 * 1024; 516 } 517 break; 518 } 519 520 NV_ERROR(dev, 521 "Unable to detect video ram size. Please report your setup to " 522 DRIVER_EMAIL "\n"); 523 return 0; 524 } 525 526 #if __OS_HAS_AGP 527 static void nouveau_mem_reset_agp(struct drm_device *dev) 528 { 529 uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable; 530 531 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1); 532 saved_pci_nv_19 = nv_rd32(dev, NV04_PBUS_PCI_NV_19); 533 534 /* clear busmaster bit */ 535 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4); 536 /* clear SBA and AGP bits */ 537 nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff); 538 539 /* power cycle pgraph, if enabled */ 540 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE); 541 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) { 542 nv_wr32(dev, NV03_PMC_ENABLE, 543 pmc_enable & ~NV_PMC_ENABLE_PGRAPH); 544 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | 545 NV_PMC_ENABLE_PGRAPH); 546 } 547 548 /* and restore (gives effect of resetting AGP) */ 549 nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19); 550 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1); 551 } 552 #endif 553 554 int 555 nouveau_mem_init_agp(struct drm_device *dev) 556 { 557 #if __OS_HAS_AGP 558 struct drm_nouveau_private *dev_priv = dev->dev_private; 559 struct drm_agp_info info; 560 struct drm_agp_mode mode; 561 int ret; 562 563 if (nouveau_noagp) 564 return 0; 565 566 nouveau_mem_reset_agp(dev); 567 568 if (!dev->agp->acquired) { 569 ret = drm_agp_acquire(dev); 570 if (ret) { 571 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret); 572 return ret; 573 } 574 } 575 576 ret = drm_agp_info(dev, &info); 577 if (ret) { 578 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret); 579 return ret; 580 } 581 582 /* see agp.h for the AGPSTAT_* modes available */ 583 mode.mode = info.mode; 584 ret = drm_agp_enable(dev, mode); 585 if (ret) { 586 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret); 587 return ret; 588 } 589 590 dev_priv->gart_info.type = NOUVEAU_GART_AGP; 591 dev_priv->gart_info.aper_base = info.aperture_base; 592 dev_priv->gart_info.aper_size = info.aperture_size; 593 #endif 594 return 0; 595 } 596 597 int 598 nouveau_mem_init(struct drm_device *dev) 599 { 600 struct drm_nouveau_private *dev_priv = dev->dev_private; 601 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; 602 int ret, dma_bits = 32; 603 604 dev_priv->fb_phys = drm_get_resource_start(dev, 1); 605 dev_priv->gart_info.type = NOUVEAU_GART_NONE; 606 607 if (dev_priv->card_type >= NV_50 && 608 pci_dma_supported(dev->pdev, DMA_BIT_MASK(40))) 609 dma_bits = 40; 610 611 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits)); 612 if (ret) { 613 NV_ERROR(dev, "Error setting DMA mask: %d\n", ret); 614 return ret; 615 } 616 617 ret = nouveau_ttm_global_init(dev_priv); 618 if (ret) 619 return ret; 620 621 ret = ttm_bo_device_init(&dev_priv->ttm.bdev, 622 dev_priv->ttm.bo_global_ref.ref.object, 623 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET, 624 dma_bits <= 32 ? true : false); 625 if (ret) { 626 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret); 627 return ret; 628 } 629 630 INIT_LIST_HEAD(&dev_priv->ttm.bo_list); 631 spin_lock_init(&dev_priv->ttm.bo_list_lock); 632 spin_lock_init(&dev_priv->tile.lock); 633 634 dev_priv->fb_available_size = nouveau_mem_fb_amount(dev); 635 636 dev_priv->fb_mappable_pages = dev_priv->fb_available_size; 637 if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1)) 638 dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1); 639 dev_priv->fb_mappable_pages >>= PAGE_SHIFT; 640 641 NV_INFO(dev, "%d MiB VRAM\n", (int)(dev_priv->fb_available_size >> 20)); 642 643 /* remove reserved space at end of vram from available amount */ 644 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; 645 dev_priv->fb_aper_free = dev_priv->fb_available_size; 646 647 /* mappable vram */ 648 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM, 649 dev_priv->fb_available_size >> PAGE_SHIFT); 650 if (ret) { 651 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret); 652 return ret; 653 } 654 655 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM, 656 0, 0, true, true, &dev_priv->vga_ram); 657 if (ret == 0) 658 ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM); 659 if (ret) { 660 NV_WARN(dev, "failed to reserve VGA memory\n"); 661 nouveau_bo_ref(NULL, &dev_priv->vga_ram); 662 } 663 664 /* GART */ 665 #if !defined(__powerpc__) && !defined(__ia64__) 666 if (drm_device_is_agp(dev) && dev->agp) { 667 ret = nouveau_mem_init_agp(dev); 668 if (ret) 669 NV_ERROR(dev, "Error initialising AGP: %d\n", ret); 670 } 671 #endif 672 673 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { 674 ret = nouveau_sgdma_init(dev); 675 if (ret) { 676 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret); 677 return ret; 678 } 679 } 680 681 NV_INFO(dev, "%d MiB GART (aperture)\n", 682 (int)(dev_priv->gart_info.aper_size >> 20)); 683 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size; 684 685 ret = ttm_bo_init_mm(bdev, TTM_PL_TT, 686 dev_priv->gart_info.aper_size >> PAGE_SHIFT); 687 if (ret) { 688 NV_ERROR(dev, "Failed TT mm init: %d\n", ret); 689 return ret; 690 } 691 692 dev_priv->fb_mtrr = drm_mtrr_add(drm_get_resource_start(dev, 1), 693 drm_get_resource_len(dev, 1), 694 DRM_MTRR_WC); 695 696 return 0; 697 } 698 699 700