1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRV_H__ 26 #define __NOUVEAU_DRV_H__ 27 28 #define DRIVER_AUTHOR "Stephane Marchesin" 29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31 #define DRIVER_NAME "nouveau" 32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33 #define DRIVER_DATE "20090420" 34 35 #define DRIVER_MAJOR 0 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 16 38 39 #define NOUVEAU_FAMILY 0x0000FFFF 40 #define NOUVEAU_FLAGS 0xFFFF0000 41 42 #include "ttm/ttm_bo_api.h" 43 #include "ttm/ttm_bo_driver.h" 44 #include "ttm/ttm_placement.h" 45 #include "ttm/ttm_memory.h" 46 #include "ttm/ttm_module.h" 47 48 struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52 }; 53 54 static inline struct nouveau_fpriv * 55 nouveau_fpriv(struct drm_file *file_priv) 56 { 57 return file_priv ? file_priv->driver_priv : NULL; 58 } 59 60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62 #include "nouveau_drm.h" 63 #include "nouveau_reg.h" 64 #include "nouveau_bios.h" 65 #include "nouveau_util.h" 66 67 struct nouveau_grctx; 68 struct nouveau_mem; 69 #include "nouveau_vm.h" 70 71 #define MAX_NUM_DCB_ENTRIES 16 72 73 #define NOUVEAU_MAX_CHANNEL_NR 128 74 #define NOUVEAU_MAX_TILE_NR 15 75 76 struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89 }; 90 91 struct nouveau_tile_reg { 92 bool used; 93 uint32_t addr; 94 uint32_t limit; 95 uint32_t pitch; 96 uint32_t zcomp; 97 struct drm_mm_node *tag_mem; 98 struct nouveau_fence *fence; 99 }; 100 101 struct nouveau_bo { 102 struct ttm_buffer_object bo; 103 struct ttm_placement placement; 104 u32 valid_domains; 105 u32 placements[3]; 106 u32 busy_placements[3]; 107 struct ttm_bo_kmap_obj kmap; 108 struct list_head head; 109 110 /* protected by ttm_bo_reserve() */ 111 struct drm_file *reserved_by; 112 struct list_head entry; 113 int pbbo_index; 114 bool validate_mapped; 115 116 struct nouveau_channel *channel; 117 118 struct list_head vma_list; 119 unsigned page_shift; 120 121 uint32_t tile_mode; 122 uint32_t tile_flags; 123 struct nouveau_tile_reg *tile; 124 125 struct drm_gem_object *gem; 126 int pin_refcnt; 127 }; 128 129 #define nouveau_bo_tile_layout(nvbo) \ 130 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 131 132 static inline struct nouveau_bo * 133 nouveau_bo(struct ttm_buffer_object *bo) 134 { 135 return container_of(bo, struct nouveau_bo, bo); 136 } 137 138 static inline struct nouveau_bo * 139 nouveau_gem_object(struct drm_gem_object *gem) 140 { 141 return gem ? gem->driver_private : NULL; 142 } 143 144 /* TODO: submit equivalent to TTM generic API upstream? */ 145 static inline void __iomem * 146 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 147 { 148 bool is_iomem; 149 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 150 &nvbo->kmap, &is_iomem); 151 WARN_ON_ONCE(ioptr && !is_iomem); 152 return ioptr; 153 } 154 155 enum nouveau_flags { 156 NV_NFORCE = 0x10000000, 157 NV_NFORCE2 = 0x20000000 158 }; 159 160 #define NVOBJ_ENGINE_SW 0 161 #define NVOBJ_ENGINE_GR 1 162 #define NVOBJ_ENGINE_CRYPT 2 163 #define NVOBJ_ENGINE_COPY0 3 164 #define NVOBJ_ENGINE_COPY1 4 165 #define NVOBJ_ENGINE_MPEG 5 166 #define NVOBJ_ENGINE_DISPLAY 15 167 #define NVOBJ_ENGINE_NR 16 168 169 #define NVOBJ_FLAG_DONT_MAP (1 << 0) 170 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 171 #define NVOBJ_FLAG_ZERO_FREE (1 << 2) 172 #define NVOBJ_FLAG_VM (1 << 3) 173 #define NVOBJ_FLAG_VM_USER (1 << 4) 174 175 #define NVOBJ_CINST_GLOBAL 0xdeadbeef 176 177 struct nouveau_gpuobj { 178 struct drm_device *dev; 179 struct kref refcount; 180 struct list_head list; 181 182 void *node; 183 u32 *suspend; 184 185 uint32_t flags; 186 187 u32 size; 188 u32 pinst; /* PRAMIN BAR offset */ 189 u32 cinst; /* Channel offset */ 190 u64 vinst; /* VRAM address */ 191 u64 linst; /* VM address */ 192 193 uint32_t engine; 194 uint32_t class; 195 196 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 197 void *priv; 198 }; 199 200 struct nouveau_page_flip_state { 201 struct list_head head; 202 struct drm_pending_vblank_event *event; 203 int crtc, bpp, pitch, x, y; 204 uint64_t offset; 205 }; 206 207 enum nouveau_channel_mutex_class { 208 NOUVEAU_UCHANNEL_MUTEX, 209 NOUVEAU_KCHANNEL_MUTEX 210 }; 211 212 struct nouveau_channel { 213 struct drm_device *dev; 214 struct list_head list; 215 int id; 216 217 /* references to the channel data structure */ 218 struct kref ref; 219 /* users of the hardware channel resources, the hardware 220 * context will be kicked off when it reaches zero. */ 221 atomic_t users; 222 struct mutex mutex; 223 224 /* owner of this fifo */ 225 struct drm_file *file_priv; 226 /* mapping of the fifo itself */ 227 struct drm_local_map *map; 228 229 /* mapping of the regs controlling the fifo */ 230 void __iomem *user; 231 uint32_t user_get; 232 uint32_t user_put; 233 234 /* Fencing */ 235 struct { 236 /* lock protects the pending list only */ 237 spinlock_t lock; 238 struct list_head pending; 239 uint32_t sequence; 240 uint32_t sequence_ack; 241 atomic_t last_sequence_irq; 242 struct nouveau_vma vma; 243 } fence; 244 245 /* DMA push buffer */ 246 struct nouveau_gpuobj *pushbuf; 247 struct nouveau_bo *pushbuf_bo; 248 struct nouveau_vma pushbuf_vma; 249 uint32_t pushbuf_base; 250 251 /* Notifier memory */ 252 struct nouveau_bo *notifier_bo; 253 struct nouveau_vma notifier_vma; 254 struct drm_mm notifier_heap; 255 256 /* PFIFO context */ 257 struct nouveau_gpuobj *ramfc; 258 struct nouveau_gpuobj *cache; 259 void *fifo_priv; 260 261 /* Execution engine contexts */ 262 void *engctx[NVOBJ_ENGINE_NR]; 263 264 /* NV50 VM */ 265 struct nouveau_vm *vm; 266 struct nouveau_gpuobj *vm_pd; 267 268 /* Objects */ 269 struct nouveau_gpuobj *ramin; /* Private instmem */ 270 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 271 struct nouveau_ramht *ramht; /* Hash table */ 272 273 /* GPU object info for stuff used in-kernel (mm_enabled) */ 274 uint32_t m2mf_ntfy; 275 uint32_t vram_handle; 276 uint32_t gart_handle; 277 bool accel_done; 278 279 /* Push buffer state (only for drm's channel on !mm_enabled) */ 280 struct { 281 int max; 282 int free; 283 int cur; 284 int put; 285 /* access via pushbuf_bo */ 286 287 int ib_base; 288 int ib_max; 289 int ib_free; 290 int ib_put; 291 } dma; 292 293 uint32_t sw_subchannel[8]; 294 295 struct nouveau_vma dispc_vma[2]; 296 struct { 297 struct nouveau_gpuobj *vblsem; 298 uint32_t vblsem_head; 299 uint32_t vblsem_offset; 300 uint32_t vblsem_rval; 301 struct list_head vbl_wait; 302 struct list_head flip; 303 } nvsw; 304 305 struct { 306 bool active; 307 char name[32]; 308 struct drm_info_list info; 309 } debugfs; 310 }; 311 312 struct nouveau_exec_engine { 313 void (*destroy)(struct drm_device *, int engine); 314 int (*init)(struct drm_device *, int engine); 315 int (*fini)(struct drm_device *, int engine, bool suspend); 316 int (*context_new)(struct nouveau_channel *, int engine); 317 void (*context_del)(struct nouveau_channel *, int engine); 318 int (*object_new)(struct nouveau_channel *, int engine, 319 u32 handle, u16 class); 320 void (*set_tile_region)(struct drm_device *dev, int i); 321 void (*tlb_flush)(struct drm_device *, int engine); 322 }; 323 324 struct nouveau_instmem_engine { 325 void *priv; 326 327 int (*init)(struct drm_device *dev); 328 void (*takedown)(struct drm_device *dev); 329 int (*suspend)(struct drm_device *dev); 330 void (*resume)(struct drm_device *dev); 331 332 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 333 u32 size, u32 align); 334 void (*put)(struct nouveau_gpuobj *); 335 int (*map)(struct nouveau_gpuobj *); 336 void (*unmap)(struct nouveau_gpuobj *); 337 338 void (*flush)(struct drm_device *); 339 }; 340 341 struct nouveau_mc_engine { 342 int (*init)(struct drm_device *dev); 343 void (*takedown)(struct drm_device *dev); 344 }; 345 346 struct nouveau_timer_engine { 347 int (*init)(struct drm_device *dev); 348 void (*takedown)(struct drm_device *dev); 349 uint64_t (*read)(struct drm_device *dev); 350 }; 351 352 struct nouveau_fb_engine { 353 int num_tiles; 354 struct drm_mm tag_heap; 355 void *priv; 356 357 int (*init)(struct drm_device *dev); 358 void (*takedown)(struct drm_device *dev); 359 360 void (*init_tile_region)(struct drm_device *dev, int i, 361 uint32_t addr, uint32_t size, 362 uint32_t pitch, uint32_t flags); 363 void (*set_tile_region)(struct drm_device *dev, int i); 364 void (*free_tile_region)(struct drm_device *dev, int i); 365 }; 366 367 struct nouveau_fifo_engine { 368 void *priv; 369 int channels; 370 371 struct nouveau_gpuobj *playlist[2]; 372 int cur_playlist; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*disable)(struct drm_device *); 378 void (*enable)(struct drm_device *); 379 bool (*reassign)(struct drm_device *, bool enable); 380 bool (*cache_pull)(struct drm_device *dev, bool enable); 381 382 int (*channel_id)(struct drm_device *); 383 384 int (*create_context)(struct nouveau_channel *); 385 void (*destroy_context)(struct nouveau_channel *); 386 int (*load_context)(struct nouveau_channel *); 387 int (*unload_context)(struct drm_device *); 388 void (*tlb_flush)(struct drm_device *dev); 389 }; 390 391 struct nouveau_display_engine { 392 void *priv; 393 int (*early_init)(struct drm_device *); 394 void (*late_takedown)(struct drm_device *); 395 int (*create)(struct drm_device *); 396 int (*init)(struct drm_device *); 397 void (*destroy)(struct drm_device *); 398 }; 399 400 struct nouveau_gpio_engine { 401 void *priv; 402 403 int (*init)(struct drm_device *); 404 void (*takedown)(struct drm_device *); 405 406 int (*get)(struct drm_device *, enum dcb_gpio_tag); 407 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 408 409 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 410 void (*)(void *, int), void *); 411 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 412 void (*)(void *, int), void *); 413 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 414 }; 415 416 struct nouveau_pm_voltage_level { 417 u8 voltage; 418 u8 vid; 419 }; 420 421 struct nouveau_pm_voltage { 422 bool supported; 423 u8 vid_mask; 424 425 struct nouveau_pm_voltage_level *level; 426 int nr_level; 427 }; 428 429 struct nouveau_pm_memtiming { 430 int id; 431 u32 reg_100220; 432 u32 reg_100224; 433 u32 reg_100228; 434 u32 reg_10022c; 435 u32 reg_100230; 436 u32 reg_100234; 437 u32 reg_100238; 438 u32 reg_10023c; 439 u32 reg_100240; 440 }; 441 442 #define NOUVEAU_PM_MAX_LEVEL 8 443 struct nouveau_pm_level { 444 struct device_attribute dev_attr; 445 char name[32]; 446 int id; 447 448 u32 core; 449 u32 memory; 450 u32 shader; 451 u32 unk05; 452 u32 unk0a; 453 454 u8 voltage; 455 u8 fanspeed; 456 457 u16 memscript; 458 struct nouveau_pm_memtiming *timing; 459 }; 460 461 struct nouveau_pm_temp_sensor_constants { 462 u16 offset_constant; 463 s16 offset_mult; 464 s16 offset_div; 465 s16 slope_mult; 466 s16 slope_div; 467 }; 468 469 struct nouveau_pm_threshold_temp { 470 s16 critical; 471 s16 down_clock; 472 s16 fan_boost; 473 }; 474 475 struct nouveau_pm_memtimings { 476 bool supported; 477 struct nouveau_pm_memtiming *timing; 478 int nr_timing; 479 }; 480 481 struct nouveau_pm_engine { 482 struct nouveau_pm_voltage voltage; 483 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 484 int nr_perflvl; 485 struct nouveau_pm_memtimings memtimings; 486 struct nouveau_pm_temp_sensor_constants sensor_constants; 487 struct nouveau_pm_threshold_temp threshold_temp; 488 489 struct nouveau_pm_level boot; 490 struct nouveau_pm_level *cur; 491 492 struct device *hwmon; 493 struct notifier_block acpi_nb; 494 495 int (*clock_get)(struct drm_device *, u32 id); 496 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 497 u32 id, int khz); 498 void (*clock_set)(struct drm_device *, void *); 499 int (*voltage_get)(struct drm_device *); 500 int (*voltage_set)(struct drm_device *, int voltage); 501 int (*fanspeed_get)(struct drm_device *); 502 int (*fanspeed_set)(struct drm_device *, int fanspeed); 503 int (*temp_get)(struct drm_device *); 504 }; 505 506 struct nouveau_vram_engine { 507 struct nouveau_mm *mm; 508 509 int (*init)(struct drm_device *); 510 void (*takedown)(struct drm_device *dev); 511 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 512 u32 type, struct nouveau_mem **); 513 void (*put)(struct drm_device *, struct nouveau_mem **); 514 515 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 516 }; 517 518 struct nouveau_engine { 519 struct nouveau_instmem_engine instmem; 520 struct nouveau_mc_engine mc; 521 struct nouveau_timer_engine timer; 522 struct nouveau_fb_engine fb; 523 struct nouveau_fifo_engine fifo; 524 struct nouveau_display_engine display; 525 struct nouveau_gpio_engine gpio; 526 struct nouveau_pm_engine pm; 527 struct nouveau_vram_engine vram; 528 }; 529 530 struct nouveau_pll_vals { 531 union { 532 struct { 533 #ifdef __BIG_ENDIAN 534 uint8_t N1, M1, N2, M2; 535 #else 536 uint8_t M1, N1, M2, N2; 537 #endif 538 }; 539 struct { 540 uint16_t NM1, NM2; 541 } __attribute__((packed)); 542 }; 543 int log2P; 544 545 int refclk; 546 }; 547 548 enum nv04_fp_display_regs { 549 FP_DISPLAY_END, 550 FP_TOTAL, 551 FP_CRTC, 552 FP_SYNC_START, 553 FP_SYNC_END, 554 FP_VALID_START, 555 FP_VALID_END 556 }; 557 558 struct nv04_crtc_reg { 559 unsigned char MiscOutReg; 560 uint8_t CRTC[0xa0]; 561 uint8_t CR58[0x10]; 562 uint8_t Sequencer[5]; 563 uint8_t Graphics[9]; 564 uint8_t Attribute[21]; 565 unsigned char DAC[768]; 566 567 /* PCRTC regs */ 568 uint32_t fb_start; 569 uint32_t crtc_cfg; 570 uint32_t cursor_cfg; 571 uint32_t gpio_ext; 572 uint32_t crtc_830; 573 uint32_t crtc_834; 574 uint32_t crtc_850; 575 uint32_t crtc_eng_ctrl; 576 577 /* PRAMDAC regs */ 578 uint32_t nv10_cursync; 579 struct nouveau_pll_vals pllvals; 580 uint32_t ramdac_gen_ctrl; 581 uint32_t ramdac_630; 582 uint32_t ramdac_634; 583 uint32_t tv_setup; 584 uint32_t tv_vtotal; 585 uint32_t tv_vskew; 586 uint32_t tv_vsync_delay; 587 uint32_t tv_htotal; 588 uint32_t tv_hskew; 589 uint32_t tv_hsync_delay; 590 uint32_t tv_hsync_delay2; 591 uint32_t fp_horiz_regs[7]; 592 uint32_t fp_vert_regs[7]; 593 uint32_t dither; 594 uint32_t fp_control; 595 uint32_t dither_regs[6]; 596 uint32_t fp_debug_0; 597 uint32_t fp_debug_1; 598 uint32_t fp_debug_2; 599 uint32_t fp_margin_color; 600 uint32_t ramdac_8c0; 601 uint32_t ramdac_a20; 602 uint32_t ramdac_a24; 603 uint32_t ramdac_a34; 604 uint32_t ctv_regs[38]; 605 }; 606 607 struct nv04_output_reg { 608 uint32_t output; 609 int head; 610 }; 611 612 struct nv04_mode_state { 613 struct nv04_crtc_reg crtc_reg[2]; 614 uint32_t pllsel; 615 uint32_t sel_clk; 616 }; 617 618 enum nouveau_card_type { 619 NV_04 = 0x00, 620 NV_10 = 0x10, 621 NV_20 = 0x20, 622 NV_30 = 0x30, 623 NV_40 = 0x40, 624 NV_50 = 0x50, 625 NV_C0 = 0xc0, 626 }; 627 628 struct drm_nouveau_private { 629 struct drm_device *dev; 630 bool noaccel; 631 632 /* the card type, takes NV_* as values */ 633 enum nouveau_card_type card_type; 634 /* exact chipset, derived from NV_PMC_BOOT_0 */ 635 int chipset; 636 int stepping; 637 int flags; 638 639 void __iomem *mmio; 640 641 spinlock_t ramin_lock; 642 void __iomem *ramin; 643 u32 ramin_size; 644 u32 ramin_base; 645 bool ramin_available; 646 struct drm_mm ramin_heap; 647 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 648 struct list_head gpuobj_list; 649 struct list_head classes; 650 651 struct nouveau_bo *vga_ram; 652 653 /* interrupt handling */ 654 void (*irq_handler[32])(struct drm_device *); 655 bool msi_enabled; 656 657 struct list_head vbl_waiting; 658 659 struct { 660 struct drm_global_reference mem_global_ref; 661 struct ttm_bo_global_ref bo_global_ref; 662 struct ttm_bo_device bdev; 663 atomic_t validate_sequence; 664 } ttm; 665 666 struct { 667 spinlock_t lock; 668 struct drm_mm heap; 669 struct nouveau_bo *bo; 670 } fence; 671 672 struct { 673 spinlock_t lock; 674 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 675 } channels; 676 677 struct nouveau_engine engine; 678 struct nouveau_channel *channel; 679 680 /* For PFIFO and PGRAPH. */ 681 spinlock_t context_switch_lock; 682 683 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 684 spinlock_t vm_lock; 685 686 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 687 struct nouveau_ramht *ramht; 688 struct nouveau_gpuobj *ramfc; 689 struct nouveau_gpuobj *ramro; 690 691 uint32_t ramin_rsvd_vram; 692 693 struct { 694 enum { 695 NOUVEAU_GART_NONE = 0, 696 NOUVEAU_GART_AGP, /* AGP */ 697 NOUVEAU_GART_PDMA, /* paged dma object */ 698 NOUVEAU_GART_HW /* on-chip gart/vm */ 699 } type; 700 uint64_t aper_base; 701 uint64_t aper_size; 702 uint64_t aper_free; 703 704 struct ttm_backend_func *func; 705 706 struct { 707 struct page *page; 708 dma_addr_t addr; 709 } dummy; 710 711 struct nouveau_gpuobj *sg_ctxdma; 712 } gart_info; 713 714 /* nv10-nv40 tiling regions */ 715 struct { 716 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 717 spinlock_t lock; 718 } tile; 719 720 /* VRAM/fb configuration */ 721 uint64_t vram_size; 722 uint64_t vram_sys_base; 723 724 uint64_t fb_phys; 725 uint64_t fb_available_size; 726 uint64_t fb_mappable_pages; 727 uint64_t fb_aper_free; 728 int fb_mtrr; 729 730 /* BAR control (NV50-) */ 731 struct nouveau_vm *bar1_vm; 732 struct nouveau_vm *bar3_vm; 733 734 /* G8x/G9x virtual address space */ 735 struct nouveau_vm *chan_vm; 736 737 struct nvbios vbios; 738 739 struct nv04_mode_state mode_reg; 740 struct nv04_mode_state saved_reg; 741 uint32_t saved_vga_font[4][16384]; 742 uint32_t crtc_owner; 743 uint32_t dac_users[4]; 744 745 struct backlight_device *backlight; 746 747 struct { 748 struct dentry *channel_root; 749 } debugfs; 750 751 struct nouveau_fbdev *nfbdev; 752 struct apertures_struct *apertures; 753 }; 754 755 static inline struct drm_nouveau_private * 756 nouveau_private(struct drm_device *dev) 757 { 758 return dev->dev_private; 759 } 760 761 static inline struct drm_nouveau_private * 762 nouveau_bdev(struct ttm_bo_device *bd) 763 { 764 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 765 } 766 767 static inline int 768 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 769 { 770 struct nouveau_bo *prev; 771 772 if (!pnvbo) 773 return -EINVAL; 774 prev = *pnvbo; 775 776 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 777 if (prev) { 778 struct ttm_buffer_object *bo = &prev->bo; 779 780 ttm_bo_unref(&bo); 781 } 782 783 return 0; 784 } 785 786 /* nouveau_drv.c */ 787 extern int nouveau_agpmode; 788 extern int nouveau_duallink; 789 extern int nouveau_uscript_lvds; 790 extern int nouveau_uscript_tmds; 791 extern int nouveau_vram_pushbuf; 792 extern int nouveau_vram_notify; 793 extern int nouveau_fbpercrtc; 794 extern int nouveau_tv_disable; 795 extern char *nouveau_tv_norm; 796 extern int nouveau_reg_debug; 797 extern char *nouveau_vbios; 798 extern int nouveau_ignorelid; 799 extern int nouveau_nofbaccel; 800 extern int nouveau_noaccel; 801 extern int nouveau_force_post; 802 extern int nouveau_override_conntype; 803 extern char *nouveau_perflvl; 804 extern int nouveau_perflvl_wr; 805 extern int nouveau_msi; 806 extern int nouveau_ctxfw; 807 808 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 809 extern int nouveau_pci_resume(struct pci_dev *pdev); 810 811 /* nouveau_state.c */ 812 extern int nouveau_open(struct drm_device *, struct drm_file *); 813 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 814 extern void nouveau_postclose(struct drm_device *, struct drm_file *); 815 extern int nouveau_load(struct drm_device *, unsigned long flags); 816 extern int nouveau_firstopen(struct drm_device *); 817 extern void nouveau_lastclose(struct drm_device *); 818 extern int nouveau_unload(struct drm_device *); 819 extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 820 struct drm_file *); 821 extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 822 struct drm_file *); 823 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 824 uint32_t reg, uint32_t mask, uint32_t val); 825 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 826 uint32_t reg, uint32_t mask, uint32_t val); 827 extern bool nouveau_wait_for_idle(struct drm_device *); 828 extern int nouveau_card_init(struct drm_device *); 829 830 /* nouveau_mem.c */ 831 extern int nouveau_mem_vram_init(struct drm_device *); 832 extern void nouveau_mem_vram_fini(struct drm_device *); 833 extern int nouveau_mem_gart_init(struct drm_device *); 834 extern void nouveau_mem_gart_fini(struct drm_device *); 835 extern int nouveau_mem_init_agp(struct drm_device *); 836 extern int nouveau_mem_reset_agp(struct drm_device *); 837 extern void nouveau_mem_close(struct drm_device *); 838 extern int nouveau_mem_detect(struct drm_device *); 839 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 840 extern struct nouveau_tile_reg *nv10_mem_set_tiling( 841 struct drm_device *dev, uint32_t addr, uint32_t size, 842 uint32_t pitch, uint32_t flags); 843 extern void nv10_mem_put_tile_region(struct drm_device *dev, 844 struct nouveau_tile_reg *tile, 845 struct nouveau_fence *fence); 846 extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 847 extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 848 849 /* nouveau_notifier.c */ 850 extern int nouveau_notifier_init_channel(struct nouveau_channel *); 851 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 852 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 853 int cout, uint32_t start, uint32_t end, 854 uint32_t *offset); 855 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 856 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 857 struct drm_file *); 858 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 859 struct drm_file *); 860 861 /* nouveau_channel.c */ 862 extern struct drm_ioctl_desc nouveau_ioctls[]; 863 extern int nouveau_max_ioctl; 864 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 865 extern int nouveau_channel_alloc(struct drm_device *dev, 866 struct nouveau_channel **chan, 867 struct drm_file *file_priv, 868 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 869 extern struct nouveau_channel * 870 nouveau_channel_get_unlocked(struct nouveau_channel *); 871 extern struct nouveau_channel * 872 nouveau_channel_get(struct drm_file *, int id); 873 extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 874 extern void nouveau_channel_put(struct nouveau_channel **); 875 extern void nouveau_channel_ref(struct nouveau_channel *chan, 876 struct nouveau_channel **pchan); 877 extern void nouveau_channel_idle(struct nouveau_channel *chan); 878 879 /* nouveau_object.c */ 880 #define NVOBJ_ENGINE_ADD(d, e, p) do { \ 881 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 882 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 883 } while (0) 884 885 #define NVOBJ_ENGINE_DEL(d, e) do { \ 886 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 887 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 888 } while (0) 889 890 #define NVOBJ_CLASS(d, c, e) do { \ 891 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 892 if (ret) \ 893 return ret; \ 894 } while (0) 895 896 #define NVOBJ_MTHD(d, c, m, e) do { \ 897 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 898 if (ret) \ 899 return ret; \ 900 } while (0) 901 902 extern int nouveau_gpuobj_early_init(struct drm_device *); 903 extern int nouveau_gpuobj_init(struct drm_device *); 904 extern void nouveau_gpuobj_takedown(struct drm_device *); 905 extern int nouveau_gpuobj_suspend(struct drm_device *dev); 906 extern void nouveau_gpuobj_resume(struct drm_device *dev); 907 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 908 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 909 int (*exec)(struct nouveau_channel *, 910 u32 class, u32 mthd, u32 data)); 911 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 912 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 913 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 914 uint32_t vram_h, uint32_t tt_h); 915 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 916 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 917 uint32_t size, int align, uint32_t flags, 918 struct nouveau_gpuobj **); 919 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 920 struct nouveau_gpuobj **); 921 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 922 u32 size, u32 flags, 923 struct nouveau_gpuobj **); 924 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 925 uint64_t offset, uint64_t size, int access, 926 int target, struct nouveau_gpuobj **); 927 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 928 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 929 u64 size, int target, int access, u32 type, 930 u32 comp, struct nouveau_gpuobj **pobj); 931 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 932 int class, u64 base, u64 size, int target, 933 int access, u32 type, u32 comp); 934 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 935 struct drm_file *); 936 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 937 struct drm_file *); 938 939 /* nouveau_irq.c */ 940 extern int nouveau_irq_init(struct drm_device *); 941 extern void nouveau_irq_fini(struct drm_device *); 942 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 943 extern void nouveau_irq_register(struct drm_device *, int status_bit, 944 void (*)(struct drm_device *)); 945 extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 946 extern void nouveau_irq_preinstall(struct drm_device *); 947 extern int nouveau_irq_postinstall(struct drm_device *); 948 extern void nouveau_irq_uninstall(struct drm_device *); 949 950 /* nouveau_sgdma.c */ 951 extern int nouveau_sgdma_init(struct drm_device *); 952 extern void nouveau_sgdma_takedown(struct drm_device *); 953 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 954 uint32_t offset); 955 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 956 957 /* nouveau_debugfs.c */ 958 #if defined(CONFIG_DRM_NOUVEAU_DEBUG) 959 extern int nouveau_debugfs_init(struct drm_minor *); 960 extern void nouveau_debugfs_takedown(struct drm_minor *); 961 extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 962 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 963 #else 964 static inline int 965 nouveau_debugfs_init(struct drm_minor *minor) 966 { 967 return 0; 968 } 969 970 static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 971 { 972 } 973 974 static inline int 975 nouveau_debugfs_channel_init(struct nouveau_channel *chan) 976 { 977 return 0; 978 } 979 980 static inline void 981 nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 982 { 983 } 984 #endif 985 986 /* nouveau_dma.c */ 987 extern void nouveau_dma_pre_init(struct nouveau_channel *); 988 extern int nouveau_dma_init(struct nouveau_channel *); 989 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 990 991 /* nouveau_acpi.c */ 992 #define ROM_BIOS_PAGE 4096 993 #if defined(CONFIG_ACPI) 994 void nouveau_register_dsm_handler(void); 995 void nouveau_unregister_dsm_handler(void); 996 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 997 bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 998 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 999 #else 1000 static inline void nouveau_register_dsm_handler(void) {} 1001 static inline void nouveau_unregister_dsm_handler(void) {} 1002 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1003 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1004 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1005 #endif 1006 1007 /* nouveau_backlight.c */ 1008 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1009 extern int nouveau_backlight_init(struct drm_connector *); 1010 extern void nouveau_backlight_exit(struct drm_connector *); 1011 #else 1012 static inline int nouveau_backlight_init(struct drm_connector *dev) 1013 { 1014 return 0; 1015 } 1016 1017 static inline void nouveau_backlight_exit(struct drm_connector *dev) { } 1018 #endif 1019 1020 /* nouveau_bios.c */ 1021 extern int nouveau_bios_init(struct drm_device *); 1022 extern void nouveau_bios_takedown(struct drm_device *dev); 1023 extern int nouveau_run_vbios_init(struct drm_device *); 1024 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1025 struct dcb_entry *); 1026 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1027 enum dcb_gpio_tag); 1028 extern struct dcb_connector_table_entry * 1029 nouveau_bios_connector_entry(struct drm_device *, int index); 1030 extern u32 get_pll_register(struct drm_device *, enum pll_types); 1031 extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1032 struct pll_lims *); 1033 extern int nouveau_bios_run_display_table(struct drm_device *, 1034 struct dcb_entry *, 1035 uint32_t script, int pxclk); 1036 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1037 int *length); 1038 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1039 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1040 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1041 bool *dl, bool *if_is_24bit); 1042 extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1043 int head, int pxclk); 1044 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1045 enum LVDS_script, int pxclk); 1046 1047 /* nouveau_ttm.c */ 1048 int nouveau_ttm_global_init(struct drm_nouveau_private *); 1049 void nouveau_ttm_global_release(struct drm_nouveau_private *); 1050 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1051 1052 /* nouveau_dp.c */ 1053 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1054 uint8_t *data, int data_nr); 1055 bool nouveau_dp_detect(struct drm_encoder *); 1056 bool nouveau_dp_link_train(struct drm_encoder *); 1057 1058 /* nv04_fb.c */ 1059 extern int nv04_fb_init(struct drm_device *); 1060 extern void nv04_fb_takedown(struct drm_device *); 1061 1062 /* nv10_fb.c */ 1063 extern int nv10_fb_init(struct drm_device *); 1064 extern void nv10_fb_takedown(struct drm_device *); 1065 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1066 uint32_t addr, uint32_t size, 1067 uint32_t pitch, uint32_t flags); 1068 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1069 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1070 1071 /* nv30_fb.c */ 1072 extern int nv30_fb_init(struct drm_device *); 1073 extern void nv30_fb_takedown(struct drm_device *); 1074 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1075 uint32_t addr, uint32_t size, 1076 uint32_t pitch, uint32_t flags); 1077 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1078 1079 /* nv40_fb.c */ 1080 extern int nv40_fb_init(struct drm_device *); 1081 extern void nv40_fb_takedown(struct drm_device *); 1082 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1083 1084 /* nv50_fb.c */ 1085 extern int nv50_fb_init(struct drm_device *); 1086 extern void nv50_fb_takedown(struct drm_device *); 1087 extern void nv50_fb_vm_trap(struct drm_device *, int display); 1088 1089 /* nvc0_fb.c */ 1090 extern int nvc0_fb_init(struct drm_device *); 1091 extern void nvc0_fb_takedown(struct drm_device *); 1092 1093 /* nv04_fifo.c */ 1094 extern int nv04_fifo_init(struct drm_device *); 1095 extern void nv04_fifo_fini(struct drm_device *); 1096 extern void nv04_fifo_disable(struct drm_device *); 1097 extern void nv04_fifo_enable(struct drm_device *); 1098 extern bool nv04_fifo_reassign(struct drm_device *, bool); 1099 extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1100 extern int nv04_fifo_channel_id(struct drm_device *); 1101 extern int nv04_fifo_create_context(struct nouveau_channel *); 1102 extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1103 extern int nv04_fifo_load_context(struct nouveau_channel *); 1104 extern int nv04_fifo_unload_context(struct drm_device *); 1105 extern void nv04_fifo_isr(struct drm_device *); 1106 1107 /* nv10_fifo.c */ 1108 extern int nv10_fifo_init(struct drm_device *); 1109 extern int nv10_fifo_channel_id(struct drm_device *); 1110 extern int nv10_fifo_create_context(struct nouveau_channel *); 1111 extern int nv10_fifo_load_context(struct nouveau_channel *); 1112 extern int nv10_fifo_unload_context(struct drm_device *); 1113 1114 /* nv40_fifo.c */ 1115 extern int nv40_fifo_init(struct drm_device *); 1116 extern int nv40_fifo_create_context(struct nouveau_channel *); 1117 extern int nv40_fifo_load_context(struct nouveau_channel *); 1118 extern int nv40_fifo_unload_context(struct drm_device *); 1119 1120 /* nv50_fifo.c */ 1121 extern int nv50_fifo_init(struct drm_device *); 1122 extern void nv50_fifo_takedown(struct drm_device *); 1123 extern int nv50_fifo_channel_id(struct drm_device *); 1124 extern int nv50_fifo_create_context(struct nouveau_channel *); 1125 extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1126 extern int nv50_fifo_load_context(struct nouveau_channel *); 1127 extern int nv50_fifo_unload_context(struct drm_device *); 1128 extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1129 1130 /* nvc0_fifo.c */ 1131 extern int nvc0_fifo_init(struct drm_device *); 1132 extern void nvc0_fifo_takedown(struct drm_device *); 1133 extern void nvc0_fifo_disable(struct drm_device *); 1134 extern void nvc0_fifo_enable(struct drm_device *); 1135 extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1136 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1137 extern int nvc0_fifo_channel_id(struct drm_device *); 1138 extern int nvc0_fifo_create_context(struct nouveau_channel *); 1139 extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1140 extern int nvc0_fifo_load_context(struct nouveau_channel *); 1141 extern int nvc0_fifo_unload_context(struct drm_device *); 1142 1143 /* nv04_graph.c */ 1144 extern int nv04_graph_create(struct drm_device *); 1145 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1146 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1147 u32 class, u32 mthd, u32 data); 1148 extern struct nouveau_bitfield nv04_graph_nsource[]; 1149 1150 /* nv10_graph.c */ 1151 extern int nv10_graph_create(struct drm_device *); 1152 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1153 extern struct nouveau_bitfield nv10_graph_intr[]; 1154 extern struct nouveau_bitfield nv10_graph_nstatus[]; 1155 1156 /* nv20_graph.c */ 1157 extern int nv20_graph_create(struct drm_device *); 1158 1159 /* nv40_graph.c */ 1160 extern int nv40_graph_create(struct drm_device *); 1161 extern void nv40_grctx_init(struct nouveau_grctx *); 1162 1163 /* nv50_graph.c */ 1164 extern int nv50_graph_create(struct drm_device *); 1165 extern int nv50_grctx_init(struct nouveau_grctx *); 1166 extern struct nouveau_enum nv50_data_error_names[]; 1167 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1168 1169 /* nvc0_graph.c */ 1170 extern int nvc0_graph_create(struct drm_device *); 1171 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1172 1173 /* nv84_crypt.c */ 1174 extern int nv84_crypt_create(struct drm_device *); 1175 1176 /* nva3_copy.c */ 1177 extern int nva3_copy_create(struct drm_device *dev); 1178 1179 /* nvc0_copy.c */ 1180 extern int nvc0_copy_create(struct drm_device *dev, int engine); 1181 1182 /* nv40_mpeg.c */ 1183 extern int nv40_mpeg_create(struct drm_device *dev); 1184 1185 /* nv50_mpeg.c */ 1186 extern int nv50_mpeg_create(struct drm_device *dev); 1187 1188 /* nv04_instmem.c */ 1189 extern int nv04_instmem_init(struct drm_device *); 1190 extern void nv04_instmem_takedown(struct drm_device *); 1191 extern int nv04_instmem_suspend(struct drm_device *); 1192 extern void nv04_instmem_resume(struct drm_device *); 1193 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1194 u32 size, u32 align); 1195 extern void nv04_instmem_put(struct nouveau_gpuobj *); 1196 extern int nv04_instmem_map(struct nouveau_gpuobj *); 1197 extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1198 extern void nv04_instmem_flush(struct drm_device *); 1199 1200 /* nv50_instmem.c */ 1201 extern int nv50_instmem_init(struct drm_device *); 1202 extern void nv50_instmem_takedown(struct drm_device *); 1203 extern int nv50_instmem_suspend(struct drm_device *); 1204 extern void nv50_instmem_resume(struct drm_device *); 1205 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1206 u32 size, u32 align); 1207 extern void nv50_instmem_put(struct nouveau_gpuobj *); 1208 extern int nv50_instmem_map(struct nouveau_gpuobj *); 1209 extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1210 extern void nv50_instmem_flush(struct drm_device *); 1211 extern void nv84_instmem_flush(struct drm_device *); 1212 1213 /* nvc0_instmem.c */ 1214 extern int nvc0_instmem_init(struct drm_device *); 1215 extern void nvc0_instmem_takedown(struct drm_device *); 1216 extern int nvc0_instmem_suspend(struct drm_device *); 1217 extern void nvc0_instmem_resume(struct drm_device *); 1218 1219 /* nv04_mc.c */ 1220 extern int nv04_mc_init(struct drm_device *); 1221 extern void nv04_mc_takedown(struct drm_device *); 1222 1223 /* nv40_mc.c */ 1224 extern int nv40_mc_init(struct drm_device *); 1225 extern void nv40_mc_takedown(struct drm_device *); 1226 1227 /* nv50_mc.c */ 1228 extern int nv50_mc_init(struct drm_device *); 1229 extern void nv50_mc_takedown(struct drm_device *); 1230 1231 /* nv04_timer.c */ 1232 extern int nv04_timer_init(struct drm_device *); 1233 extern uint64_t nv04_timer_read(struct drm_device *); 1234 extern void nv04_timer_takedown(struct drm_device *); 1235 1236 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1237 unsigned long arg); 1238 1239 /* nv04_dac.c */ 1240 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1241 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1242 extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1243 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1244 extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1245 1246 /* nv04_dfp.c */ 1247 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1248 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1249 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1250 int head, bool dl); 1251 extern void nv04_dfp_disable(struct drm_device *dev, int head); 1252 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1253 1254 /* nv04_tv.c */ 1255 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1256 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1257 1258 /* nv17_tv.c */ 1259 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1260 1261 /* nv04_display.c */ 1262 extern int nv04_display_early_init(struct drm_device *); 1263 extern void nv04_display_late_takedown(struct drm_device *); 1264 extern int nv04_display_create(struct drm_device *); 1265 extern int nv04_display_init(struct drm_device *); 1266 extern void nv04_display_destroy(struct drm_device *); 1267 1268 /* nv04_crtc.c */ 1269 extern int nv04_crtc_create(struct drm_device *, int index); 1270 1271 /* nouveau_bo.c */ 1272 extern struct ttm_bo_driver nouveau_bo_driver; 1273 extern int nouveau_bo_new(struct drm_device *, int size, int align, 1274 uint32_t flags, uint32_t tile_mode, 1275 uint32_t tile_flags, struct nouveau_bo **); 1276 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1277 extern int nouveau_bo_unpin(struct nouveau_bo *); 1278 extern int nouveau_bo_map(struct nouveau_bo *); 1279 extern void nouveau_bo_unmap(struct nouveau_bo *); 1280 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1281 uint32_t busy); 1282 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1283 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1284 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1285 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1286 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1287 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1288 bool no_wait_reserve, bool no_wait_gpu); 1289 1290 extern struct nouveau_vma * 1291 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1292 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1293 struct nouveau_vma *); 1294 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1295 1296 /* nouveau_fence.c */ 1297 struct nouveau_fence; 1298 extern int nouveau_fence_init(struct drm_device *); 1299 extern void nouveau_fence_fini(struct drm_device *); 1300 extern int nouveau_fence_channel_init(struct nouveau_channel *); 1301 extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1302 extern void nouveau_fence_update(struct nouveau_channel *); 1303 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1304 bool emit); 1305 extern int nouveau_fence_emit(struct nouveau_fence *); 1306 extern void nouveau_fence_work(struct nouveau_fence *fence, 1307 void (*work)(void *priv, bool signalled), 1308 void *priv); 1309 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1310 1311 extern bool __nouveau_fence_signalled(void *obj, void *arg); 1312 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1313 extern int __nouveau_fence_flush(void *obj, void *arg); 1314 extern void __nouveau_fence_unref(void **obj); 1315 extern void *__nouveau_fence_ref(void *obj); 1316 1317 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1318 { 1319 return __nouveau_fence_signalled(obj, NULL); 1320 } 1321 static inline int 1322 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1323 { 1324 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1325 } 1326 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1327 static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1328 { 1329 return __nouveau_fence_flush(obj, NULL); 1330 } 1331 static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1332 { 1333 __nouveau_fence_unref((void **)obj); 1334 } 1335 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1336 { 1337 return __nouveau_fence_ref(obj); 1338 } 1339 1340 /* nouveau_gem.c */ 1341 extern int nouveau_gem_new(struct drm_device *, int size, int align, 1342 uint32_t domain, uint32_t tile_mode, 1343 uint32_t tile_flags, struct nouveau_bo **); 1344 extern int nouveau_gem_object_new(struct drm_gem_object *); 1345 extern void nouveau_gem_object_del(struct drm_gem_object *); 1346 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1347 extern void nouveau_gem_object_close(struct drm_gem_object *, 1348 struct drm_file *); 1349 extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1350 struct drm_file *); 1351 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1352 struct drm_file *); 1353 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1354 struct drm_file *); 1355 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1356 struct drm_file *); 1357 extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1358 struct drm_file *); 1359 1360 /* nouveau_display.c */ 1361 int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1362 void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1363 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1364 struct drm_pending_vblank_event *event); 1365 int nouveau_finish_page_flip(struct nouveau_channel *, 1366 struct nouveau_page_flip_state *); 1367 1368 /* nv10_gpio.c */ 1369 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1370 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1371 1372 /* nv50_gpio.c */ 1373 int nv50_gpio_init(struct drm_device *dev); 1374 void nv50_gpio_fini(struct drm_device *dev); 1375 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1376 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1377 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1378 void (*)(void *, int), void *); 1379 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1380 void (*)(void *, int), void *); 1381 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1382 1383 /* nv50_calc. */ 1384 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1385 int *N1, int *M1, int *N2, int *M2, int *P); 1386 int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1387 int clk, int *N, int *fN, int *M, int *P); 1388 1389 #ifndef ioread32_native 1390 #ifdef __BIG_ENDIAN 1391 #define ioread16_native ioread16be 1392 #define iowrite16_native iowrite16be 1393 #define ioread32_native ioread32be 1394 #define iowrite32_native iowrite32be 1395 #else /* def __BIG_ENDIAN */ 1396 #define ioread16_native ioread16 1397 #define iowrite16_native iowrite16 1398 #define ioread32_native ioread32 1399 #define iowrite32_native iowrite32 1400 #endif /* def __BIG_ENDIAN else */ 1401 #endif /* !ioread32_native */ 1402 1403 /* channel control reg access */ 1404 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1405 { 1406 return ioread32_native(chan->user + reg); 1407 } 1408 1409 static inline void nvchan_wr32(struct nouveau_channel *chan, 1410 unsigned reg, u32 val) 1411 { 1412 iowrite32_native(val, chan->user + reg); 1413 } 1414 1415 /* register access */ 1416 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1417 { 1418 struct drm_nouveau_private *dev_priv = dev->dev_private; 1419 return ioread32_native(dev_priv->mmio + reg); 1420 } 1421 1422 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1423 { 1424 struct drm_nouveau_private *dev_priv = dev->dev_private; 1425 iowrite32_native(val, dev_priv->mmio + reg); 1426 } 1427 1428 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1429 { 1430 u32 tmp = nv_rd32(dev, reg); 1431 nv_wr32(dev, reg, (tmp & ~mask) | val); 1432 return tmp; 1433 } 1434 1435 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1436 { 1437 struct drm_nouveau_private *dev_priv = dev->dev_private; 1438 return ioread8(dev_priv->mmio + reg); 1439 } 1440 1441 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1442 { 1443 struct drm_nouveau_private *dev_priv = dev->dev_private; 1444 iowrite8(val, dev_priv->mmio + reg); 1445 } 1446 1447 #define nv_wait(dev, reg, mask, val) \ 1448 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1449 #define nv_wait_ne(dev, reg, mask, val) \ 1450 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1451 1452 /* PRAMIN access */ 1453 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1454 { 1455 struct drm_nouveau_private *dev_priv = dev->dev_private; 1456 return ioread32_native(dev_priv->ramin + offset); 1457 } 1458 1459 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1460 { 1461 struct drm_nouveau_private *dev_priv = dev->dev_private; 1462 iowrite32_native(val, dev_priv->ramin + offset); 1463 } 1464 1465 /* object access */ 1466 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1467 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1468 1469 /* 1470 * Logging 1471 * Argument d is (struct drm_device *). 1472 */ 1473 #define NV_PRINTK(level, d, fmt, arg...) \ 1474 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1475 pci_name(d->pdev), ##arg) 1476 #ifndef NV_DEBUG_NOTRACE 1477 #define NV_DEBUG(d, fmt, arg...) do { \ 1478 if (drm_debug & DRM_UT_DRIVER) { \ 1479 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1480 __LINE__, ##arg); \ 1481 } \ 1482 } while (0) 1483 #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1484 if (drm_debug & DRM_UT_KMS) { \ 1485 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1486 __LINE__, ##arg); \ 1487 } \ 1488 } while (0) 1489 #else 1490 #define NV_DEBUG(d, fmt, arg...) do { \ 1491 if (drm_debug & DRM_UT_DRIVER) \ 1492 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1493 } while (0) 1494 #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1495 if (drm_debug & DRM_UT_KMS) \ 1496 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1497 } while (0) 1498 #endif 1499 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1500 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1501 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1502 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1503 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1504 1505 /* nouveau_reg_debug bitmask */ 1506 enum { 1507 NOUVEAU_REG_DEBUG_MC = 0x1, 1508 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1509 NOUVEAU_REG_DEBUG_FB = 0x4, 1510 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1511 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1512 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1513 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1514 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1515 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1516 NOUVEAU_REG_DEBUG_EVO = 0x200, 1517 }; 1518 1519 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1520 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1521 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1522 } while (0) 1523 1524 static inline bool 1525 nv_two_heads(struct drm_device *dev) 1526 { 1527 struct drm_nouveau_private *dev_priv = dev->dev_private; 1528 const int impl = dev->pci_device & 0x0ff0; 1529 1530 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1531 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1532 return true; 1533 1534 return false; 1535 } 1536 1537 static inline bool 1538 nv_gf4_disp_arch(struct drm_device *dev) 1539 { 1540 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1541 } 1542 1543 static inline bool 1544 nv_two_reg_pll(struct drm_device *dev) 1545 { 1546 struct drm_nouveau_private *dev_priv = dev->dev_private; 1547 const int impl = dev->pci_device & 0x0ff0; 1548 1549 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1550 return true; 1551 return false; 1552 } 1553 1554 static inline bool 1555 nv_match_device(struct drm_device *dev, unsigned device, 1556 unsigned sub_vendor, unsigned sub_device) 1557 { 1558 return dev->pdev->device == device && 1559 dev->pdev->subsystem_vendor == sub_vendor && 1560 dev->pdev->subsystem_device == sub_device; 1561 } 1562 1563 static inline void * 1564 nv_engine(struct drm_device *dev, int engine) 1565 { 1566 struct drm_nouveau_private *dev_priv = dev->dev_private; 1567 return (void *)dev_priv->eng[engine]; 1568 } 1569 1570 /* returns 1 if device is one of the nv4x using the 0x4497 object class, 1571 * helpful to determine a number of other hardware features 1572 */ 1573 static inline int 1574 nv44_graph_class(struct drm_device *dev) 1575 { 1576 struct drm_nouveau_private *dev_priv = dev->dev_private; 1577 1578 if ((dev_priv->chipset & 0xf0) == 0x60) 1579 return 1; 1580 1581 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1582 } 1583 1584 /* memory type/access flags, do not match hardware values */ 1585 #define NV_MEM_ACCESS_RO 1 1586 #define NV_MEM_ACCESS_WO 2 1587 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1588 #define NV_MEM_ACCESS_SYS 4 1589 #define NV_MEM_ACCESS_VM 8 1590 1591 #define NV_MEM_TARGET_VRAM 0 1592 #define NV_MEM_TARGET_PCI 1 1593 #define NV_MEM_TARGET_PCI_NOSNOOP 2 1594 #define NV_MEM_TARGET_VM 3 1595 #define NV_MEM_TARGET_GART 4 1596 1597 #define NV_MEM_TYPE_VM 0x7f 1598 #define NV_MEM_COMP_VM 0x03 1599 1600 /* NV_SW object class */ 1601 #define NV_SW 0x0000506e 1602 #define NV_SW_DMA_SEMAPHORE 0x00000060 1603 #define NV_SW_SEMAPHORE_OFFSET 0x00000064 1604 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1605 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1606 #define NV_SW_YIELD 0x00000080 1607 #define NV_SW_DMA_VBLSEM 0x0000018c 1608 #define NV_SW_VBLSEM_OFFSET 0x00000400 1609 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1610 #define NV_SW_VBLSEM_RELEASE 0x00000408 1611 #define NV_SW_PAGE_FLIP 0x00000500 1612 1613 #endif /* __NOUVEAU_DRV_H__ */ 1614