1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRV_H__ 26 #define __NOUVEAU_DRV_H__ 27 28 #define DRIVER_AUTHOR "Stephane Marchesin" 29 #define DRIVER_EMAIL "nouveau@lists.freedesktop.org" 30 31 #define DRIVER_NAME "nouveau" 32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33 #define DRIVER_DATE "20120316" 34 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 0 38 39 #define NOUVEAU_FAMILY 0x0000FFFF 40 #define NOUVEAU_FLAGS 0xFFFF0000 41 42 #include "ttm/ttm_bo_api.h" 43 #include "ttm/ttm_bo_driver.h" 44 #include "ttm/ttm_placement.h" 45 #include "ttm/ttm_memory.h" 46 #include "ttm/ttm_module.h" 47 48 struct nouveau_fpriv { 49 spinlock_t lock; 50 struct list_head channels; 51 struct nouveau_vm *vm; 52 }; 53 54 static inline struct nouveau_fpriv * 55 nouveau_fpriv(struct drm_file *file_priv) 56 { 57 return file_priv ? file_priv->driver_priv : NULL; 58 } 59 60 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 61 62 #include "nouveau_drm.h" 63 #include "nouveau_reg.h" 64 #include "nouveau_bios.h" 65 #include "nouveau_util.h" 66 67 struct nouveau_grctx; 68 struct nouveau_mem; 69 #include "nouveau_vm.h" 70 71 #define MAX_NUM_DCB_ENTRIES 16 72 73 #define NOUVEAU_MAX_CHANNEL_NR 4096 74 #define NOUVEAU_MAX_TILE_NR 15 75 76 struct nouveau_mem { 77 struct drm_device *dev; 78 79 struct nouveau_vma bar_vma; 80 struct nouveau_vma vma[2]; 81 u8 page_shift; 82 83 struct drm_mm_node *tag; 84 struct list_head regions; 85 dma_addr_t *pages; 86 u32 memtype; 87 u64 offset; 88 u64 size; 89 struct sg_table *sg; 90 }; 91 92 struct nouveau_tile_reg { 93 bool used; 94 uint32_t addr; 95 uint32_t limit; 96 uint32_t pitch; 97 uint32_t zcomp; 98 struct drm_mm_node *tag_mem; 99 struct nouveau_fence *fence; 100 }; 101 102 struct nouveau_bo { 103 struct ttm_buffer_object bo; 104 struct ttm_placement placement; 105 u32 valid_domains; 106 u32 placements[3]; 107 u32 busy_placements[3]; 108 struct ttm_bo_kmap_obj kmap; 109 struct list_head head; 110 111 /* protected by ttm_bo_reserve() */ 112 struct drm_file *reserved_by; 113 struct list_head entry; 114 int pbbo_index; 115 bool validate_mapped; 116 117 struct list_head vma_list; 118 unsigned page_shift; 119 120 uint32_t tile_mode; 121 uint32_t tile_flags; 122 struct nouveau_tile_reg *tile; 123 124 struct drm_gem_object *gem; 125 int pin_refcnt; 126 127 struct ttm_bo_kmap_obj dma_buf_vmap; 128 int vmapping_count; 129 }; 130 131 #define nouveau_bo_tile_layout(nvbo) \ 132 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 133 134 static inline struct nouveau_bo * 135 nouveau_bo(struct ttm_buffer_object *bo) 136 { 137 return container_of(bo, struct nouveau_bo, bo); 138 } 139 140 static inline struct nouveau_bo * 141 nouveau_gem_object(struct drm_gem_object *gem) 142 { 143 return gem ? gem->driver_private : NULL; 144 } 145 146 /* TODO: submit equivalent to TTM generic API upstream? */ 147 static inline void __iomem * 148 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 149 { 150 bool is_iomem; 151 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 152 &nvbo->kmap, &is_iomem); 153 WARN_ON_ONCE(ioptr && !is_iomem); 154 return ioptr; 155 } 156 157 enum nouveau_flags { 158 NV_NFORCE = 0x10000000, 159 NV_NFORCE2 = 0x20000000 160 }; 161 162 #define NVOBJ_ENGINE_SW 0 163 #define NVOBJ_ENGINE_GR 1 164 #define NVOBJ_ENGINE_CRYPT 2 165 #define NVOBJ_ENGINE_COPY0 3 166 #define NVOBJ_ENGINE_COPY1 4 167 #define NVOBJ_ENGINE_MPEG 5 168 #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG 169 #define NVOBJ_ENGINE_BSP 6 170 #define NVOBJ_ENGINE_VP 7 171 #define NVOBJ_ENGINE_FIFO 14 172 #define NVOBJ_ENGINE_FENCE 15 173 #define NVOBJ_ENGINE_NR 16 174 #define NVOBJ_ENGINE_DISPLAY (NVOBJ_ENGINE_NR + 0) /*XXX*/ 175 176 #define NVOBJ_FLAG_DONT_MAP (1 << 0) 177 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 178 #define NVOBJ_FLAG_ZERO_FREE (1 << 2) 179 #define NVOBJ_FLAG_VM (1 << 3) 180 #define NVOBJ_FLAG_VM_USER (1 << 4) 181 182 #define NVOBJ_CINST_GLOBAL 0xdeadbeef 183 184 struct nouveau_gpuobj { 185 struct drm_device *dev; 186 struct kref refcount; 187 struct list_head list; 188 189 void *node; 190 u32 *suspend; 191 192 uint32_t flags; 193 194 u32 size; 195 u32 pinst; /* PRAMIN BAR offset */ 196 u32 cinst; /* Channel offset */ 197 u64 vinst; /* VRAM address */ 198 u64 linst; /* VM address */ 199 200 uint32_t engine; 201 uint32_t class; 202 203 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 204 void *priv; 205 }; 206 207 struct nouveau_page_flip_state { 208 struct list_head head; 209 struct drm_pending_vblank_event *event; 210 int crtc, bpp, pitch, x, y; 211 uint64_t offset; 212 }; 213 214 enum nouveau_channel_mutex_class { 215 NOUVEAU_UCHANNEL_MUTEX, 216 NOUVEAU_KCHANNEL_MUTEX 217 }; 218 219 struct nouveau_channel { 220 struct drm_device *dev; 221 struct list_head list; 222 int id; 223 224 /* references to the channel data structure */ 225 struct kref ref; 226 /* users of the hardware channel resources, the hardware 227 * context will be kicked off when it reaches zero. */ 228 atomic_t users; 229 struct mutex mutex; 230 231 /* owner of this fifo */ 232 struct drm_file *file_priv; 233 /* mapping of the fifo itself */ 234 struct drm_local_map *map; 235 236 /* mapping of the regs controlling the fifo */ 237 void __iomem *user; 238 uint32_t user_get; 239 uint32_t user_get_hi; 240 uint32_t user_put; 241 242 /* DMA push buffer */ 243 struct nouveau_gpuobj *pushbuf; 244 struct nouveau_bo *pushbuf_bo; 245 struct nouveau_vma pushbuf_vma; 246 uint64_t pushbuf_base; 247 248 /* Notifier memory */ 249 struct nouveau_bo *notifier_bo; 250 struct nouveau_vma notifier_vma; 251 struct drm_mm notifier_heap; 252 253 /* PFIFO context */ 254 struct nouveau_gpuobj *ramfc; 255 256 /* Execution engine contexts */ 257 void *engctx[NVOBJ_ENGINE_NR]; 258 259 /* NV50 VM */ 260 struct nouveau_vm *vm; 261 struct nouveau_gpuobj *vm_pd; 262 263 /* Objects */ 264 struct nouveau_gpuobj *ramin; /* Private instmem */ 265 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 266 struct nouveau_ramht *ramht; /* Hash table */ 267 268 /* GPU object info for stuff used in-kernel (mm_enabled) */ 269 uint32_t m2mf_ntfy; 270 uint32_t vram_handle; 271 uint32_t gart_handle; 272 bool accel_done; 273 274 /* Push buffer state (only for drm's channel on !mm_enabled) */ 275 struct { 276 int max; 277 int free; 278 int cur; 279 int put; 280 /* access via pushbuf_bo */ 281 282 int ib_base; 283 int ib_max; 284 int ib_free; 285 int ib_put; 286 } dma; 287 288 struct { 289 bool active; 290 char name[32]; 291 struct drm_info_list info; 292 } debugfs; 293 }; 294 295 struct nouveau_exec_engine { 296 void (*destroy)(struct drm_device *, int engine); 297 int (*init)(struct drm_device *, int engine); 298 int (*fini)(struct drm_device *, int engine, bool suspend); 299 int (*context_new)(struct nouveau_channel *, int engine); 300 void (*context_del)(struct nouveau_channel *, int engine); 301 int (*object_new)(struct nouveau_channel *, int engine, 302 u32 handle, u16 class); 303 void (*set_tile_region)(struct drm_device *dev, int i); 304 void (*tlb_flush)(struct drm_device *, int engine); 305 }; 306 307 struct nouveau_instmem_engine { 308 void *priv; 309 310 int (*init)(struct drm_device *dev); 311 void (*takedown)(struct drm_device *dev); 312 int (*suspend)(struct drm_device *dev); 313 void (*resume)(struct drm_device *dev); 314 315 int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, 316 u32 size, u32 align); 317 void (*put)(struct nouveau_gpuobj *); 318 int (*map)(struct nouveau_gpuobj *); 319 void (*unmap)(struct nouveau_gpuobj *); 320 321 void (*flush)(struct drm_device *); 322 }; 323 324 struct nouveau_mc_engine { 325 int (*init)(struct drm_device *dev); 326 void (*takedown)(struct drm_device *dev); 327 }; 328 329 struct nouveau_timer_engine { 330 int (*init)(struct drm_device *dev); 331 void (*takedown)(struct drm_device *dev); 332 uint64_t (*read)(struct drm_device *dev); 333 }; 334 335 struct nouveau_fb_engine { 336 int num_tiles; 337 struct drm_mm tag_heap; 338 void *priv; 339 340 int (*init)(struct drm_device *dev); 341 void (*takedown)(struct drm_device *dev); 342 343 void (*init_tile_region)(struct drm_device *dev, int i, 344 uint32_t addr, uint32_t size, 345 uint32_t pitch, uint32_t flags); 346 void (*set_tile_region)(struct drm_device *dev, int i); 347 void (*free_tile_region)(struct drm_device *dev, int i); 348 }; 349 350 struct nouveau_display_engine { 351 void *priv; 352 int (*early_init)(struct drm_device *); 353 void (*late_takedown)(struct drm_device *); 354 int (*create)(struct drm_device *); 355 void (*destroy)(struct drm_device *); 356 int (*init)(struct drm_device *); 357 void (*fini)(struct drm_device *); 358 359 struct drm_property *dithering_mode; 360 struct drm_property *dithering_depth; 361 struct drm_property *underscan_property; 362 struct drm_property *underscan_hborder_property; 363 struct drm_property *underscan_vborder_property; 364 /* not really hue and saturation: */ 365 struct drm_property *vibrant_hue_property; 366 struct drm_property *color_vibrance_property; 367 }; 368 369 struct nouveau_gpio_engine { 370 spinlock_t lock; 371 struct list_head isr; 372 int (*init)(struct drm_device *); 373 void (*fini)(struct drm_device *); 374 int (*drive)(struct drm_device *, int line, int dir, int out); 375 int (*sense)(struct drm_device *, int line); 376 void (*irq_enable)(struct drm_device *, int line, bool); 377 }; 378 379 struct nouveau_pm_voltage_level { 380 u32 voltage; /* microvolts */ 381 u8 vid; 382 }; 383 384 struct nouveau_pm_voltage { 385 bool supported; 386 u8 version; 387 u8 vid_mask; 388 389 struct nouveau_pm_voltage_level *level; 390 int nr_level; 391 }; 392 393 /* Exclusive upper limits */ 394 #define NV_MEM_CL_DDR2_MAX 8 395 #define NV_MEM_WR_DDR2_MAX 9 396 #define NV_MEM_CL_DDR3_MAX 17 397 #define NV_MEM_WR_DDR3_MAX 17 398 #define NV_MEM_CL_GDDR3_MAX 16 399 #define NV_MEM_WR_GDDR3_MAX 18 400 #define NV_MEM_CL_GDDR5_MAX 21 401 #define NV_MEM_WR_GDDR5_MAX 20 402 403 struct nouveau_pm_memtiming { 404 int id; 405 406 u32 reg[9]; 407 u32 mr[4]; 408 409 u8 tCWL; 410 411 u8 odt; 412 u8 drive_strength; 413 }; 414 415 struct nouveau_pm_tbl_header { 416 u8 version; 417 u8 header_len; 418 u8 entry_cnt; 419 u8 entry_len; 420 }; 421 422 struct nouveau_pm_tbl_entry { 423 u8 tWR; 424 u8 tWTR; 425 u8 tCL; 426 u8 tRC; 427 u8 empty_4; 428 u8 tRFC; /* Byte 5 */ 429 u8 empty_6; 430 u8 tRAS; /* Byte 7 */ 431 u8 empty_8; 432 u8 tRP; /* Byte 9 */ 433 u8 tRCDRD; 434 u8 tRCDWR; 435 u8 tRRD; 436 u8 tUNK_13; 437 u8 RAM_FT1; /* 14, a bitmask of random RAM features */ 438 u8 empty_15; 439 u8 tUNK_16; 440 u8 empty_17; 441 u8 tUNK_18; 442 u8 tCWL; 443 u8 tUNK_20, tUNK_21; 444 }; 445 446 struct nouveau_pm_profile; 447 struct nouveau_pm_profile_func { 448 void (*destroy)(struct nouveau_pm_profile *); 449 void (*init)(struct nouveau_pm_profile *); 450 void (*fini)(struct nouveau_pm_profile *); 451 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *); 452 }; 453 454 struct nouveau_pm_profile { 455 const struct nouveau_pm_profile_func *func; 456 struct list_head head; 457 char name[8]; 458 }; 459 460 #define NOUVEAU_PM_MAX_LEVEL 8 461 struct nouveau_pm_level { 462 struct nouveau_pm_profile profile; 463 struct device_attribute dev_attr; 464 char name[32]; 465 int id; 466 467 struct nouveau_pm_memtiming timing; 468 u32 memory; 469 u16 memscript; 470 471 u32 core; 472 u32 shader; 473 u32 rop; 474 u32 copy; 475 u32 daemon; 476 u32 vdec; 477 u32 dom6; 478 u32 unka0; /* nva3:nvc0 */ 479 u32 hub01; /* nvc0- */ 480 u32 hub06; /* nvc0- */ 481 u32 hub07; /* nvc0- */ 482 483 u32 volt_min; /* microvolts */ 484 u32 volt_max; 485 u8 fanspeed; 486 }; 487 488 struct nouveau_pm_temp_sensor_constants { 489 u16 offset_constant; 490 s16 offset_mult; 491 s16 offset_div; 492 s16 slope_mult; 493 s16 slope_div; 494 }; 495 496 struct nouveau_pm_threshold_temp { 497 s16 critical; 498 s16 down_clock; 499 s16 fan_boost; 500 }; 501 502 struct nouveau_pm_fan { 503 u32 percent; 504 u32 min_duty; 505 u32 max_duty; 506 u32 pwm_freq; 507 u32 pwm_divisor; 508 }; 509 510 struct nouveau_pm_engine { 511 struct nouveau_pm_voltage voltage; 512 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 513 int nr_perflvl; 514 struct nouveau_pm_temp_sensor_constants sensor_constants; 515 struct nouveau_pm_threshold_temp threshold_temp; 516 struct nouveau_pm_fan fan; 517 518 struct nouveau_pm_profile *profile_ac; 519 struct nouveau_pm_profile *profile_dc; 520 struct nouveau_pm_profile *profile; 521 struct list_head profiles; 522 523 struct nouveau_pm_level boot; 524 struct nouveau_pm_level *cur; 525 526 struct device *hwmon; 527 struct notifier_block acpi_nb; 528 529 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); 530 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); 531 int (*clocks_set)(struct drm_device *, void *); 532 533 int (*voltage_get)(struct drm_device *); 534 int (*voltage_set)(struct drm_device *, int voltage); 535 int (*pwm_get)(struct drm_device *, int line, u32*, u32*); 536 int (*pwm_set)(struct drm_device *, int line, u32, u32); 537 int (*temp_get)(struct drm_device *); 538 }; 539 540 struct nouveau_vram_engine { 541 struct nouveau_mm mm; 542 543 int (*init)(struct drm_device *); 544 void (*takedown)(struct drm_device *dev); 545 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 546 u32 type, struct nouveau_mem **); 547 void (*put)(struct drm_device *, struct nouveau_mem **); 548 549 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 550 }; 551 552 struct nouveau_engine { 553 struct nouveau_instmem_engine instmem; 554 struct nouveau_mc_engine mc; 555 struct nouveau_timer_engine timer; 556 struct nouveau_fb_engine fb; 557 struct nouveau_display_engine display; 558 struct nouveau_gpio_engine gpio; 559 struct nouveau_pm_engine pm; 560 struct nouveau_vram_engine vram; 561 }; 562 563 struct nouveau_pll_vals { 564 union { 565 struct { 566 #ifdef __BIG_ENDIAN 567 uint8_t N1, M1, N2, M2; 568 #else 569 uint8_t M1, N1, M2, N2; 570 #endif 571 }; 572 struct { 573 uint16_t NM1, NM2; 574 } __attribute__((packed)); 575 }; 576 int log2P; 577 578 int refclk; 579 }; 580 581 enum nv04_fp_display_regs { 582 FP_DISPLAY_END, 583 FP_TOTAL, 584 FP_CRTC, 585 FP_SYNC_START, 586 FP_SYNC_END, 587 FP_VALID_START, 588 FP_VALID_END 589 }; 590 591 struct nv04_crtc_reg { 592 unsigned char MiscOutReg; 593 uint8_t CRTC[0xa0]; 594 uint8_t CR58[0x10]; 595 uint8_t Sequencer[5]; 596 uint8_t Graphics[9]; 597 uint8_t Attribute[21]; 598 unsigned char DAC[768]; 599 600 /* PCRTC regs */ 601 uint32_t fb_start; 602 uint32_t crtc_cfg; 603 uint32_t cursor_cfg; 604 uint32_t gpio_ext; 605 uint32_t crtc_830; 606 uint32_t crtc_834; 607 uint32_t crtc_850; 608 uint32_t crtc_eng_ctrl; 609 610 /* PRAMDAC regs */ 611 uint32_t nv10_cursync; 612 struct nouveau_pll_vals pllvals; 613 uint32_t ramdac_gen_ctrl; 614 uint32_t ramdac_630; 615 uint32_t ramdac_634; 616 uint32_t tv_setup; 617 uint32_t tv_vtotal; 618 uint32_t tv_vskew; 619 uint32_t tv_vsync_delay; 620 uint32_t tv_htotal; 621 uint32_t tv_hskew; 622 uint32_t tv_hsync_delay; 623 uint32_t tv_hsync_delay2; 624 uint32_t fp_horiz_regs[7]; 625 uint32_t fp_vert_regs[7]; 626 uint32_t dither; 627 uint32_t fp_control; 628 uint32_t dither_regs[6]; 629 uint32_t fp_debug_0; 630 uint32_t fp_debug_1; 631 uint32_t fp_debug_2; 632 uint32_t fp_margin_color; 633 uint32_t ramdac_8c0; 634 uint32_t ramdac_a20; 635 uint32_t ramdac_a24; 636 uint32_t ramdac_a34; 637 uint32_t ctv_regs[38]; 638 }; 639 640 struct nv04_output_reg { 641 uint32_t output; 642 int head; 643 }; 644 645 struct nv04_mode_state { 646 struct nv04_crtc_reg crtc_reg[2]; 647 uint32_t pllsel; 648 uint32_t sel_clk; 649 }; 650 651 enum nouveau_card_type { 652 NV_04 = 0x04, 653 NV_10 = 0x10, 654 NV_20 = 0x20, 655 NV_30 = 0x30, 656 NV_40 = 0x40, 657 NV_50 = 0x50, 658 NV_C0 = 0xc0, 659 NV_D0 = 0xd0, 660 NV_E0 = 0xe0, 661 }; 662 663 struct drm_nouveau_private { 664 struct drm_device *dev; 665 bool noaccel; 666 667 /* the card type, takes NV_* as values */ 668 enum nouveau_card_type card_type; 669 /* exact chipset, derived from NV_PMC_BOOT_0 */ 670 int chipset; 671 int flags; 672 u32 crystal; 673 674 void __iomem *mmio; 675 676 spinlock_t ramin_lock; 677 void __iomem *ramin; 678 u32 ramin_size; 679 u32 ramin_base; 680 bool ramin_available; 681 struct drm_mm ramin_heap; 682 struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; 683 struct list_head gpuobj_list; 684 struct list_head classes; 685 686 struct nouveau_bo *vga_ram; 687 688 /* interrupt handling */ 689 void (*irq_handler[32])(struct drm_device *); 690 bool msi_enabled; 691 692 struct { 693 struct drm_global_reference mem_global_ref; 694 struct ttm_bo_global_ref bo_global_ref; 695 struct ttm_bo_device bdev; 696 atomic_t validate_sequence; 697 int (*move)(struct nouveau_channel *, 698 struct ttm_buffer_object *, 699 struct ttm_mem_reg *, struct ttm_mem_reg *); 700 } ttm; 701 702 struct { 703 spinlock_t lock; 704 struct drm_mm heap; 705 struct nouveau_bo *bo; 706 } fence; 707 708 struct { 709 spinlock_t lock; 710 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 711 } channels; 712 713 struct nouveau_engine engine; 714 struct nouveau_channel *channel; 715 716 /* For PFIFO and PGRAPH. */ 717 spinlock_t context_switch_lock; 718 719 /* VM/PRAMIN flush, legacy PRAMIN aperture */ 720 spinlock_t vm_lock; 721 722 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 723 struct nouveau_ramht *ramht; 724 struct nouveau_gpuobj *ramfc; 725 struct nouveau_gpuobj *ramro; 726 727 uint32_t ramin_rsvd_vram; 728 729 struct { 730 enum { 731 NOUVEAU_GART_NONE = 0, 732 NOUVEAU_GART_AGP, /* AGP */ 733 NOUVEAU_GART_PDMA, /* paged dma object */ 734 NOUVEAU_GART_HW /* on-chip gart/vm */ 735 } type; 736 uint64_t aper_base; 737 uint64_t aper_size; 738 uint64_t aper_free; 739 740 struct ttm_backend_func *func; 741 742 struct { 743 struct page *page; 744 dma_addr_t addr; 745 } dummy; 746 747 struct nouveau_gpuobj *sg_ctxdma; 748 } gart_info; 749 750 /* nv10-nv40 tiling regions */ 751 struct { 752 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 753 spinlock_t lock; 754 } tile; 755 756 /* VRAM/fb configuration */ 757 enum { 758 NV_MEM_TYPE_UNKNOWN = 0, 759 NV_MEM_TYPE_STOLEN, 760 NV_MEM_TYPE_SGRAM, 761 NV_MEM_TYPE_SDRAM, 762 NV_MEM_TYPE_DDR1, 763 NV_MEM_TYPE_DDR2, 764 NV_MEM_TYPE_DDR3, 765 NV_MEM_TYPE_GDDR2, 766 NV_MEM_TYPE_GDDR3, 767 NV_MEM_TYPE_GDDR4, 768 NV_MEM_TYPE_GDDR5 769 } vram_type; 770 uint64_t vram_size; 771 uint64_t vram_sys_base; 772 bool vram_rank_B; 773 774 uint64_t fb_available_size; 775 uint64_t fb_mappable_pages; 776 uint64_t fb_aper_free; 777 int fb_mtrr; 778 779 /* BAR control (NV50-) */ 780 struct nouveau_vm *bar1_vm; 781 struct nouveau_vm *bar3_vm; 782 783 /* G8x/G9x virtual address space */ 784 struct nouveau_vm *chan_vm; 785 786 struct nvbios vbios; 787 u8 *mxms; 788 struct list_head i2c_ports; 789 790 struct nv04_mode_state mode_reg; 791 struct nv04_mode_state saved_reg; 792 uint32_t saved_vga_font[4][16384]; 793 uint32_t crtc_owner; 794 uint32_t dac_users[4]; 795 796 struct backlight_device *backlight; 797 798 struct { 799 struct dentry *channel_root; 800 } debugfs; 801 802 struct nouveau_fbdev *nfbdev; 803 struct apertures_struct *apertures; 804 }; 805 806 static inline struct drm_nouveau_private * 807 nouveau_private(struct drm_device *dev) 808 { 809 return dev->dev_private; 810 } 811 812 static inline struct drm_nouveau_private * 813 nouveau_bdev(struct ttm_bo_device *bd) 814 { 815 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 816 } 817 818 static inline int 819 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 820 { 821 struct nouveau_bo *prev; 822 823 if (!pnvbo) 824 return -EINVAL; 825 prev = *pnvbo; 826 827 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 828 if (prev) { 829 struct ttm_buffer_object *bo = &prev->bo; 830 831 ttm_bo_unref(&bo); 832 } 833 834 return 0; 835 } 836 837 /* nouveau_drv.c */ 838 extern int nouveau_modeset; 839 extern int nouveau_agpmode; 840 extern int nouveau_duallink; 841 extern int nouveau_uscript_lvds; 842 extern int nouveau_uscript_tmds; 843 extern int nouveau_vram_pushbuf; 844 extern int nouveau_vram_notify; 845 extern char *nouveau_vram_type; 846 extern int nouveau_fbpercrtc; 847 extern int nouveau_tv_disable; 848 extern char *nouveau_tv_norm; 849 extern int nouveau_reg_debug; 850 extern char *nouveau_vbios; 851 extern int nouveau_ignorelid; 852 extern int nouveau_nofbaccel; 853 extern int nouveau_noaccel; 854 extern int nouveau_force_post; 855 extern int nouveau_override_conntype; 856 extern char *nouveau_perflvl; 857 extern int nouveau_perflvl_wr; 858 extern int nouveau_msi; 859 extern int nouveau_ctxfw; 860 extern int nouveau_mxmdcb; 861 862 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 863 extern int nouveau_pci_resume(struct pci_dev *pdev); 864 865 /* nouveau_state.c */ 866 extern int nouveau_open(struct drm_device *, struct drm_file *); 867 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 868 extern void nouveau_postclose(struct drm_device *, struct drm_file *); 869 extern int nouveau_load(struct drm_device *, unsigned long flags); 870 extern int nouveau_firstopen(struct drm_device *); 871 extern void nouveau_lastclose(struct drm_device *); 872 extern int nouveau_unload(struct drm_device *); 873 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 874 uint32_t reg, uint32_t mask, uint32_t val); 875 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 876 uint32_t reg, uint32_t mask, uint32_t val); 877 extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, 878 bool (*cond)(void *), void *); 879 extern bool nouveau_wait_for_idle(struct drm_device *); 880 extern int nouveau_card_init(struct drm_device *); 881 882 /* nouveau_mem.c */ 883 extern int nouveau_mem_vram_init(struct drm_device *); 884 extern void nouveau_mem_vram_fini(struct drm_device *); 885 extern int nouveau_mem_gart_init(struct drm_device *); 886 extern void nouveau_mem_gart_fini(struct drm_device *); 887 extern int nouveau_mem_init_agp(struct drm_device *); 888 extern int nouveau_mem_reset_agp(struct drm_device *); 889 extern void nouveau_mem_close(struct drm_device *); 890 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 891 extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq, 892 struct nouveau_pm_memtiming *); 893 extern void nouveau_mem_timing_read(struct drm_device *, 894 struct nouveau_pm_memtiming *); 895 extern int nouveau_mem_vbios_type(struct drm_device *); 896 extern struct nouveau_tile_reg *nv10_mem_set_tiling( 897 struct drm_device *dev, uint32_t addr, uint32_t size, 898 uint32_t pitch, uint32_t flags); 899 extern void nv10_mem_put_tile_region(struct drm_device *dev, 900 struct nouveau_tile_reg *tile, 901 struct nouveau_fence *fence); 902 extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 903 extern const struct ttm_mem_type_manager_func nouveau_gart_manager; 904 905 /* nouveau_notifier.c */ 906 extern int nouveau_notifier_init_channel(struct nouveau_channel *); 907 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 908 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 909 int cout, uint32_t start, uint32_t end, 910 uint32_t *offset); 911 912 /* nouveau_channel.c */ 913 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 914 extern int nouveau_channel_alloc(struct drm_device *dev, 915 struct nouveau_channel **chan, 916 struct drm_file *file_priv, 917 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 918 extern struct nouveau_channel * 919 nouveau_channel_get_unlocked(struct nouveau_channel *); 920 extern struct nouveau_channel * 921 nouveau_channel_get(struct drm_file *, int id); 922 extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 923 extern void nouveau_channel_put(struct nouveau_channel **); 924 extern void nouveau_channel_ref(struct nouveau_channel *chan, 925 struct nouveau_channel **pchan); 926 extern int nouveau_channel_idle(struct nouveau_channel *chan); 927 928 /* nouveau_gpuobj.c */ 929 #define NVOBJ_ENGINE_ADD(d, e, p) do { \ 930 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 931 dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ 932 } while (0) 933 934 #define NVOBJ_ENGINE_DEL(d, e) do { \ 935 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 936 dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ 937 } while (0) 938 939 #define NVOBJ_CLASS(d, c, e) do { \ 940 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 941 if (ret) \ 942 return ret; \ 943 } while (0) 944 945 #define NVOBJ_MTHD(d, c, m, e) do { \ 946 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 947 if (ret) \ 948 return ret; \ 949 } while (0) 950 951 extern int nouveau_gpuobj_early_init(struct drm_device *); 952 extern int nouveau_gpuobj_init(struct drm_device *); 953 extern void nouveau_gpuobj_takedown(struct drm_device *); 954 extern int nouveau_gpuobj_suspend(struct drm_device *dev); 955 extern void nouveau_gpuobj_resume(struct drm_device *dev); 956 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 957 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 958 int (*exec)(struct nouveau_channel *, 959 u32 class, u32 mthd, u32 data)); 960 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 961 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 962 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 963 uint32_t vram_h, uint32_t tt_h); 964 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 965 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 966 uint32_t size, int align, uint32_t flags, 967 struct nouveau_gpuobj **); 968 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 969 struct nouveau_gpuobj **); 970 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 971 u32 size, u32 flags, 972 struct nouveau_gpuobj **); 973 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 974 uint64_t offset, uint64_t size, int access, 975 int target, struct nouveau_gpuobj **); 976 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 977 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 978 u64 size, int target, int access, u32 type, 979 u32 comp, struct nouveau_gpuobj **pobj); 980 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 981 int class, u64 base, u64 size, int target, 982 int access, u32 type, u32 comp); 983 984 /* nouveau_irq.c */ 985 extern int nouveau_irq_init(struct drm_device *); 986 extern void nouveau_irq_fini(struct drm_device *); 987 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 988 extern void nouveau_irq_register(struct drm_device *, int status_bit, 989 void (*)(struct drm_device *)); 990 extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 991 extern void nouveau_irq_preinstall(struct drm_device *); 992 extern int nouveau_irq_postinstall(struct drm_device *); 993 extern void nouveau_irq_uninstall(struct drm_device *); 994 995 /* nouveau_sgdma.c */ 996 extern int nouveau_sgdma_init(struct drm_device *); 997 extern void nouveau_sgdma_takedown(struct drm_device *); 998 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 999 uint32_t offset); 1000 extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, 1001 unsigned long size, 1002 uint32_t page_flags, 1003 struct page *dummy_read_page); 1004 1005 /* nouveau_debugfs.c */ 1006 #if defined(CONFIG_DRM_NOUVEAU_DEBUG) 1007 extern int nouveau_debugfs_init(struct drm_minor *); 1008 extern void nouveau_debugfs_takedown(struct drm_minor *); 1009 extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 1010 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 1011 #else 1012 static inline int 1013 nouveau_debugfs_init(struct drm_minor *minor) 1014 { 1015 return 0; 1016 } 1017 1018 static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 1019 { 1020 } 1021 1022 static inline int 1023 nouveau_debugfs_channel_init(struct nouveau_channel *chan) 1024 { 1025 return 0; 1026 } 1027 1028 static inline void 1029 nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 1030 { 1031 } 1032 #endif 1033 1034 /* nouveau_dma.c */ 1035 extern void nouveau_dma_init(struct nouveau_channel *); 1036 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 1037 1038 /* nouveau_acpi.c */ 1039 #define ROM_BIOS_PAGE 4096 1040 #if defined(CONFIG_ACPI) 1041 void nouveau_register_dsm_handler(void); 1042 void nouveau_unregister_dsm_handler(void); 1043 void nouveau_switcheroo_optimus_dsm(void); 1044 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 1045 bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 1046 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 1047 #else 1048 static inline void nouveau_register_dsm_handler(void) {} 1049 static inline void nouveau_unregister_dsm_handler(void) {} 1050 static inline void nouveau_switcheroo_optimus_dsm(void) {} 1051 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 1052 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 1053 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 1054 #endif 1055 1056 /* nouveau_backlight.c */ 1057 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1058 extern int nouveau_backlight_init(struct drm_device *); 1059 extern void nouveau_backlight_exit(struct drm_device *); 1060 #else 1061 static inline int nouveau_backlight_init(struct drm_device *dev) 1062 { 1063 return 0; 1064 } 1065 1066 static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1067 #endif 1068 1069 /* nouveau_bios.c */ 1070 extern int nouveau_bios_init(struct drm_device *); 1071 extern void nouveau_bios_takedown(struct drm_device *dev); 1072 extern int nouveau_run_vbios_init(struct drm_device *); 1073 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1074 struct dcb_entry *, int crtc); 1075 extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); 1076 extern struct dcb_connector_table_entry * 1077 nouveau_bios_connector_entry(struct drm_device *, int index); 1078 extern u32 get_pll_register(struct drm_device *, enum pll_types); 1079 extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1080 struct pll_lims *); 1081 extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, 1082 struct dcb_entry *, int crtc); 1083 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1084 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1085 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1086 bool *dl, bool *if_is_24bit); 1087 extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1088 int head, int pxclk); 1089 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1090 enum LVDS_script, int pxclk); 1091 bool bios_encoder_match(struct dcb_entry *, u32 hash); 1092 1093 /* nouveau_mxm.c */ 1094 int nouveau_mxm_init(struct drm_device *dev); 1095 void nouveau_mxm_fini(struct drm_device *dev); 1096 1097 /* nouveau_ttm.c */ 1098 int nouveau_ttm_global_init(struct drm_nouveau_private *); 1099 void nouveau_ttm_global_release(struct drm_nouveau_private *); 1100 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1101 1102 /* nouveau_hdmi.c */ 1103 void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); 1104 1105 /* nv04_fb.c */ 1106 extern int nv04_fb_vram_init(struct drm_device *); 1107 extern int nv04_fb_init(struct drm_device *); 1108 extern void nv04_fb_takedown(struct drm_device *); 1109 1110 /* nv10_fb.c */ 1111 extern int nv10_fb_vram_init(struct drm_device *dev); 1112 extern int nv1a_fb_vram_init(struct drm_device *dev); 1113 extern int nv10_fb_init(struct drm_device *); 1114 extern void nv10_fb_takedown(struct drm_device *); 1115 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1116 uint32_t addr, uint32_t size, 1117 uint32_t pitch, uint32_t flags); 1118 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1119 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1120 1121 /* nv20_fb.c */ 1122 extern int nv20_fb_vram_init(struct drm_device *dev); 1123 extern int nv20_fb_init(struct drm_device *); 1124 extern void nv20_fb_takedown(struct drm_device *); 1125 extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, 1126 uint32_t addr, uint32_t size, 1127 uint32_t pitch, uint32_t flags); 1128 extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); 1129 extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); 1130 1131 /* nv30_fb.c */ 1132 extern int nv30_fb_init(struct drm_device *); 1133 extern void nv30_fb_takedown(struct drm_device *); 1134 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1135 uint32_t addr, uint32_t size, 1136 uint32_t pitch, uint32_t flags); 1137 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1138 1139 /* nv40_fb.c */ 1140 extern int nv40_fb_vram_init(struct drm_device *dev); 1141 extern int nv40_fb_init(struct drm_device *); 1142 extern void nv40_fb_takedown(struct drm_device *); 1143 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1144 1145 /* nv50_fb.c */ 1146 extern int nv50_fb_init(struct drm_device *); 1147 extern void nv50_fb_takedown(struct drm_device *); 1148 extern void nv50_fb_vm_trap(struct drm_device *, int display); 1149 1150 /* nvc0_fb.c */ 1151 extern int nvc0_fb_init(struct drm_device *); 1152 extern void nvc0_fb_takedown(struct drm_device *); 1153 1154 /* nv04_graph.c */ 1155 extern int nv04_graph_create(struct drm_device *); 1156 extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); 1157 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1158 u32 class, u32 mthd, u32 data); 1159 extern struct nouveau_bitfield nv04_graph_nsource[]; 1160 1161 /* nv10_graph.c */ 1162 extern int nv10_graph_create(struct drm_device *); 1163 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1164 extern struct nouveau_bitfield nv10_graph_intr[]; 1165 extern struct nouveau_bitfield nv10_graph_nstatus[]; 1166 1167 /* nv20_graph.c */ 1168 extern int nv20_graph_create(struct drm_device *); 1169 1170 /* nv40_graph.c */ 1171 extern int nv40_graph_create(struct drm_device *); 1172 extern void nv40_grctx_init(struct drm_device *, u32 *size); 1173 extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *); 1174 1175 /* nv50_graph.c */ 1176 extern int nv50_graph_create(struct drm_device *); 1177 extern struct nouveau_enum nv50_data_error_names[]; 1178 extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); 1179 extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *); 1180 extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *); 1181 1182 /* nvc0_graph.c */ 1183 extern int nvc0_graph_create(struct drm_device *); 1184 extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); 1185 1186 /* nve0_graph.c */ 1187 extern int nve0_graph_create(struct drm_device *); 1188 1189 /* nv84_crypt.c */ 1190 extern int nv84_crypt_create(struct drm_device *); 1191 1192 /* nv98_crypt.c */ 1193 extern int nv98_crypt_create(struct drm_device *dev); 1194 1195 /* nva3_copy.c */ 1196 extern int nva3_copy_create(struct drm_device *dev); 1197 1198 /* nvc0_copy.c */ 1199 extern int nvc0_copy_create(struct drm_device *dev, int engine); 1200 1201 /* nv31_mpeg.c */ 1202 extern int nv31_mpeg_create(struct drm_device *dev); 1203 1204 /* nv50_mpeg.c */ 1205 extern int nv50_mpeg_create(struct drm_device *dev); 1206 1207 /* nv84_bsp.c */ 1208 /* nv98_bsp.c */ 1209 extern int nv84_bsp_create(struct drm_device *dev); 1210 1211 /* nv84_vp.c */ 1212 /* nv98_vp.c */ 1213 extern int nv84_vp_create(struct drm_device *dev); 1214 1215 /* nv98_ppp.c */ 1216 extern int nv98_ppp_create(struct drm_device *dev); 1217 1218 /* nv04_instmem.c */ 1219 extern int nv04_instmem_init(struct drm_device *); 1220 extern void nv04_instmem_takedown(struct drm_device *); 1221 extern int nv04_instmem_suspend(struct drm_device *); 1222 extern void nv04_instmem_resume(struct drm_device *); 1223 extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1224 u32 size, u32 align); 1225 extern void nv04_instmem_put(struct nouveau_gpuobj *); 1226 extern int nv04_instmem_map(struct nouveau_gpuobj *); 1227 extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1228 extern void nv04_instmem_flush(struct drm_device *); 1229 1230 /* nv50_instmem.c */ 1231 extern int nv50_instmem_init(struct drm_device *); 1232 extern void nv50_instmem_takedown(struct drm_device *); 1233 extern int nv50_instmem_suspend(struct drm_device *); 1234 extern void nv50_instmem_resume(struct drm_device *); 1235 extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, 1236 u32 size, u32 align); 1237 extern void nv50_instmem_put(struct nouveau_gpuobj *); 1238 extern int nv50_instmem_map(struct nouveau_gpuobj *); 1239 extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1240 extern void nv50_instmem_flush(struct drm_device *); 1241 extern void nv84_instmem_flush(struct drm_device *); 1242 1243 /* nvc0_instmem.c */ 1244 extern int nvc0_instmem_init(struct drm_device *); 1245 extern void nvc0_instmem_takedown(struct drm_device *); 1246 extern int nvc0_instmem_suspend(struct drm_device *); 1247 extern void nvc0_instmem_resume(struct drm_device *); 1248 1249 /* nv04_mc.c */ 1250 extern int nv04_mc_init(struct drm_device *); 1251 extern void nv04_mc_takedown(struct drm_device *); 1252 1253 /* nv40_mc.c */ 1254 extern int nv40_mc_init(struct drm_device *); 1255 extern void nv40_mc_takedown(struct drm_device *); 1256 1257 /* nv50_mc.c */ 1258 extern int nv50_mc_init(struct drm_device *); 1259 extern void nv50_mc_takedown(struct drm_device *); 1260 1261 /* nv04_timer.c */ 1262 extern int nv04_timer_init(struct drm_device *); 1263 extern uint64_t nv04_timer_read(struct drm_device *); 1264 extern void nv04_timer_takedown(struct drm_device *); 1265 1266 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1267 unsigned long arg); 1268 1269 /* nv04_dac.c */ 1270 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1271 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1272 extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1273 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1274 extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1275 1276 /* nv04_dfp.c */ 1277 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1278 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1279 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1280 int head, bool dl); 1281 extern void nv04_dfp_disable(struct drm_device *dev, int head); 1282 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1283 1284 /* nv04_tv.c */ 1285 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1286 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1287 1288 /* nv17_tv.c */ 1289 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1290 1291 /* nv04_display.c */ 1292 extern int nv04_display_early_init(struct drm_device *); 1293 extern void nv04_display_late_takedown(struct drm_device *); 1294 extern int nv04_display_create(struct drm_device *); 1295 extern void nv04_display_destroy(struct drm_device *); 1296 extern int nv04_display_init(struct drm_device *); 1297 extern void nv04_display_fini(struct drm_device *); 1298 1299 /* nvd0_display.c */ 1300 extern int nvd0_display_create(struct drm_device *); 1301 extern void nvd0_display_destroy(struct drm_device *); 1302 extern int nvd0_display_init(struct drm_device *); 1303 extern void nvd0_display_fini(struct drm_device *); 1304 struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); 1305 void nvd0_display_flip_stop(struct drm_crtc *); 1306 int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, 1307 struct nouveau_channel *, u32 swap_interval); 1308 1309 /* nv04_crtc.c */ 1310 extern int nv04_crtc_create(struct drm_device *, int index); 1311 1312 /* nouveau_bo.c */ 1313 extern struct ttm_bo_driver nouveau_bo_driver; 1314 extern void nouveau_bo_move_init(struct nouveau_channel *); 1315 extern int nouveau_bo_new(struct drm_device *, int size, int align, 1316 uint32_t flags, uint32_t tile_mode, 1317 uint32_t tile_flags, 1318 struct sg_table *sg, 1319 struct nouveau_bo **); 1320 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1321 extern int nouveau_bo_unpin(struct nouveau_bo *); 1322 extern int nouveau_bo_map(struct nouveau_bo *); 1323 extern void nouveau_bo_unmap(struct nouveau_bo *); 1324 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1325 uint32_t busy); 1326 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1327 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1328 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1329 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1330 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1331 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1332 bool no_wait_reserve, bool no_wait_gpu); 1333 1334 extern struct nouveau_vma * 1335 nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); 1336 extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, 1337 struct nouveau_vma *); 1338 extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); 1339 1340 /* nouveau_gem.c */ 1341 extern int nouveau_gem_new(struct drm_device *, int size, int align, 1342 uint32_t domain, uint32_t tile_mode, 1343 uint32_t tile_flags, struct nouveau_bo **); 1344 extern int nouveau_gem_object_new(struct drm_gem_object *); 1345 extern void nouveau_gem_object_del(struct drm_gem_object *); 1346 extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); 1347 extern void nouveau_gem_object_close(struct drm_gem_object *, 1348 struct drm_file *); 1349 extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1350 struct drm_file *); 1351 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1352 struct drm_file *); 1353 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1354 struct drm_file *); 1355 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1356 struct drm_file *); 1357 extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1358 struct drm_file *); 1359 1360 extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev, 1361 struct drm_gem_object *obj, int flags); 1362 extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev, 1363 struct dma_buf *dma_buf); 1364 1365 /* nouveau_display.c */ 1366 int nouveau_display_create(struct drm_device *dev); 1367 void nouveau_display_destroy(struct drm_device *dev); 1368 int nouveau_display_init(struct drm_device *dev); 1369 void nouveau_display_fini(struct drm_device *dev); 1370 int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1371 void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1372 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1373 struct drm_pending_vblank_event *event); 1374 int nouveau_finish_page_flip(struct nouveau_channel *, 1375 struct nouveau_page_flip_state *); 1376 int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, 1377 struct drm_mode_create_dumb *args); 1378 int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, 1379 uint32_t handle, uint64_t *offset); 1380 int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, 1381 uint32_t handle); 1382 1383 /* nv10_gpio.c */ 1384 int nv10_gpio_init(struct drm_device *dev); 1385 void nv10_gpio_fini(struct drm_device *dev); 1386 int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1387 int nv10_gpio_sense(struct drm_device *dev, int line); 1388 void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); 1389 1390 /* nv50_gpio.c */ 1391 int nv50_gpio_init(struct drm_device *dev); 1392 void nv50_gpio_fini(struct drm_device *dev); 1393 int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1394 int nv50_gpio_sense(struct drm_device *dev, int line); 1395 void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); 1396 int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); 1397 int nvd0_gpio_sense(struct drm_device *dev, int line); 1398 1399 /* nv50_calc.c */ 1400 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1401 int *N1, int *M1, int *N2, int *M2, int *P); 1402 int nva3_calc_pll(struct drm_device *, struct pll_lims *, 1403 int clk, int *N, int *fN, int *M, int *P); 1404 1405 #ifndef ioread32_native 1406 #ifdef __BIG_ENDIAN 1407 #define ioread16_native ioread16be 1408 #define iowrite16_native iowrite16be 1409 #define ioread32_native ioread32be 1410 #define iowrite32_native iowrite32be 1411 #else /* def __BIG_ENDIAN */ 1412 #define ioread16_native ioread16 1413 #define iowrite16_native iowrite16 1414 #define ioread32_native ioread32 1415 #define iowrite32_native iowrite32 1416 #endif /* def __BIG_ENDIAN else */ 1417 #endif /* !ioread32_native */ 1418 1419 /* channel control reg access */ 1420 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1421 { 1422 return ioread32_native(chan->user + reg); 1423 } 1424 1425 static inline void nvchan_wr32(struct nouveau_channel *chan, 1426 unsigned reg, u32 val) 1427 { 1428 iowrite32_native(val, chan->user + reg); 1429 } 1430 1431 /* register access */ 1432 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1433 { 1434 struct drm_nouveau_private *dev_priv = dev->dev_private; 1435 return ioread32_native(dev_priv->mmio + reg); 1436 } 1437 1438 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1439 { 1440 struct drm_nouveau_private *dev_priv = dev->dev_private; 1441 iowrite32_native(val, dev_priv->mmio + reg); 1442 } 1443 1444 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1445 { 1446 u32 tmp = nv_rd32(dev, reg); 1447 nv_wr32(dev, reg, (tmp & ~mask) | val); 1448 return tmp; 1449 } 1450 1451 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1452 { 1453 struct drm_nouveau_private *dev_priv = dev->dev_private; 1454 return ioread8(dev_priv->mmio + reg); 1455 } 1456 1457 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1458 { 1459 struct drm_nouveau_private *dev_priv = dev->dev_private; 1460 iowrite8(val, dev_priv->mmio + reg); 1461 } 1462 1463 #define nv_wait(dev, reg, mask, val) \ 1464 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1465 #define nv_wait_ne(dev, reg, mask, val) \ 1466 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1467 #define nv_wait_cb(dev, func, data) \ 1468 nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) 1469 1470 /* PRAMIN access */ 1471 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1472 { 1473 struct drm_nouveau_private *dev_priv = dev->dev_private; 1474 return ioread32_native(dev_priv->ramin + offset); 1475 } 1476 1477 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1478 { 1479 struct drm_nouveau_private *dev_priv = dev->dev_private; 1480 iowrite32_native(val, dev_priv->ramin + offset); 1481 } 1482 1483 /* object access */ 1484 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1485 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1486 1487 /* 1488 * Logging 1489 * Argument d is (struct drm_device *). 1490 */ 1491 #define NV_PRINTK(level, d, fmt, arg...) \ 1492 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1493 pci_name(d->pdev), ##arg) 1494 #ifndef NV_DEBUG_NOTRACE 1495 #define NV_DEBUG(d, fmt, arg...) do { \ 1496 if (drm_debug & DRM_UT_DRIVER) { \ 1497 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1498 __LINE__, ##arg); \ 1499 } \ 1500 } while (0) 1501 #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1502 if (drm_debug & DRM_UT_KMS) { \ 1503 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1504 __LINE__, ##arg); \ 1505 } \ 1506 } while (0) 1507 #else 1508 #define NV_DEBUG(d, fmt, arg...) do { \ 1509 if (drm_debug & DRM_UT_DRIVER) \ 1510 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1511 } while (0) 1512 #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1513 if (drm_debug & DRM_UT_KMS) \ 1514 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1515 } while (0) 1516 #endif 1517 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1518 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1519 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1520 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1521 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1522 #define NV_WARNONCE(d, fmt, arg...) do { \ 1523 static int _warned = 0; \ 1524 if (!_warned) { \ 1525 NV_WARN(d, fmt, ##arg); \ 1526 _warned = 1; \ 1527 } \ 1528 } while(0) 1529 1530 /* nouveau_reg_debug bitmask */ 1531 enum { 1532 NOUVEAU_REG_DEBUG_MC = 0x1, 1533 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1534 NOUVEAU_REG_DEBUG_FB = 0x4, 1535 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1536 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1537 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1538 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1539 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1540 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1541 NOUVEAU_REG_DEBUG_EVO = 0x200, 1542 NOUVEAU_REG_DEBUG_AUXCH = 0x400 1543 }; 1544 1545 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1546 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1547 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1548 } while (0) 1549 1550 static inline bool 1551 nv_two_heads(struct drm_device *dev) 1552 { 1553 struct drm_nouveau_private *dev_priv = dev->dev_private; 1554 const int impl = dev->pci_device & 0x0ff0; 1555 1556 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1557 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1558 return true; 1559 1560 return false; 1561 } 1562 1563 static inline bool 1564 nv_gf4_disp_arch(struct drm_device *dev) 1565 { 1566 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1567 } 1568 1569 static inline bool 1570 nv_two_reg_pll(struct drm_device *dev) 1571 { 1572 struct drm_nouveau_private *dev_priv = dev->dev_private; 1573 const int impl = dev->pci_device & 0x0ff0; 1574 1575 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1576 return true; 1577 return false; 1578 } 1579 1580 static inline bool 1581 nv_match_device(struct drm_device *dev, unsigned device, 1582 unsigned sub_vendor, unsigned sub_device) 1583 { 1584 return dev->pdev->device == device && 1585 dev->pdev->subsystem_vendor == sub_vendor && 1586 dev->pdev->subsystem_device == sub_device; 1587 } 1588 1589 static inline void * 1590 nv_engine(struct drm_device *dev, int engine) 1591 { 1592 struct drm_nouveau_private *dev_priv = dev->dev_private; 1593 return (void *)dev_priv->eng[engine]; 1594 } 1595 1596 /* returns 1 if device is one of the nv4x using the 0x4497 object class, 1597 * helpful to determine a number of other hardware features 1598 */ 1599 static inline int 1600 nv44_graph_class(struct drm_device *dev) 1601 { 1602 struct drm_nouveau_private *dev_priv = dev->dev_private; 1603 1604 if ((dev_priv->chipset & 0xf0) == 0x60) 1605 return 1; 1606 1607 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1608 } 1609 1610 /* memory type/access flags, do not match hardware values */ 1611 #define NV_MEM_ACCESS_RO 1 1612 #define NV_MEM_ACCESS_WO 2 1613 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1614 #define NV_MEM_ACCESS_SYS 4 1615 #define NV_MEM_ACCESS_VM 8 1616 #define NV_MEM_ACCESS_NOSNOOP 16 1617 1618 #define NV_MEM_TARGET_VRAM 0 1619 #define NV_MEM_TARGET_PCI 1 1620 #define NV_MEM_TARGET_PCI_NOSNOOP 2 1621 #define NV_MEM_TARGET_VM 3 1622 #define NV_MEM_TARGET_GART 4 1623 1624 #define NV_MEM_TYPE_VM 0x7f 1625 #define NV_MEM_COMP_VM 0x03 1626 1627 /* FIFO methods */ 1628 #define NV01_SUBCHAN_OBJECT 0x00000000 1629 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 1630 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 1631 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 1632 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c 1633 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 1634 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 1635 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 1636 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 1637 #define NV84_SUBCHAN_NOTIFY_INTR 0x00000020 1638 #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 1639 #define NV10_SUBCHAN_REF_CNT 0x00000050 1640 #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054 1641 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 1642 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 1643 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 1644 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c 1645 #define NV40_SUBCHAN_YIELD 0x00000080 1646 1647 /* NV_SW object class */ 1648 #define NV_SW 0x0000506e 1649 #define NV_SW_DMA_VBLSEM 0x0000018c 1650 #define NV_SW_VBLSEM_OFFSET 0x00000400 1651 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1652 #define NV_SW_VBLSEM_RELEASE 0x00000408 1653 #define NV_SW_PAGE_FLIP 0x00000500 1654 1655 #endif /* __NOUVEAU_DRV_H__ */ 1656