1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRV_H__ 26 #define __NOUVEAU_DRV_H__ 27 28 #define DRIVER_AUTHOR "Stephane Marchesin" 29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" 30 31 #define DRIVER_NAME "nouveau" 32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce" 33 #define DRIVER_DATE "20090420" 34 35 #define DRIVER_MAJOR 0 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 16 38 39 #define NOUVEAU_FAMILY 0x0000FFFF 40 #define NOUVEAU_FLAGS 0xFFFF0000 41 42 #include "ttm/ttm_bo_api.h" 43 #include "ttm/ttm_bo_driver.h" 44 #include "ttm/ttm_placement.h" 45 #include "ttm/ttm_memory.h" 46 #include "ttm/ttm_module.h" 47 48 struct nouveau_fpriv { 49 struct ttm_object_file *tfile; 50 }; 51 52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 53 54 #include "nouveau_drm.h" 55 #include "nouveau_reg.h" 56 #include "nouveau_bios.h" 57 #include "nouveau_util.h" 58 59 struct nouveau_grctx; 60 struct nouveau_vram; 61 #include "nouveau_vm.h" 62 63 #define MAX_NUM_DCB_ENTRIES 16 64 65 #define NOUVEAU_MAX_CHANNEL_NR 128 66 #define NOUVEAU_MAX_TILE_NR 15 67 68 struct nouveau_vram { 69 struct drm_device *dev; 70 71 struct nouveau_vma bar_vma; 72 u8 page_shift; 73 74 struct list_head regions; 75 u32 memtype; 76 u64 offset; 77 u64 size; 78 }; 79 80 struct nouveau_tile_reg { 81 bool used; 82 uint32_t addr; 83 uint32_t limit; 84 uint32_t pitch; 85 uint32_t zcomp; 86 struct drm_mm_node *tag_mem; 87 struct nouveau_fence *fence; 88 }; 89 90 struct nouveau_bo { 91 struct ttm_buffer_object bo; 92 struct ttm_placement placement; 93 u32 placements[3]; 94 u32 busy_placements[3]; 95 struct ttm_bo_kmap_obj kmap; 96 struct list_head head; 97 98 /* protected by ttm_bo_reserve() */ 99 struct drm_file *reserved_by; 100 struct list_head entry; 101 int pbbo_index; 102 bool validate_mapped; 103 104 struct nouveau_channel *channel; 105 106 struct nouveau_vma vma; 107 bool mappable; 108 bool no_vm; 109 110 uint32_t tile_mode; 111 uint32_t tile_flags; 112 struct nouveau_tile_reg *tile; 113 114 struct drm_gem_object *gem; 115 int pin_refcnt; 116 }; 117 118 #define nouveau_bo_tile_layout(nvbo) \ 119 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) 120 121 static inline struct nouveau_bo * 122 nouveau_bo(struct ttm_buffer_object *bo) 123 { 124 return container_of(bo, struct nouveau_bo, bo); 125 } 126 127 static inline struct nouveau_bo * 128 nouveau_gem_object(struct drm_gem_object *gem) 129 { 130 return gem ? gem->driver_private : NULL; 131 } 132 133 /* TODO: submit equivalent to TTM generic API upstream? */ 134 static inline void __iomem * 135 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) 136 { 137 bool is_iomem; 138 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( 139 &nvbo->kmap, &is_iomem); 140 WARN_ON_ONCE(ioptr && !is_iomem); 141 return ioptr; 142 } 143 144 enum nouveau_flags { 145 NV_NFORCE = 0x10000000, 146 NV_NFORCE2 = 0x20000000 147 }; 148 149 #define NVOBJ_ENGINE_SW 0 150 #define NVOBJ_ENGINE_GR 1 151 #define NVOBJ_ENGINE_PPP 2 152 #define NVOBJ_ENGINE_COPY 3 153 #define NVOBJ_ENGINE_VP 4 154 #define NVOBJ_ENGINE_CRYPT 5 155 #define NVOBJ_ENGINE_BSP 6 156 #define NVOBJ_ENGINE_DISPLAY 0xcafe0001 157 #define NVOBJ_ENGINE_INT 0xdeadbeef 158 159 #define NVOBJ_FLAG_DONT_MAP (1 << 0) 160 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) 161 #define NVOBJ_FLAG_ZERO_FREE (1 << 2) 162 #define NVOBJ_FLAG_VM (1 << 3) 163 #define NVOBJ_FLAG_VM_USER (1 << 4) 164 165 #define NVOBJ_CINST_GLOBAL 0xdeadbeef 166 167 struct nouveau_gpuobj { 168 struct drm_device *dev; 169 struct kref refcount; 170 struct list_head list; 171 172 void *node; 173 u32 *suspend; 174 175 uint32_t flags; 176 177 u32 size; 178 u32 pinst; 179 u32 cinst; 180 u64 vinst; 181 182 uint32_t engine; 183 uint32_t class; 184 185 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); 186 void *priv; 187 }; 188 189 struct nouveau_page_flip_state { 190 struct list_head head; 191 struct drm_pending_vblank_event *event; 192 int crtc, bpp, pitch, x, y; 193 uint64_t offset; 194 }; 195 196 enum nouveau_channel_mutex_class { 197 NOUVEAU_UCHANNEL_MUTEX, 198 NOUVEAU_KCHANNEL_MUTEX 199 }; 200 201 struct nouveau_channel { 202 struct drm_device *dev; 203 int id; 204 205 /* references to the channel data structure */ 206 struct kref ref; 207 /* users of the hardware channel resources, the hardware 208 * context will be kicked off when it reaches zero. */ 209 atomic_t users; 210 struct mutex mutex; 211 212 /* owner of this fifo */ 213 struct drm_file *file_priv; 214 /* mapping of the fifo itself */ 215 struct drm_local_map *map; 216 217 /* mapping of the regs controling the fifo */ 218 void __iomem *user; 219 uint32_t user_get; 220 uint32_t user_put; 221 222 /* Fencing */ 223 struct { 224 /* lock protects the pending list only */ 225 spinlock_t lock; 226 struct list_head pending; 227 uint32_t sequence; 228 uint32_t sequence_ack; 229 atomic_t last_sequence_irq; 230 } fence; 231 232 /* DMA push buffer */ 233 struct nouveau_gpuobj *pushbuf; 234 struct nouveau_bo *pushbuf_bo; 235 uint32_t pushbuf_base; 236 237 /* Notifier memory */ 238 struct nouveau_bo *notifier_bo; 239 struct drm_mm notifier_heap; 240 241 /* PFIFO context */ 242 struct nouveau_gpuobj *ramfc; 243 struct nouveau_gpuobj *cache; 244 void *fifo_priv; 245 246 /* PGRAPH context */ 247 /* XXX may be merge 2 pointers as private data ??? */ 248 struct nouveau_gpuobj *ramin_grctx; 249 struct nouveau_gpuobj *crypt_ctx; 250 void *pgraph_ctx; 251 252 /* NV50 VM */ 253 struct nouveau_vm *vm; 254 struct nouveau_gpuobj *vm_pd; 255 256 /* Objects */ 257 struct nouveau_gpuobj *ramin; /* Private instmem */ 258 struct drm_mm ramin_heap; /* Private PRAMIN heap */ 259 struct nouveau_ramht *ramht; /* Hash table */ 260 261 /* GPU object info for stuff used in-kernel (mm_enabled) */ 262 uint32_t m2mf_ntfy; 263 uint32_t vram_handle; 264 uint32_t gart_handle; 265 bool accel_done; 266 267 /* Push buffer state (only for drm's channel on !mm_enabled) */ 268 struct { 269 int max; 270 int free; 271 int cur; 272 int put; 273 /* access via pushbuf_bo */ 274 275 int ib_base; 276 int ib_max; 277 int ib_free; 278 int ib_put; 279 } dma; 280 281 uint32_t sw_subchannel[8]; 282 283 struct { 284 struct nouveau_gpuobj *vblsem; 285 uint32_t vblsem_head; 286 uint32_t vblsem_offset; 287 uint32_t vblsem_rval; 288 struct list_head vbl_wait; 289 struct list_head flip; 290 } nvsw; 291 292 struct { 293 bool active; 294 char name[32]; 295 struct drm_info_list info; 296 } debugfs; 297 }; 298 299 struct nouveau_instmem_engine { 300 void *priv; 301 302 int (*init)(struct drm_device *dev); 303 void (*takedown)(struct drm_device *dev); 304 int (*suspend)(struct drm_device *dev); 305 void (*resume)(struct drm_device *dev); 306 307 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); 308 void (*put)(struct nouveau_gpuobj *); 309 int (*map)(struct nouveau_gpuobj *); 310 void (*unmap)(struct nouveau_gpuobj *); 311 312 void (*flush)(struct drm_device *); 313 }; 314 315 struct nouveau_mc_engine { 316 int (*init)(struct drm_device *dev); 317 void (*takedown)(struct drm_device *dev); 318 }; 319 320 struct nouveau_timer_engine { 321 int (*init)(struct drm_device *dev); 322 void (*takedown)(struct drm_device *dev); 323 uint64_t (*read)(struct drm_device *dev); 324 }; 325 326 struct nouveau_fb_engine { 327 int num_tiles; 328 struct drm_mm tag_heap; 329 void *priv; 330 331 int (*init)(struct drm_device *dev); 332 void (*takedown)(struct drm_device *dev); 333 334 void (*init_tile_region)(struct drm_device *dev, int i, 335 uint32_t addr, uint32_t size, 336 uint32_t pitch, uint32_t flags); 337 void (*set_tile_region)(struct drm_device *dev, int i); 338 void (*free_tile_region)(struct drm_device *dev, int i); 339 }; 340 341 struct nouveau_fifo_engine { 342 void *priv; 343 int channels; 344 345 struct nouveau_gpuobj *playlist[2]; 346 int cur_playlist; 347 348 int (*init)(struct drm_device *); 349 void (*takedown)(struct drm_device *); 350 351 void (*disable)(struct drm_device *); 352 void (*enable)(struct drm_device *); 353 bool (*reassign)(struct drm_device *, bool enable); 354 bool (*cache_pull)(struct drm_device *dev, bool enable); 355 356 int (*channel_id)(struct drm_device *); 357 358 int (*create_context)(struct nouveau_channel *); 359 void (*destroy_context)(struct nouveau_channel *); 360 int (*load_context)(struct nouveau_channel *); 361 int (*unload_context)(struct drm_device *); 362 void (*tlb_flush)(struct drm_device *dev); 363 }; 364 365 struct nouveau_pgraph_engine { 366 bool accel_blocked; 367 bool registered; 368 int grctx_size; 369 void *priv; 370 371 /* NV2x/NV3x context table (0x400780) */ 372 struct nouveau_gpuobj *ctx_table; 373 374 int (*init)(struct drm_device *); 375 void (*takedown)(struct drm_device *); 376 377 void (*fifo_access)(struct drm_device *, bool); 378 379 struct nouveau_channel *(*channel)(struct drm_device *); 380 int (*create_context)(struct nouveau_channel *); 381 void (*destroy_context)(struct nouveau_channel *); 382 int (*load_context)(struct nouveau_channel *); 383 int (*unload_context)(struct drm_device *); 384 void (*tlb_flush)(struct drm_device *dev); 385 386 void (*set_tile_region)(struct drm_device *dev, int i); 387 }; 388 389 struct nouveau_display_engine { 390 int (*early_init)(struct drm_device *); 391 void (*late_takedown)(struct drm_device *); 392 int (*create)(struct drm_device *); 393 int (*init)(struct drm_device *); 394 void (*destroy)(struct drm_device *); 395 }; 396 397 struct nouveau_gpio_engine { 398 void *priv; 399 400 int (*init)(struct drm_device *); 401 void (*takedown)(struct drm_device *); 402 403 int (*get)(struct drm_device *, enum dcb_gpio_tag); 404 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); 405 406 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, 407 void (*)(void *, int), void *); 408 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, 409 void (*)(void *, int), void *); 410 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); 411 }; 412 413 struct nouveau_pm_voltage_level { 414 u8 voltage; 415 u8 vid; 416 }; 417 418 struct nouveau_pm_voltage { 419 bool supported; 420 u8 vid_mask; 421 422 struct nouveau_pm_voltage_level *level; 423 int nr_level; 424 }; 425 426 #define NOUVEAU_PM_MAX_LEVEL 8 427 struct nouveau_pm_level { 428 struct device_attribute dev_attr; 429 char name[32]; 430 int id; 431 432 u32 core; 433 u32 memory; 434 u32 shader; 435 u32 unk05; 436 437 u8 voltage; 438 u8 fanspeed; 439 440 u16 memscript; 441 }; 442 443 struct nouveau_pm_temp_sensor_constants { 444 u16 offset_constant; 445 s16 offset_mult; 446 u16 offset_div; 447 u16 slope_mult; 448 u16 slope_div; 449 }; 450 451 struct nouveau_pm_threshold_temp { 452 s16 critical; 453 s16 down_clock; 454 s16 fan_boost; 455 }; 456 457 struct nouveau_pm_memtiming { 458 u32 reg_100220; 459 u32 reg_100224; 460 u32 reg_100228; 461 u32 reg_10022c; 462 u32 reg_100230; 463 u32 reg_100234; 464 u32 reg_100238; 465 u32 reg_10023c; 466 }; 467 468 struct nouveau_pm_memtimings { 469 bool supported; 470 struct nouveau_pm_memtiming *timing; 471 int nr_timing; 472 }; 473 474 struct nouveau_pm_engine { 475 struct nouveau_pm_voltage voltage; 476 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; 477 int nr_perflvl; 478 struct nouveau_pm_memtimings memtimings; 479 struct nouveau_pm_temp_sensor_constants sensor_constants; 480 struct nouveau_pm_threshold_temp threshold_temp; 481 482 struct nouveau_pm_level boot; 483 struct nouveau_pm_level *cur; 484 485 struct device *hwmon; 486 struct notifier_block acpi_nb; 487 488 int (*clock_get)(struct drm_device *, u32 id); 489 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, 490 u32 id, int khz); 491 void (*clock_set)(struct drm_device *, void *); 492 int (*voltage_get)(struct drm_device *); 493 int (*voltage_set)(struct drm_device *, int voltage); 494 int (*fanspeed_get)(struct drm_device *); 495 int (*fanspeed_set)(struct drm_device *, int fanspeed); 496 int (*temp_get)(struct drm_device *); 497 }; 498 499 struct nouveau_crypt_engine { 500 bool registered; 501 502 int (*init)(struct drm_device *); 503 void (*takedown)(struct drm_device *); 504 int (*create_context)(struct nouveau_channel *); 505 void (*destroy_context)(struct nouveau_channel *); 506 void (*tlb_flush)(struct drm_device *dev); 507 }; 508 509 struct nouveau_vram_engine { 510 int (*init)(struct drm_device *); 511 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, 512 u32 type, struct nouveau_vram **); 513 void (*put)(struct drm_device *, struct nouveau_vram **); 514 515 bool (*flags_valid)(struct drm_device *, u32 tile_flags); 516 }; 517 518 struct nouveau_engine { 519 struct nouveau_instmem_engine instmem; 520 struct nouveau_mc_engine mc; 521 struct nouveau_timer_engine timer; 522 struct nouveau_fb_engine fb; 523 struct nouveau_pgraph_engine graph; 524 struct nouveau_fifo_engine fifo; 525 struct nouveau_display_engine display; 526 struct nouveau_gpio_engine gpio; 527 struct nouveau_pm_engine pm; 528 struct nouveau_crypt_engine crypt; 529 struct nouveau_vram_engine vram; 530 }; 531 532 struct nouveau_pll_vals { 533 union { 534 struct { 535 #ifdef __BIG_ENDIAN 536 uint8_t N1, M1, N2, M2; 537 #else 538 uint8_t M1, N1, M2, N2; 539 #endif 540 }; 541 struct { 542 uint16_t NM1, NM2; 543 } __attribute__((packed)); 544 }; 545 int log2P; 546 547 int refclk; 548 }; 549 550 enum nv04_fp_display_regs { 551 FP_DISPLAY_END, 552 FP_TOTAL, 553 FP_CRTC, 554 FP_SYNC_START, 555 FP_SYNC_END, 556 FP_VALID_START, 557 FP_VALID_END 558 }; 559 560 struct nv04_crtc_reg { 561 unsigned char MiscOutReg; 562 uint8_t CRTC[0xa0]; 563 uint8_t CR58[0x10]; 564 uint8_t Sequencer[5]; 565 uint8_t Graphics[9]; 566 uint8_t Attribute[21]; 567 unsigned char DAC[768]; 568 569 /* PCRTC regs */ 570 uint32_t fb_start; 571 uint32_t crtc_cfg; 572 uint32_t cursor_cfg; 573 uint32_t gpio_ext; 574 uint32_t crtc_830; 575 uint32_t crtc_834; 576 uint32_t crtc_850; 577 uint32_t crtc_eng_ctrl; 578 579 /* PRAMDAC regs */ 580 uint32_t nv10_cursync; 581 struct nouveau_pll_vals pllvals; 582 uint32_t ramdac_gen_ctrl; 583 uint32_t ramdac_630; 584 uint32_t ramdac_634; 585 uint32_t tv_setup; 586 uint32_t tv_vtotal; 587 uint32_t tv_vskew; 588 uint32_t tv_vsync_delay; 589 uint32_t tv_htotal; 590 uint32_t tv_hskew; 591 uint32_t tv_hsync_delay; 592 uint32_t tv_hsync_delay2; 593 uint32_t fp_horiz_regs[7]; 594 uint32_t fp_vert_regs[7]; 595 uint32_t dither; 596 uint32_t fp_control; 597 uint32_t dither_regs[6]; 598 uint32_t fp_debug_0; 599 uint32_t fp_debug_1; 600 uint32_t fp_debug_2; 601 uint32_t fp_margin_color; 602 uint32_t ramdac_8c0; 603 uint32_t ramdac_a20; 604 uint32_t ramdac_a24; 605 uint32_t ramdac_a34; 606 uint32_t ctv_regs[38]; 607 }; 608 609 struct nv04_output_reg { 610 uint32_t output; 611 int head; 612 }; 613 614 struct nv04_mode_state { 615 struct nv04_crtc_reg crtc_reg[2]; 616 uint32_t pllsel; 617 uint32_t sel_clk; 618 }; 619 620 enum nouveau_card_type { 621 NV_04 = 0x00, 622 NV_10 = 0x10, 623 NV_20 = 0x20, 624 NV_30 = 0x30, 625 NV_40 = 0x40, 626 NV_50 = 0x50, 627 NV_C0 = 0xc0, 628 }; 629 630 struct drm_nouveau_private { 631 struct drm_device *dev; 632 633 /* the card type, takes NV_* as values */ 634 enum nouveau_card_type card_type; 635 /* exact chipset, derived from NV_PMC_BOOT_0 */ 636 int chipset; 637 int flags; 638 639 void __iomem *mmio; 640 641 spinlock_t ramin_lock; 642 void __iomem *ramin; 643 u32 ramin_size; 644 u32 ramin_base; 645 bool ramin_available; 646 struct drm_mm ramin_heap; 647 struct list_head gpuobj_list; 648 struct list_head classes; 649 650 struct nouveau_bo *vga_ram; 651 652 /* interrupt handling */ 653 void (*irq_handler[32])(struct drm_device *); 654 bool msi_enabled; 655 struct workqueue_struct *wq; 656 struct work_struct irq_work; 657 658 struct list_head vbl_waiting; 659 660 struct { 661 struct drm_global_reference mem_global_ref; 662 struct ttm_bo_global_ref bo_global_ref; 663 struct ttm_bo_device bdev; 664 atomic_t validate_sequence; 665 } ttm; 666 667 struct { 668 spinlock_t lock; 669 struct drm_mm heap; 670 struct nouveau_bo *bo; 671 } fence; 672 673 struct { 674 spinlock_t lock; 675 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; 676 } channels; 677 678 struct nouveau_engine engine; 679 struct nouveau_channel *channel; 680 681 /* For PFIFO and PGRAPH. */ 682 spinlock_t context_switch_lock; 683 684 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ 685 struct nouveau_ramht *ramht; 686 struct nouveau_gpuobj *ramfc; 687 struct nouveau_gpuobj *ramro; 688 689 uint32_t ramin_rsvd_vram; 690 691 struct { 692 enum { 693 NOUVEAU_GART_NONE = 0, 694 NOUVEAU_GART_AGP, 695 NOUVEAU_GART_SGDMA 696 } type; 697 uint64_t aper_base; 698 uint64_t aper_size; 699 uint64_t aper_free; 700 701 struct nouveau_gpuobj *sg_ctxdma; 702 struct nouveau_vma vma; 703 } gart_info; 704 705 /* nv10-nv40 tiling regions */ 706 struct { 707 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; 708 spinlock_t lock; 709 } tile; 710 711 /* VRAM/fb configuration */ 712 uint64_t vram_size; 713 uint64_t vram_sys_base; 714 u32 vram_rblock_size; 715 716 uint64_t fb_phys; 717 uint64_t fb_available_size; 718 uint64_t fb_mappable_pages; 719 uint64_t fb_aper_free; 720 int fb_mtrr; 721 722 /* BAR control (NV50-) */ 723 struct nouveau_vm *bar1_vm; 724 struct nouveau_vm *bar3_vm; 725 726 /* G8x/G9x virtual address space */ 727 struct nouveau_vm *chan_vm; 728 729 struct nvbios vbios; 730 731 struct nv04_mode_state mode_reg; 732 struct nv04_mode_state saved_reg; 733 uint32_t saved_vga_font[4][16384]; 734 uint32_t crtc_owner; 735 uint32_t dac_users[4]; 736 737 struct nouveau_suspend_resume { 738 uint32_t *ramin_copy; 739 } susres; 740 741 struct backlight_device *backlight; 742 743 struct nouveau_channel *evo; 744 u32 evo_alloc; 745 struct { 746 struct dcb_entry *dcb; 747 u16 script; 748 u32 pclk; 749 } evo_irq; 750 751 struct { 752 struct dentry *channel_root; 753 } debugfs; 754 755 struct nouveau_fbdev *nfbdev; 756 struct apertures_struct *apertures; 757 758 bool powered_down; 759 }; 760 761 static inline struct drm_nouveau_private * 762 nouveau_private(struct drm_device *dev) 763 { 764 return dev->dev_private; 765 } 766 767 static inline struct drm_nouveau_private * 768 nouveau_bdev(struct ttm_bo_device *bd) 769 { 770 return container_of(bd, struct drm_nouveau_private, ttm.bdev); 771 } 772 773 static inline int 774 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) 775 { 776 struct nouveau_bo *prev; 777 778 if (!pnvbo) 779 return -EINVAL; 780 prev = *pnvbo; 781 782 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; 783 if (prev) { 784 struct ttm_buffer_object *bo = &prev->bo; 785 786 ttm_bo_unref(&bo); 787 } 788 789 return 0; 790 } 791 792 /* nouveau_drv.c */ 793 extern int nouveau_agpmode; 794 extern int nouveau_duallink; 795 extern int nouveau_uscript_lvds; 796 extern int nouveau_uscript_tmds; 797 extern int nouveau_vram_pushbuf; 798 extern int nouveau_vram_notify; 799 extern int nouveau_fbpercrtc; 800 extern int nouveau_tv_disable; 801 extern char *nouveau_tv_norm; 802 extern int nouveau_reg_debug; 803 extern char *nouveau_vbios; 804 extern int nouveau_ignorelid; 805 extern int nouveau_nofbaccel; 806 extern int nouveau_noaccel; 807 extern int nouveau_force_post; 808 extern int nouveau_override_conntype; 809 extern char *nouveau_perflvl; 810 extern int nouveau_perflvl_wr; 811 extern int nouveau_msi; 812 813 extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); 814 extern int nouveau_pci_resume(struct pci_dev *pdev); 815 816 /* nouveau_state.c */ 817 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); 818 extern int nouveau_load(struct drm_device *, unsigned long flags); 819 extern int nouveau_firstopen(struct drm_device *); 820 extern void nouveau_lastclose(struct drm_device *); 821 extern int nouveau_unload(struct drm_device *); 822 extern int nouveau_ioctl_getparam(struct drm_device *, void *data, 823 struct drm_file *); 824 extern int nouveau_ioctl_setparam(struct drm_device *, void *data, 825 struct drm_file *); 826 extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, 827 uint32_t reg, uint32_t mask, uint32_t val); 828 extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, 829 uint32_t reg, uint32_t mask, uint32_t val); 830 extern bool nouveau_wait_for_idle(struct drm_device *); 831 extern int nouveau_card_init(struct drm_device *); 832 833 /* nouveau_mem.c */ 834 extern int nouveau_mem_vram_init(struct drm_device *); 835 extern void nouveau_mem_vram_fini(struct drm_device *); 836 extern int nouveau_mem_gart_init(struct drm_device *); 837 extern void nouveau_mem_gart_fini(struct drm_device *); 838 extern int nouveau_mem_init_agp(struct drm_device *); 839 extern int nouveau_mem_reset_agp(struct drm_device *); 840 extern void nouveau_mem_close(struct drm_device *); 841 extern int nouveau_mem_detect(struct drm_device *); 842 extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); 843 extern struct nouveau_tile_reg *nv10_mem_set_tiling( 844 struct drm_device *dev, uint32_t addr, uint32_t size, 845 uint32_t pitch, uint32_t flags); 846 extern void nv10_mem_put_tile_region(struct drm_device *dev, 847 struct nouveau_tile_reg *tile, 848 struct nouveau_fence *fence); 849 extern const struct ttm_mem_type_manager_func nouveau_vram_manager; 850 851 /* nvc0_vram.c */ 852 extern const struct ttm_mem_type_manager_func nvc0_vram_manager; 853 854 /* nouveau_notifier.c */ 855 extern int nouveau_notifier_init_channel(struct nouveau_channel *); 856 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); 857 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, 858 int cout, uint32_t *offset); 859 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); 860 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, 861 struct drm_file *); 862 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, 863 struct drm_file *); 864 865 /* nouveau_channel.c */ 866 extern struct drm_ioctl_desc nouveau_ioctls[]; 867 extern int nouveau_max_ioctl; 868 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); 869 extern int nouveau_channel_alloc(struct drm_device *dev, 870 struct nouveau_channel **chan, 871 struct drm_file *file_priv, 872 uint32_t fb_ctxdma, uint32_t tt_ctxdma); 873 extern struct nouveau_channel * 874 nouveau_channel_get_unlocked(struct nouveau_channel *); 875 extern struct nouveau_channel * 876 nouveau_channel_get(struct drm_device *, struct drm_file *, int id); 877 extern void nouveau_channel_put_unlocked(struct nouveau_channel **); 878 extern void nouveau_channel_put(struct nouveau_channel **); 879 extern void nouveau_channel_ref(struct nouveau_channel *chan, 880 struct nouveau_channel **pchan); 881 extern void nouveau_channel_idle(struct nouveau_channel *chan); 882 883 /* nouveau_object.c */ 884 #define NVOBJ_CLASS(d,c,e) do { \ 885 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ 886 if (ret) \ 887 return ret; \ 888 } while(0) 889 890 #define NVOBJ_MTHD(d,c,m,e) do { \ 891 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ 892 if (ret) \ 893 return ret; \ 894 } while(0) 895 896 extern int nouveau_gpuobj_early_init(struct drm_device *); 897 extern int nouveau_gpuobj_init(struct drm_device *); 898 extern void nouveau_gpuobj_takedown(struct drm_device *); 899 extern int nouveau_gpuobj_suspend(struct drm_device *dev); 900 extern void nouveau_gpuobj_resume(struct drm_device *dev); 901 extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); 902 extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, 903 int (*exec)(struct nouveau_channel *, 904 u32 class, u32 mthd, u32 data)); 905 extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 906 extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); 907 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 908 uint32_t vram_h, uint32_t tt_h); 909 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 910 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, 911 uint32_t size, int align, uint32_t flags, 912 struct nouveau_gpuobj **); 913 extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, 914 struct nouveau_gpuobj **); 915 extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, 916 u32 size, u32 flags, 917 struct nouveau_gpuobj **); 918 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, 919 uint64_t offset, uint64_t size, int access, 920 int target, struct nouveau_gpuobj **); 921 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); 922 extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, 923 u64 size, int target, int access, u32 type, 924 u32 comp, struct nouveau_gpuobj **pobj); 925 extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, 926 int class, u64 base, u64 size, int target, 927 int access, u32 type, u32 comp); 928 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, 929 struct drm_file *); 930 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, 931 struct drm_file *); 932 933 /* nouveau_irq.c */ 934 extern int nouveau_irq_init(struct drm_device *); 935 extern void nouveau_irq_fini(struct drm_device *); 936 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); 937 extern void nouveau_irq_register(struct drm_device *, int status_bit, 938 void (*)(struct drm_device *)); 939 extern void nouveau_irq_unregister(struct drm_device *, int status_bit); 940 extern void nouveau_irq_preinstall(struct drm_device *); 941 extern int nouveau_irq_postinstall(struct drm_device *); 942 extern void nouveau_irq_uninstall(struct drm_device *); 943 944 /* nouveau_sgdma.c */ 945 extern int nouveau_sgdma_init(struct drm_device *); 946 extern void nouveau_sgdma_takedown(struct drm_device *); 947 extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, 948 uint32_t offset); 949 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); 950 951 /* nouveau_debugfs.c */ 952 #if defined(CONFIG_DRM_NOUVEAU_DEBUG) 953 extern int nouveau_debugfs_init(struct drm_minor *); 954 extern void nouveau_debugfs_takedown(struct drm_minor *); 955 extern int nouveau_debugfs_channel_init(struct nouveau_channel *); 956 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); 957 #else 958 static inline int 959 nouveau_debugfs_init(struct drm_minor *minor) 960 { 961 return 0; 962 } 963 964 static inline void nouveau_debugfs_takedown(struct drm_minor *minor) 965 { 966 } 967 968 static inline int 969 nouveau_debugfs_channel_init(struct nouveau_channel *chan) 970 { 971 return 0; 972 } 973 974 static inline void 975 nouveau_debugfs_channel_fini(struct nouveau_channel *chan) 976 { 977 } 978 #endif 979 980 /* nouveau_dma.c */ 981 extern void nouveau_dma_pre_init(struct nouveau_channel *); 982 extern int nouveau_dma_init(struct nouveau_channel *); 983 extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); 984 985 /* nouveau_acpi.c */ 986 #define ROM_BIOS_PAGE 4096 987 #if defined(CONFIG_ACPI) 988 void nouveau_register_dsm_handler(void); 989 void nouveau_unregister_dsm_handler(void); 990 int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); 991 bool nouveau_acpi_rom_supported(struct pci_dev *pdev); 992 int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); 993 #else 994 static inline void nouveau_register_dsm_handler(void) {} 995 static inline void nouveau_unregister_dsm_handler(void) {} 996 static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } 997 static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } 998 static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } 999 #endif 1000 1001 /* nouveau_backlight.c */ 1002 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1003 extern int nouveau_backlight_init(struct drm_device *); 1004 extern void nouveau_backlight_exit(struct drm_device *); 1005 #else 1006 static inline int nouveau_backlight_init(struct drm_device *dev) 1007 { 1008 return 0; 1009 } 1010 1011 static inline void nouveau_backlight_exit(struct drm_device *dev) { } 1012 #endif 1013 1014 /* nouveau_bios.c */ 1015 extern int nouveau_bios_init(struct drm_device *); 1016 extern void nouveau_bios_takedown(struct drm_device *dev); 1017 extern int nouveau_run_vbios_init(struct drm_device *); 1018 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, 1019 struct dcb_entry *); 1020 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, 1021 enum dcb_gpio_tag); 1022 extern struct dcb_connector_table_entry * 1023 nouveau_bios_connector_entry(struct drm_device *, int index); 1024 extern u32 get_pll_register(struct drm_device *, enum pll_types); 1025 extern int get_pll_limits(struct drm_device *, uint32_t limit_match, 1026 struct pll_lims *); 1027 extern int nouveau_bios_run_display_table(struct drm_device *, 1028 struct dcb_entry *, 1029 uint32_t script, int pxclk); 1030 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, 1031 int *length); 1032 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); 1033 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); 1034 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, 1035 bool *dl, bool *if_is_24bit); 1036 extern int run_tmds_table(struct drm_device *, struct dcb_entry *, 1037 int head, int pxclk); 1038 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, 1039 enum LVDS_script, int pxclk); 1040 1041 /* nouveau_ttm.c */ 1042 int nouveau_ttm_global_init(struct drm_nouveau_private *); 1043 void nouveau_ttm_global_release(struct drm_nouveau_private *); 1044 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); 1045 1046 /* nouveau_dp.c */ 1047 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, 1048 uint8_t *data, int data_nr); 1049 bool nouveau_dp_detect(struct drm_encoder *); 1050 bool nouveau_dp_link_train(struct drm_encoder *); 1051 1052 /* nv04_fb.c */ 1053 extern int nv04_fb_init(struct drm_device *); 1054 extern void nv04_fb_takedown(struct drm_device *); 1055 1056 /* nv10_fb.c */ 1057 extern int nv10_fb_init(struct drm_device *); 1058 extern void nv10_fb_takedown(struct drm_device *); 1059 extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, 1060 uint32_t addr, uint32_t size, 1061 uint32_t pitch, uint32_t flags); 1062 extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); 1063 extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); 1064 1065 /* nv30_fb.c */ 1066 extern int nv30_fb_init(struct drm_device *); 1067 extern void nv30_fb_takedown(struct drm_device *); 1068 extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, 1069 uint32_t addr, uint32_t size, 1070 uint32_t pitch, uint32_t flags); 1071 extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); 1072 1073 /* nv40_fb.c */ 1074 extern int nv40_fb_init(struct drm_device *); 1075 extern void nv40_fb_takedown(struct drm_device *); 1076 extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 1077 1078 /* nv50_fb.c */ 1079 extern int nv50_fb_init(struct drm_device *); 1080 extern void nv50_fb_takedown(struct drm_device *); 1081 extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); 1082 1083 /* nvc0_fb.c */ 1084 extern int nvc0_fb_init(struct drm_device *); 1085 extern void nvc0_fb_takedown(struct drm_device *); 1086 1087 /* nv04_fifo.c */ 1088 extern int nv04_fifo_init(struct drm_device *); 1089 extern void nv04_fifo_fini(struct drm_device *); 1090 extern void nv04_fifo_disable(struct drm_device *); 1091 extern void nv04_fifo_enable(struct drm_device *); 1092 extern bool nv04_fifo_reassign(struct drm_device *, bool); 1093 extern bool nv04_fifo_cache_pull(struct drm_device *, bool); 1094 extern int nv04_fifo_channel_id(struct drm_device *); 1095 extern int nv04_fifo_create_context(struct nouveau_channel *); 1096 extern void nv04_fifo_destroy_context(struct nouveau_channel *); 1097 extern int nv04_fifo_load_context(struct nouveau_channel *); 1098 extern int nv04_fifo_unload_context(struct drm_device *); 1099 extern void nv04_fifo_isr(struct drm_device *); 1100 1101 /* nv10_fifo.c */ 1102 extern int nv10_fifo_init(struct drm_device *); 1103 extern int nv10_fifo_channel_id(struct drm_device *); 1104 extern int nv10_fifo_create_context(struct nouveau_channel *); 1105 extern int nv10_fifo_load_context(struct nouveau_channel *); 1106 extern int nv10_fifo_unload_context(struct drm_device *); 1107 1108 /* nv40_fifo.c */ 1109 extern int nv40_fifo_init(struct drm_device *); 1110 extern int nv40_fifo_create_context(struct nouveau_channel *); 1111 extern int nv40_fifo_load_context(struct nouveau_channel *); 1112 extern int nv40_fifo_unload_context(struct drm_device *); 1113 1114 /* nv50_fifo.c */ 1115 extern int nv50_fifo_init(struct drm_device *); 1116 extern void nv50_fifo_takedown(struct drm_device *); 1117 extern int nv50_fifo_channel_id(struct drm_device *); 1118 extern int nv50_fifo_create_context(struct nouveau_channel *); 1119 extern void nv50_fifo_destroy_context(struct nouveau_channel *); 1120 extern int nv50_fifo_load_context(struct nouveau_channel *); 1121 extern int nv50_fifo_unload_context(struct drm_device *); 1122 extern void nv50_fifo_tlb_flush(struct drm_device *dev); 1123 1124 /* nvc0_fifo.c */ 1125 extern int nvc0_fifo_init(struct drm_device *); 1126 extern void nvc0_fifo_takedown(struct drm_device *); 1127 extern void nvc0_fifo_disable(struct drm_device *); 1128 extern void nvc0_fifo_enable(struct drm_device *); 1129 extern bool nvc0_fifo_reassign(struct drm_device *, bool); 1130 extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); 1131 extern int nvc0_fifo_channel_id(struct drm_device *); 1132 extern int nvc0_fifo_create_context(struct nouveau_channel *); 1133 extern void nvc0_fifo_destroy_context(struct nouveau_channel *); 1134 extern int nvc0_fifo_load_context(struct nouveau_channel *); 1135 extern int nvc0_fifo_unload_context(struct drm_device *); 1136 1137 /* nv04_graph.c */ 1138 extern int nv04_graph_init(struct drm_device *); 1139 extern void nv04_graph_takedown(struct drm_device *); 1140 extern void nv04_graph_fifo_access(struct drm_device *, bool); 1141 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); 1142 extern int nv04_graph_create_context(struct nouveau_channel *); 1143 extern void nv04_graph_destroy_context(struct nouveau_channel *); 1144 extern int nv04_graph_load_context(struct nouveau_channel *); 1145 extern int nv04_graph_unload_context(struct drm_device *); 1146 extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1147 u32 class, u32 mthd, u32 data); 1148 extern struct nouveau_bitfield nv04_graph_nsource[]; 1149 1150 /* nv10_graph.c */ 1151 extern int nv10_graph_init(struct drm_device *); 1152 extern void nv10_graph_takedown(struct drm_device *); 1153 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); 1154 extern int nv10_graph_create_context(struct nouveau_channel *); 1155 extern void nv10_graph_destroy_context(struct nouveau_channel *); 1156 extern int nv10_graph_load_context(struct nouveau_channel *); 1157 extern int nv10_graph_unload_context(struct drm_device *); 1158 extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1159 extern struct nouveau_bitfield nv10_graph_intr[]; 1160 extern struct nouveau_bitfield nv10_graph_nstatus[]; 1161 1162 /* nv20_graph.c */ 1163 extern int nv20_graph_create_context(struct nouveau_channel *); 1164 extern void nv20_graph_destroy_context(struct nouveau_channel *); 1165 extern int nv20_graph_load_context(struct nouveau_channel *); 1166 extern int nv20_graph_unload_context(struct drm_device *); 1167 extern int nv20_graph_init(struct drm_device *); 1168 extern void nv20_graph_takedown(struct drm_device *); 1169 extern int nv30_graph_init(struct drm_device *); 1170 extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); 1171 1172 /* nv40_graph.c */ 1173 extern int nv40_graph_init(struct drm_device *); 1174 extern void nv40_graph_takedown(struct drm_device *); 1175 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); 1176 extern int nv40_graph_create_context(struct nouveau_channel *); 1177 extern void nv40_graph_destroy_context(struct nouveau_channel *); 1178 extern int nv40_graph_load_context(struct nouveau_channel *); 1179 extern int nv40_graph_unload_context(struct drm_device *); 1180 extern void nv40_grctx_init(struct nouveau_grctx *); 1181 extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); 1182 1183 /* nv50_graph.c */ 1184 extern int nv50_graph_init(struct drm_device *); 1185 extern void nv50_graph_takedown(struct drm_device *); 1186 extern void nv50_graph_fifo_access(struct drm_device *, bool); 1187 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); 1188 extern int nv50_graph_create_context(struct nouveau_channel *); 1189 extern void nv50_graph_destroy_context(struct nouveau_channel *); 1190 extern int nv50_graph_load_context(struct nouveau_channel *); 1191 extern int nv50_graph_unload_context(struct drm_device *); 1192 extern int nv50_grctx_init(struct nouveau_grctx *); 1193 extern void nv50_graph_tlb_flush(struct drm_device *dev); 1194 extern void nv86_graph_tlb_flush(struct drm_device *dev); 1195 extern struct nouveau_enum nv50_data_error_names[]; 1196 1197 /* nvc0_graph.c */ 1198 extern int nvc0_graph_init(struct drm_device *); 1199 extern void nvc0_graph_takedown(struct drm_device *); 1200 extern void nvc0_graph_fifo_access(struct drm_device *, bool); 1201 extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); 1202 extern int nvc0_graph_create_context(struct nouveau_channel *); 1203 extern void nvc0_graph_destroy_context(struct nouveau_channel *); 1204 extern int nvc0_graph_load_context(struct nouveau_channel *); 1205 extern int nvc0_graph_unload_context(struct drm_device *); 1206 1207 /* nv84_crypt.c */ 1208 extern int nv84_crypt_init(struct drm_device *dev); 1209 extern void nv84_crypt_fini(struct drm_device *dev); 1210 extern int nv84_crypt_create_context(struct nouveau_channel *); 1211 extern void nv84_crypt_destroy_context(struct nouveau_channel *); 1212 extern void nv84_crypt_tlb_flush(struct drm_device *dev); 1213 1214 /* nv04_instmem.c */ 1215 extern int nv04_instmem_init(struct drm_device *); 1216 extern void nv04_instmem_takedown(struct drm_device *); 1217 extern int nv04_instmem_suspend(struct drm_device *); 1218 extern void nv04_instmem_resume(struct drm_device *); 1219 extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1220 extern void nv04_instmem_put(struct nouveau_gpuobj *); 1221 extern int nv04_instmem_map(struct nouveau_gpuobj *); 1222 extern void nv04_instmem_unmap(struct nouveau_gpuobj *); 1223 extern void nv04_instmem_flush(struct drm_device *); 1224 1225 /* nv50_instmem.c */ 1226 extern int nv50_instmem_init(struct drm_device *); 1227 extern void nv50_instmem_takedown(struct drm_device *); 1228 extern int nv50_instmem_suspend(struct drm_device *); 1229 extern void nv50_instmem_resume(struct drm_device *); 1230 extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); 1231 extern void nv50_instmem_put(struct nouveau_gpuobj *); 1232 extern int nv50_instmem_map(struct nouveau_gpuobj *); 1233 extern void nv50_instmem_unmap(struct nouveau_gpuobj *); 1234 extern void nv50_instmem_flush(struct drm_device *); 1235 extern void nv84_instmem_flush(struct drm_device *); 1236 1237 /* nvc0_instmem.c */ 1238 extern int nvc0_instmem_init(struct drm_device *); 1239 extern void nvc0_instmem_takedown(struct drm_device *); 1240 extern int nvc0_instmem_suspend(struct drm_device *); 1241 extern void nvc0_instmem_resume(struct drm_device *); 1242 1243 /* nv04_mc.c */ 1244 extern int nv04_mc_init(struct drm_device *); 1245 extern void nv04_mc_takedown(struct drm_device *); 1246 1247 /* nv40_mc.c */ 1248 extern int nv40_mc_init(struct drm_device *); 1249 extern void nv40_mc_takedown(struct drm_device *); 1250 1251 /* nv50_mc.c */ 1252 extern int nv50_mc_init(struct drm_device *); 1253 extern void nv50_mc_takedown(struct drm_device *); 1254 1255 /* nv04_timer.c */ 1256 extern int nv04_timer_init(struct drm_device *); 1257 extern uint64_t nv04_timer_read(struct drm_device *); 1258 extern void nv04_timer_takedown(struct drm_device *); 1259 1260 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, 1261 unsigned long arg); 1262 1263 /* nv04_dac.c */ 1264 extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); 1265 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); 1266 extern int nv04_dac_output_offset(struct drm_encoder *encoder); 1267 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); 1268 extern bool nv04_dac_in_use(struct drm_encoder *encoder); 1269 1270 /* nv04_dfp.c */ 1271 extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); 1272 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); 1273 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, 1274 int head, bool dl); 1275 extern void nv04_dfp_disable(struct drm_device *dev, int head); 1276 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); 1277 1278 /* nv04_tv.c */ 1279 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); 1280 extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); 1281 1282 /* nv17_tv.c */ 1283 extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); 1284 1285 /* nv04_display.c */ 1286 extern int nv04_display_early_init(struct drm_device *); 1287 extern void nv04_display_late_takedown(struct drm_device *); 1288 extern int nv04_display_create(struct drm_device *); 1289 extern int nv04_display_init(struct drm_device *); 1290 extern void nv04_display_destroy(struct drm_device *); 1291 1292 /* nv04_crtc.c */ 1293 extern int nv04_crtc_create(struct drm_device *, int index); 1294 1295 /* nouveau_bo.c */ 1296 extern struct ttm_bo_driver nouveau_bo_driver; 1297 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, 1298 int size, int align, uint32_t flags, 1299 uint32_t tile_mode, uint32_t tile_flags, 1300 bool no_vm, bool mappable, struct nouveau_bo **); 1301 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); 1302 extern int nouveau_bo_unpin(struct nouveau_bo *); 1303 extern int nouveau_bo_map(struct nouveau_bo *); 1304 extern void nouveau_bo_unmap(struct nouveau_bo *); 1305 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, 1306 uint32_t busy); 1307 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); 1308 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1309 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1310 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1311 extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); 1312 extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, 1313 bool no_wait_reserve, bool no_wait_gpu); 1314 1315 /* nouveau_fence.c */ 1316 struct nouveau_fence; 1317 extern int nouveau_fence_init(struct drm_device *); 1318 extern void nouveau_fence_fini(struct drm_device *); 1319 extern int nouveau_fence_channel_init(struct nouveau_channel *); 1320 extern void nouveau_fence_channel_fini(struct nouveau_channel *); 1321 extern void nouveau_fence_update(struct nouveau_channel *); 1322 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, 1323 bool emit); 1324 extern int nouveau_fence_emit(struct nouveau_fence *); 1325 extern void nouveau_fence_work(struct nouveau_fence *fence, 1326 void (*work)(void *priv, bool signalled), 1327 void *priv); 1328 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); 1329 1330 extern bool __nouveau_fence_signalled(void *obj, void *arg); 1331 extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); 1332 extern int __nouveau_fence_flush(void *obj, void *arg); 1333 extern void __nouveau_fence_unref(void **obj); 1334 extern void *__nouveau_fence_ref(void *obj); 1335 1336 static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) 1337 { 1338 return __nouveau_fence_signalled(obj, NULL); 1339 } 1340 static inline int 1341 nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) 1342 { 1343 return __nouveau_fence_wait(obj, NULL, lazy, intr); 1344 } 1345 extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); 1346 static inline int nouveau_fence_flush(struct nouveau_fence *obj) 1347 { 1348 return __nouveau_fence_flush(obj, NULL); 1349 } 1350 static inline void nouveau_fence_unref(struct nouveau_fence **obj) 1351 { 1352 __nouveau_fence_unref((void **)obj); 1353 } 1354 static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) 1355 { 1356 return __nouveau_fence_ref(obj); 1357 } 1358 1359 /* nouveau_gem.c */ 1360 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, 1361 int size, int align, uint32_t flags, 1362 uint32_t tile_mode, uint32_t tile_flags, 1363 bool no_vm, bool mappable, struct nouveau_bo **); 1364 extern int nouveau_gem_object_new(struct drm_gem_object *); 1365 extern void nouveau_gem_object_del(struct drm_gem_object *); 1366 extern int nouveau_gem_ioctl_new(struct drm_device *, void *, 1367 struct drm_file *); 1368 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, 1369 struct drm_file *); 1370 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, 1371 struct drm_file *); 1372 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, 1373 struct drm_file *); 1374 extern int nouveau_gem_ioctl_info(struct drm_device *, void *, 1375 struct drm_file *); 1376 1377 /* nouveau_display.c */ 1378 int nouveau_vblank_enable(struct drm_device *dev, int crtc); 1379 void nouveau_vblank_disable(struct drm_device *dev, int crtc); 1380 int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1381 struct drm_pending_vblank_event *event); 1382 int nouveau_finish_page_flip(struct nouveau_channel *, 1383 struct nouveau_page_flip_state *); 1384 1385 /* nv10_gpio.c */ 1386 int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1387 int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1388 1389 /* nv50_gpio.c */ 1390 int nv50_gpio_init(struct drm_device *dev); 1391 void nv50_gpio_fini(struct drm_device *dev); 1392 int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); 1393 int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); 1394 int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, 1395 void (*)(void *, int), void *); 1396 void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, 1397 void (*)(void *, int), void *); 1398 bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); 1399 1400 /* nv50_calc. */ 1401 int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, 1402 int *N1, int *M1, int *N2, int *M2, int *P); 1403 int nv50_calc_pll2(struct drm_device *, struct pll_lims *, 1404 int clk, int *N, int *fN, int *M, int *P); 1405 1406 #ifndef ioread32_native 1407 #ifdef __BIG_ENDIAN 1408 #define ioread16_native ioread16be 1409 #define iowrite16_native iowrite16be 1410 #define ioread32_native ioread32be 1411 #define iowrite32_native iowrite32be 1412 #else /* def __BIG_ENDIAN */ 1413 #define ioread16_native ioread16 1414 #define iowrite16_native iowrite16 1415 #define ioread32_native ioread32 1416 #define iowrite32_native iowrite32 1417 #endif /* def __BIG_ENDIAN else */ 1418 #endif /* !ioread32_native */ 1419 1420 /* channel control reg access */ 1421 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) 1422 { 1423 return ioread32_native(chan->user + reg); 1424 } 1425 1426 static inline void nvchan_wr32(struct nouveau_channel *chan, 1427 unsigned reg, u32 val) 1428 { 1429 iowrite32_native(val, chan->user + reg); 1430 } 1431 1432 /* register access */ 1433 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) 1434 { 1435 struct drm_nouveau_private *dev_priv = dev->dev_private; 1436 return ioread32_native(dev_priv->mmio + reg); 1437 } 1438 1439 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) 1440 { 1441 struct drm_nouveau_private *dev_priv = dev->dev_private; 1442 iowrite32_native(val, dev_priv->mmio + reg); 1443 } 1444 1445 static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) 1446 { 1447 u32 tmp = nv_rd32(dev, reg); 1448 nv_wr32(dev, reg, (tmp & ~mask) | val); 1449 return tmp; 1450 } 1451 1452 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) 1453 { 1454 struct drm_nouveau_private *dev_priv = dev->dev_private; 1455 return ioread8(dev_priv->mmio + reg); 1456 } 1457 1458 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) 1459 { 1460 struct drm_nouveau_private *dev_priv = dev->dev_private; 1461 iowrite8(val, dev_priv->mmio + reg); 1462 } 1463 1464 #define nv_wait(dev, reg, mask, val) \ 1465 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) 1466 #define nv_wait_ne(dev, reg, mask, val) \ 1467 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) 1468 1469 /* PRAMIN access */ 1470 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) 1471 { 1472 struct drm_nouveau_private *dev_priv = dev->dev_private; 1473 return ioread32_native(dev_priv->ramin + offset); 1474 } 1475 1476 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) 1477 { 1478 struct drm_nouveau_private *dev_priv = dev->dev_private; 1479 iowrite32_native(val, dev_priv->ramin + offset); 1480 } 1481 1482 /* object access */ 1483 extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); 1484 extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); 1485 1486 /* 1487 * Logging 1488 * Argument d is (struct drm_device *). 1489 */ 1490 #define NV_PRINTK(level, d, fmt, arg...) \ 1491 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ 1492 pci_name(d->pdev), ##arg) 1493 #ifndef NV_DEBUG_NOTRACE 1494 #define NV_DEBUG(d, fmt, arg...) do { \ 1495 if (drm_debug & DRM_UT_DRIVER) { \ 1496 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1497 __LINE__, ##arg); \ 1498 } \ 1499 } while (0) 1500 #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1501 if (drm_debug & DRM_UT_KMS) { \ 1502 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ 1503 __LINE__, ##arg); \ 1504 } \ 1505 } while (0) 1506 #else 1507 #define NV_DEBUG(d, fmt, arg...) do { \ 1508 if (drm_debug & DRM_UT_DRIVER) \ 1509 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1510 } while (0) 1511 #define NV_DEBUG_KMS(d, fmt, arg...) do { \ 1512 if (drm_debug & DRM_UT_KMS) \ 1513 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ 1514 } while (0) 1515 #endif 1516 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) 1517 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1518 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) 1519 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) 1520 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) 1521 1522 /* nouveau_reg_debug bitmask */ 1523 enum { 1524 NOUVEAU_REG_DEBUG_MC = 0x1, 1525 NOUVEAU_REG_DEBUG_VIDEO = 0x2, 1526 NOUVEAU_REG_DEBUG_FB = 0x4, 1527 NOUVEAU_REG_DEBUG_EXTDEV = 0x8, 1528 NOUVEAU_REG_DEBUG_CRTC = 0x10, 1529 NOUVEAU_REG_DEBUG_RAMDAC = 0x20, 1530 NOUVEAU_REG_DEBUG_VGACRTC = 0x40, 1531 NOUVEAU_REG_DEBUG_RMVIO = 0x80, 1532 NOUVEAU_REG_DEBUG_VGAATTR = 0x100, 1533 NOUVEAU_REG_DEBUG_EVO = 0x200, 1534 }; 1535 1536 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ 1537 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ 1538 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ 1539 } while (0) 1540 1541 static inline bool 1542 nv_two_heads(struct drm_device *dev) 1543 { 1544 struct drm_nouveau_private *dev_priv = dev->dev_private; 1545 const int impl = dev->pci_device & 0x0ff0; 1546 1547 if (dev_priv->card_type >= NV_10 && impl != 0x0100 && 1548 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) 1549 return true; 1550 1551 return false; 1552 } 1553 1554 static inline bool 1555 nv_gf4_disp_arch(struct drm_device *dev) 1556 { 1557 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; 1558 } 1559 1560 static inline bool 1561 nv_two_reg_pll(struct drm_device *dev) 1562 { 1563 struct drm_nouveau_private *dev_priv = dev->dev_private; 1564 const int impl = dev->pci_device & 0x0ff0; 1565 1566 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) 1567 return true; 1568 return false; 1569 } 1570 1571 static inline bool 1572 nv_match_device(struct drm_device *dev, unsigned device, 1573 unsigned sub_vendor, unsigned sub_device) 1574 { 1575 return dev->pdev->device == device && 1576 dev->pdev->subsystem_vendor == sub_vendor && 1577 dev->pdev->subsystem_device == sub_device; 1578 } 1579 1580 /* returns 1 if device is one of the nv4x using the 0x4497 object class, 1581 * helpful to determine a number of other hardware features 1582 */ 1583 static inline int 1584 nv44_graph_class(struct drm_device *dev) 1585 { 1586 struct drm_nouveau_private *dev_priv = dev->dev_private; 1587 1588 if ((dev_priv->chipset & 0xf0) == 0x60) 1589 return 1; 1590 1591 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); 1592 } 1593 1594 /* memory type/access flags, do not match hardware values */ 1595 #define NV_MEM_ACCESS_RO 1 1596 #define NV_MEM_ACCESS_WO 2 1597 #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) 1598 #define NV_MEM_ACCESS_SYS 4 1599 #define NV_MEM_ACCESS_VM 8 1600 1601 #define NV_MEM_TARGET_VRAM 0 1602 #define NV_MEM_TARGET_PCI 1 1603 #define NV_MEM_TARGET_PCI_NOSNOOP 2 1604 #define NV_MEM_TARGET_VM 3 1605 #define NV_MEM_TARGET_GART 4 1606 1607 #define NV_MEM_TYPE_VM 0x7f 1608 #define NV_MEM_COMP_VM 0x03 1609 1610 /* NV_SW object class */ 1611 #define NV_SW 0x0000506e 1612 #define NV_SW_DMA_SEMAPHORE 0x00000060 1613 #define NV_SW_SEMAPHORE_OFFSET 0x00000064 1614 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 1615 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c 1616 #define NV_SW_YIELD 0x00000080 1617 #define NV_SW_DMA_VBLSEM 0x0000018c 1618 #define NV_SW_VBLSEM_OFFSET 0x00000400 1619 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 1620 #define NV_SW_VBLSEM_RELEASE 0x00000408 1621 #define NV_SW_PAGE_FLIP 0x00000500 1622 1623 #endif /* __NOUVEAU_DRV_H__ */ 1624