1 /* 2 * Copyright 2009 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <drm/drmP.h> 26 #include <drm/drm_dp_helper.h> 27 28 #include "nouveau_drm.h" 29 #include "nouveau_connector.h" 30 #include "nouveau_encoder.h" 31 #include "nouveau_crtc.h" 32 33 #include <core/class.h> 34 35 #include <subdev/gpio.h> 36 #include <subdev/i2c.h> 37 38 /****************************************************************************** 39 * link training 40 *****************************************************************************/ 41 struct dp_state { 42 struct nouveau_i2c_port *auxch; 43 struct nouveau_object *core; 44 struct dcb_output *dcb; 45 int crtc; 46 u8 *dpcd; 47 int link_nr; 48 u32 link_bw; 49 u8 stat[6]; 50 u8 conf[4]; 51 }; 52 53 static void 54 dp_set_link_config(struct drm_device *dev, struct dp_state *dp) 55 { 56 struct nouveau_drm *drm = nouveau_drm(dev); 57 struct dcb_output *dcb = dp->dcb; 58 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 59 const u32 moff = (dp->crtc << 3) | (link << 2) | or; 60 u8 sink[2]; 61 u32 data; 62 63 NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw); 64 65 /* set desired link configuration on the source */ 66 data = ((dp->link_bw / 27000) << 8) | dp->link_nr; 67 if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) 68 data |= NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH; 69 70 nv_call(dp->core, NV94_DISP_SOR_DP_LNKCTL + moff, data); 71 72 /* inform the sink of the new configuration */ 73 sink[0] = dp->link_bw / 27000; 74 sink[1] = dp->link_nr; 75 if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) 76 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 77 78 nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2); 79 } 80 81 static void 82 dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern) 83 { 84 struct nouveau_drm *drm = nouveau_drm(dev); 85 struct dcb_output *dcb = dp->dcb; 86 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 87 const u32 moff = (dp->crtc << 3) | (link << 2) | or; 88 u8 sink_tp; 89 90 NV_DEBUG(drm, "training pattern %d\n", pattern); 91 92 nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, pattern); 93 94 nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1); 95 sink_tp &= ~DP_TRAINING_PATTERN_MASK; 96 sink_tp |= pattern; 97 nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1); 98 } 99 100 static int 101 dp_link_train_commit(struct drm_device *dev, struct dp_state *dp) 102 { 103 struct nouveau_drm *drm = nouveau_drm(dev); 104 struct dcb_output *dcb = dp->dcb; 105 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 106 const u32 moff = (dp->crtc << 3) | (link << 2) | or; 107 int i; 108 109 for (i = 0; i < dp->link_nr; i++) { 110 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; 111 u8 lpre = (lane & 0x0c) >> 2; 112 u8 lvsw = (lane & 0x03) >> 0; 113 114 dp->conf[i] = (lpre << 3) | lvsw; 115 if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200) 116 dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED; 117 if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5) 118 dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 119 120 NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]); 121 122 nv_call(dp->core, NV94_DISP_SOR_DP_DRVCTL(i) + moff, (lvsw << 8) | lpre); 123 } 124 125 return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4); 126 } 127 128 static int 129 dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay) 130 { 131 struct nouveau_drm *drm = nouveau_drm(dev); 132 int ret; 133 134 udelay(delay); 135 136 ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6); 137 if (ret) 138 return ret; 139 140 NV_DEBUG(drm, "status %*ph\n", 6, dp->stat); 141 return 0; 142 } 143 144 static int 145 dp_link_train_cr(struct drm_device *dev, struct dp_state *dp) 146 { 147 bool cr_done = false, abort = false; 148 int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 149 int tries = 0, i; 150 151 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1); 152 153 do { 154 if (dp_link_train_commit(dev, dp) || 155 dp_link_train_update(dev, dp, 100)) 156 break; 157 158 cr_done = true; 159 for (i = 0; i < dp->link_nr; i++) { 160 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; 161 if (!(lane & DP_LANE_CR_DONE)) { 162 cr_done = false; 163 if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED) 164 abort = true; 165 break; 166 } 167 } 168 169 if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) { 170 voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 171 tries = 0; 172 } 173 } while (!cr_done && !abort && ++tries < 5); 174 175 return cr_done ? 0 : -1; 176 } 177 178 static int 179 dp_link_train_eq(struct drm_device *dev, struct dp_state *dp) 180 { 181 bool eq_done, cr_done = true; 182 int tries = 0, i; 183 184 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2); 185 186 do { 187 if (dp_link_train_update(dev, dp, 400)) 188 break; 189 190 eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE); 191 for (i = 0; i < dp->link_nr && eq_done; i++) { 192 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; 193 if (!(lane & DP_LANE_CR_DONE)) 194 cr_done = false; 195 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) || 196 !(lane & DP_LANE_SYMBOL_LOCKED)) 197 eq_done = false; 198 } 199 200 if (dp_link_train_commit(dev, dp)) 201 break; 202 } while (!eq_done && cr_done && ++tries <= 5); 203 204 return eq_done ? 0 : -1; 205 } 206 207 static void 208 dp_link_train_init(struct drm_device *dev, struct dp_state *dp, bool spread) 209 { 210 struct dcb_output *dcb = dp->dcb; 211 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 212 const u32 moff = (dp->crtc << 3) | (link << 2) | or; 213 214 nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, (spread ? 215 NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON : 216 NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF) | 217 NV94_DISP_SOR_DP_TRAIN_OP_INIT); 218 } 219 220 static void 221 dp_link_train_fini(struct drm_device *dev, struct dp_state *dp) 222 { 223 struct dcb_output *dcb = dp->dcb; 224 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 225 const u32 moff = (dp->crtc << 3) | (link << 2) | or; 226 227 nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, 228 NV94_DISP_SOR_DP_TRAIN_OP_FINI); 229 } 230 231 static bool 232 nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate, 233 struct nouveau_object *core) 234 { 235 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 236 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 237 struct nouveau_connector *nv_connector = 238 nouveau_encoder_connector_get(nv_encoder); 239 struct drm_device *dev = encoder->dev; 240 struct nouveau_drm *drm = nouveau_drm(dev); 241 struct nouveau_i2c *i2c = nouveau_i2c(drm->device); 242 struct nouveau_gpio *gpio = nouveau_gpio(drm->device); 243 const u32 bw_list[] = { 270000, 162000, 0 }; 244 const u32 *link_bw = bw_list; 245 struct dp_state dp; 246 247 dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index); 248 if (!dp.auxch) 249 return false; 250 251 dp.core = core; 252 dp.dcb = nv_encoder->dcb; 253 dp.crtc = nv_crtc->index; 254 dp.dpcd = nv_encoder->dp.dpcd; 255 256 /* adjust required bandwidth for 8B/10B coding overhead */ 257 datarate = (datarate / 8) * 10; 258 259 /* some sinks toggle hotplug in response to some of the actions 260 * we take during link training (DP_SET_POWER is one), we need 261 * to ignore them for the moment to avoid races. 262 */ 263 gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false); 264 265 /* enable down-spreading and execute pre-train script from vbios */ 266 dp_link_train_init(dev, &dp, nv_encoder->dp.dpcd[3] & 1); 267 268 /* start off at highest link rate supported by encoder and display */ 269 while (*link_bw > nv_encoder->dp.link_bw) 270 link_bw++; 271 272 while (link_bw[0]) { 273 /* find minimum required lane count at this link rate */ 274 dp.link_nr = nv_encoder->dp.link_nr; 275 while ((dp.link_nr >> 1) * link_bw[0] > datarate) 276 dp.link_nr >>= 1; 277 278 /* drop link rate to minimum with this lane count */ 279 while ((link_bw[1] * dp.link_nr) > datarate) 280 link_bw++; 281 dp.link_bw = link_bw[0]; 282 283 /* program selected link configuration */ 284 dp_set_link_config(dev, &dp); 285 286 /* attempt to train the link at this configuration */ 287 memset(dp.stat, 0x00, sizeof(dp.stat)); 288 if (!dp_link_train_cr(dev, &dp) && 289 !dp_link_train_eq(dev, &dp)) 290 break; 291 292 /* retry at lower rate */ 293 link_bw++; 294 } 295 296 /* finish link training */ 297 dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE); 298 299 /* execute post-train script from vbios */ 300 dp_link_train_fini(dev, &dp); 301 302 /* re-enable hotplug detect */ 303 gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true); 304 return true; 305 } 306 307 void 308 nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate, 309 struct nouveau_object *core) 310 { 311 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 312 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 313 struct nouveau_i2c *i2c = nouveau_i2c(drm->device); 314 struct nouveau_i2c_port *auxch; 315 u8 status; 316 317 auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index); 318 if (!auxch) 319 return; 320 321 if (mode == DRM_MODE_DPMS_ON) 322 status = DP_SET_POWER_D0; 323 else 324 status = DP_SET_POWER_D3; 325 326 nv_wraux(auxch, DP_SET_POWER, &status, 1); 327 328 if (mode == DRM_MODE_DPMS_ON) 329 nouveau_dp_link_train(encoder, datarate, core); 330 } 331 332 static void 333 nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch, 334 u8 *dpcd) 335 { 336 struct nouveau_drm *drm = nouveau_drm(dev); 337 u8 buf[3]; 338 339 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 340 return; 341 342 if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3)) 343 NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n", 344 buf[0], buf[1], buf[2]); 345 346 if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3)) 347 NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n", 348 buf[0], buf[1], buf[2]); 349 350 } 351 352 bool 353 nouveau_dp_detect(struct drm_encoder *encoder) 354 { 355 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 356 struct drm_device *dev = encoder->dev; 357 struct nouveau_drm *drm = nouveau_drm(dev); 358 struct nouveau_i2c *i2c = nouveau_i2c(drm->device); 359 struct nouveau_i2c_port *auxch; 360 u8 *dpcd = nv_encoder->dp.dpcd; 361 int ret; 362 363 auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index); 364 if (!auxch) 365 return false; 366 367 ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8); 368 if (ret) 369 return false; 370 371 nv_encoder->dp.link_bw = 27000 * dpcd[1]; 372 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; 373 374 NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n", 375 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); 376 NV_DEBUG(drm, "encoder: %dx%d\n", 377 nv_encoder->dcb->dpconf.link_nr, 378 nv_encoder->dcb->dpconf.link_bw); 379 380 if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr) 381 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr; 382 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) 383 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; 384 385 NV_DEBUG(drm, "maximum: %dx%d\n", 386 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); 387 388 nouveau_dp_probe_oui(dev, auxch, dpcd); 389 390 return true; 391 } 392