xref: /openbmc/linux/drivers/gpu/drm/nouveau/nouveau_dma.c (revision df2634f43f5106947f3735a0b61a6527a4b278cd)
1 /*
2  * Copyright (C) 2007 Ben Skeggs.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  */
26 
27 #include "drmP.h"
28 #include "drm.h"
29 #include "nouveau_drv.h"
30 #include "nouveau_dma.h"
31 #include "nouveau_ramht.h"
32 
33 void
34 nouveau_dma_pre_init(struct nouveau_channel *chan)
35 {
36 	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
37 	struct nouveau_bo *pushbuf = chan->pushbuf_bo;
38 
39 	if (dev_priv->card_type >= NV_50) {
40 		const int ib_size = pushbuf->bo.mem.size / 2;
41 
42 		chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
43 		chan->dma.ib_max = (ib_size / 8) - 1;
44 		chan->dma.ib_put = 0;
45 		chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
46 
47 		chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
48 	} else {
49 		chan->dma.max  = (pushbuf->bo.mem.size >> 2) - 2;
50 	}
51 
52 	chan->dma.put  = 0;
53 	chan->dma.cur  = chan->dma.put;
54 	chan->dma.free = chan->dma.max - chan->dma.cur;
55 }
56 
57 int
58 nouveau_dma_init(struct nouveau_channel *chan)
59 {
60 	struct drm_device *dev = chan->dev;
61 	struct drm_nouveau_private *dev_priv = dev->dev_private;
62 	int ret, i;
63 
64 	if (dev_priv->card_type >= NV_C0) {
65 		ret = nouveau_gpuobj_gr_new(chan, 0x9039, 0x9039);
66 		if (ret)
67 			return ret;
68 
69 		ret = RING_SPACE(chan, 2);
70 		if (ret)
71 			return ret;
72 
73 		BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0000, 1);
74 		OUT_RING  (chan, 0x00009039);
75 		FIRE_RING (chan);
76 		return 0;
77 	}
78 
79 	/* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
80 	ret = nouveau_gpuobj_gr_new(chan, NvM2MF, dev_priv->card_type < NV_50 ?
81 				    0x0039 : 0x5039);
82 	if (ret)
83 		return ret;
84 
85 	/* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
86 	ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
87 	if (ret)
88 		return ret;
89 
90 	/* Insert NOPS for NOUVEAU_DMA_SKIPS */
91 	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
92 	if (ret)
93 		return ret;
94 
95 	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
96 		OUT_RING(chan, 0);
97 
98 	/* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
99 	ret = RING_SPACE(chan, 4);
100 	if (ret)
101 		return ret;
102 	BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
103 	OUT_RING(chan, NvM2MF);
104 	BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
105 	OUT_RING(chan, NvNotify0);
106 
107 	/* Sit back and pray the channel works.. */
108 	FIRE_RING(chan);
109 
110 	return 0;
111 }
112 
113 void
114 OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
115 {
116 	bool is_iomem;
117 	u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
118 	mem = &mem[chan->dma.cur];
119 	if (is_iomem)
120 		memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
121 	else
122 		memcpy(mem, data, nr_dwords * 4);
123 	chan->dma.cur += nr_dwords;
124 }
125 
126 /* Fetch and adjust GPU GET pointer
127  *
128  * Returns:
129  *  value >= 0, the adjusted GET pointer
130  *  -EINVAL if GET pointer currently outside main push buffer
131  *  -EBUSY if timeout exceeded
132  */
133 static inline int
134 READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
135 {
136 	uint32_t val;
137 
138 	val = nvchan_rd32(chan, chan->user_get);
139 
140 	/* reset counter as long as GET is still advancing, this is
141 	 * to avoid misdetecting a GPU lockup if the GPU happens to
142 	 * just be processing an operation that takes a long time
143 	 */
144 	if (val != *prev_get) {
145 		*prev_get = val;
146 		*timeout = 0;
147 	}
148 
149 	if ((++*timeout & 0xff) == 0) {
150 		DRM_UDELAY(1);
151 		if (*timeout > 100000)
152 			return -EBUSY;
153 	}
154 
155 	if (val < chan->pushbuf_base ||
156 	    val > chan->pushbuf_base + (chan->dma.max << 2))
157 		return -EINVAL;
158 
159 	return (val - chan->pushbuf_base) >> 2;
160 }
161 
162 void
163 nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
164 	      int delta, int length)
165 {
166 	struct nouveau_bo *pb = chan->pushbuf_bo;
167 	uint64_t offset = bo->bo.offset + delta;
168 	int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
169 
170 	BUG_ON(chan->dma.ib_free < 1);
171 	nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
172 	nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
173 
174 	chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
175 
176 	DRM_MEMORYBARRIER();
177 	/* Flush writes. */
178 	nouveau_bo_rd32(pb, 0);
179 
180 	nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
181 	chan->dma.ib_free--;
182 }
183 
184 static int
185 nv50_dma_push_wait(struct nouveau_channel *chan, int count)
186 {
187 	uint32_t cnt = 0, prev_get = 0;
188 
189 	while (chan->dma.ib_free < count) {
190 		uint32_t get = nvchan_rd32(chan, 0x88);
191 		if (get != prev_get) {
192 			prev_get = get;
193 			cnt = 0;
194 		}
195 
196 		if ((++cnt & 0xff) == 0) {
197 			DRM_UDELAY(1);
198 			if (cnt > 100000)
199 				return -EBUSY;
200 		}
201 
202 		chan->dma.ib_free = get - chan->dma.ib_put;
203 		if (chan->dma.ib_free <= 0)
204 			chan->dma.ib_free += chan->dma.ib_max;
205 	}
206 
207 	return 0;
208 }
209 
210 static int
211 nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
212 {
213 	uint32_t cnt = 0, prev_get = 0;
214 	int ret;
215 
216 	ret = nv50_dma_push_wait(chan, slots + 1);
217 	if (unlikely(ret))
218 		return ret;
219 
220 	while (chan->dma.free < count) {
221 		int get = READ_GET(chan, &prev_get, &cnt);
222 		if (unlikely(get < 0)) {
223 			if (get == -EINVAL)
224 				continue;
225 
226 			return get;
227 		}
228 
229 		if (get <= chan->dma.cur) {
230 			chan->dma.free = chan->dma.max - chan->dma.cur;
231 			if (chan->dma.free >= count)
232 				break;
233 
234 			FIRE_RING(chan);
235 			do {
236 				get = READ_GET(chan, &prev_get, &cnt);
237 				if (unlikely(get < 0)) {
238 					if (get == -EINVAL)
239 						continue;
240 					return get;
241 				}
242 			} while (get == 0);
243 			chan->dma.cur = 0;
244 			chan->dma.put = 0;
245 		}
246 
247 		chan->dma.free = get - chan->dma.cur - 1;
248 	}
249 
250 	return 0;
251 }
252 
253 int
254 nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
255 {
256 	uint32_t prev_get = 0, cnt = 0;
257 	int get;
258 
259 	if (chan->dma.ib_max)
260 		return nv50_dma_wait(chan, slots, size);
261 
262 	while (chan->dma.free < size) {
263 		get = READ_GET(chan, &prev_get, &cnt);
264 		if (unlikely(get == -EBUSY))
265 			return -EBUSY;
266 
267 		/* loop until we have a usable GET pointer.  the value
268 		 * we read from the GPU may be outside the main ring if
269 		 * PFIFO is processing a buffer called from the main ring,
270 		 * discard these values until something sensible is seen.
271 		 *
272 		 * the other case we discard GET is while the GPU is fetching
273 		 * from the SKIPS area, so the code below doesn't have to deal
274 		 * with some fun corner cases.
275 		 */
276 		if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
277 			continue;
278 
279 		if (get <= chan->dma.cur) {
280 			/* engine is fetching behind us, or is completely
281 			 * idle (GET == PUT) so we have free space up until
282 			 * the end of the push buffer
283 			 *
284 			 * we can only hit that path once per call due to
285 			 * looping back to the beginning of the push buffer,
286 			 * we'll hit the fetching-ahead-of-us path from that
287 			 * point on.
288 			 *
289 			 * the *one* exception to that rule is if we read
290 			 * GET==PUT, in which case the below conditional will
291 			 * always succeed and break us out of the wait loop.
292 			 */
293 			chan->dma.free = chan->dma.max - chan->dma.cur;
294 			if (chan->dma.free >= size)
295 				break;
296 
297 			/* not enough space left at the end of the push buffer,
298 			 * instruct the GPU to jump back to the start right
299 			 * after processing the currently pending commands.
300 			 */
301 			OUT_RING(chan, chan->pushbuf_base | 0x20000000);
302 
303 			/* wait for GET to depart from the skips area.
304 			 * prevents writing GET==PUT and causing a race
305 			 * condition that causes us to think the GPU is
306 			 * idle when it's not.
307 			 */
308 			do {
309 				get = READ_GET(chan, &prev_get, &cnt);
310 				if (unlikely(get == -EBUSY))
311 					return -EBUSY;
312 				if (unlikely(get == -EINVAL))
313 					continue;
314 			} while (get <= NOUVEAU_DMA_SKIPS);
315 			WRITE_PUT(NOUVEAU_DMA_SKIPS);
316 
317 			/* we're now submitting commands at the start of
318 			 * the push buffer.
319 			 */
320 			chan->dma.cur  =
321 			chan->dma.put  = NOUVEAU_DMA_SKIPS;
322 		}
323 
324 		/* engine fetching ahead of us, we have space up until the
325 		 * current GET pointer.  the "- 1" is to ensure there's
326 		 * space left to emit a jump back to the beginning of the
327 		 * push buffer if we require it.  we can never get GET == PUT
328 		 * here, so this is safe.
329 		 */
330 		chan->dma.free = get - chan->dma.cur - 1;
331 	}
332 
333 	return 0;
334 }
335 
336