1 /*
2  * Copyright (C) 2007 Ben Skeggs.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  */
26 
27 #include "nouveau_drv.h"
28 #include "nouveau_dma.h"
29 #include "nouveau_vmm.h"
30 
31 #include <nvif/user.h>
32 
33 /* Fetch and adjust GPU GET pointer
34  *
35  * Returns:
36  *  value >= 0, the adjusted GET pointer
37  *  -EINVAL if GET pointer currently outside main push buffer
38  *  -EBUSY if timeout exceeded
39  */
40 static inline int
41 READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout)
42 {
43 	uint64_t val;
44 
45 	val = nvif_rd32(chan->userd, chan->user_get);
46         if (chan->user_get_hi)
47 		val |= (uint64_t)nvif_rd32(chan->userd, chan->user_get_hi) << 32;
48 
49 	/* reset counter as long as GET is still advancing, this is
50 	 * to avoid misdetecting a GPU lockup if the GPU happens to
51 	 * just be processing an operation that takes a long time
52 	 */
53 	if (val != *prev_get) {
54 		*prev_get = val;
55 		*timeout = 0;
56 	}
57 
58 	if ((++*timeout & 0xff) == 0) {
59 		udelay(1);
60 		if (*timeout > 100000)
61 			return -EBUSY;
62 	}
63 
64 	if (val < chan->push.addr ||
65 	    val > chan->push.addr + (chan->dma.max << 2))
66 		return -EINVAL;
67 
68 	return (val - chan->push.addr) >> 2;
69 }
70 
71 void
72 nv50_dma_push(struct nouveau_channel *chan, u64 offset, int length)
73 {
74 	struct nvif_user *user = &chan->drm->client.device.user;
75 	struct nouveau_bo *pb = chan->push.buffer;
76 	int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
77 
78 	BUG_ON(chan->dma.ib_free < 1);
79 
80 	nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
81 	nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
82 
83 	chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
84 
85 	mb();
86 	/* Flush writes. */
87 	nouveau_bo_rd32(pb, 0);
88 
89 	nvif_wr32(chan->userd, 0x8c, chan->dma.ib_put);
90 	if (user->func && user->func->doorbell)
91 		user->func->doorbell(user, chan->token);
92 	chan->dma.ib_free--;
93 }
94 
95 static int
96 nv50_dma_push_wait(struct nouveau_channel *chan, int count)
97 {
98 	uint32_t cnt = 0, prev_get = 0;
99 
100 	while (chan->dma.ib_free < count) {
101 		uint32_t get = nvif_rd32(chan->userd, 0x88);
102 		if (get != prev_get) {
103 			prev_get = get;
104 			cnt = 0;
105 		}
106 
107 		if ((++cnt & 0xff) == 0) {
108 			udelay(1);
109 			if (cnt > 100000)
110 				return -EBUSY;
111 		}
112 
113 		chan->dma.ib_free = get - chan->dma.ib_put;
114 		if (chan->dma.ib_free <= 0)
115 			chan->dma.ib_free += chan->dma.ib_max;
116 	}
117 
118 	return 0;
119 }
120 
121 static int
122 nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
123 {
124 	uint64_t prev_get = 0;
125 	int ret, cnt = 0;
126 
127 	ret = nv50_dma_push_wait(chan, slots + 1);
128 	if (unlikely(ret))
129 		return ret;
130 
131 	while (chan->dma.free < count) {
132 		int get = READ_GET(chan, &prev_get, &cnt);
133 		if (unlikely(get < 0)) {
134 			if (get == -EINVAL)
135 				continue;
136 
137 			return get;
138 		}
139 
140 		if (get <= chan->dma.cur) {
141 			chan->dma.free = chan->dma.max - chan->dma.cur;
142 			if (chan->dma.free >= count)
143 				break;
144 
145 			FIRE_RING(chan);
146 			do {
147 				get = READ_GET(chan, &prev_get, &cnt);
148 				if (unlikely(get < 0)) {
149 					if (get == -EINVAL)
150 						continue;
151 					return get;
152 				}
153 			} while (get == 0);
154 			chan->dma.cur = 0;
155 			chan->dma.put = 0;
156 		}
157 
158 		chan->dma.free = get - chan->dma.cur - 1;
159 	}
160 
161 	return 0;
162 }
163 
164 int
165 nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
166 {
167 	uint64_t prev_get = 0;
168 	int cnt = 0, get;
169 
170 	if (chan->dma.ib_max)
171 		return nv50_dma_wait(chan, slots, size);
172 
173 	while (chan->dma.free < size) {
174 		get = READ_GET(chan, &prev_get, &cnt);
175 		if (unlikely(get == -EBUSY))
176 			return -EBUSY;
177 
178 		/* loop until we have a usable GET pointer.  the value
179 		 * we read from the GPU may be outside the main ring if
180 		 * PFIFO is processing a buffer called from the main ring,
181 		 * discard these values until something sensible is seen.
182 		 *
183 		 * the other case we discard GET is while the GPU is fetching
184 		 * from the SKIPS area, so the code below doesn't have to deal
185 		 * with some fun corner cases.
186 		 */
187 		if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
188 			continue;
189 
190 		if (get <= chan->dma.cur) {
191 			/* engine is fetching behind us, or is completely
192 			 * idle (GET == PUT) so we have free space up until
193 			 * the end of the push buffer
194 			 *
195 			 * we can only hit that path once per call due to
196 			 * looping back to the beginning of the push buffer,
197 			 * we'll hit the fetching-ahead-of-us path from that
198 			 * point on.
199 			 *
200 			 * the *one* exception to that rule is if we read
201 			 * GET==PUT, in which case the below conditional will
202 			 * always succeed and break us out of the wait loop.
203 			 */
204 			chan->dma.free = chan->dma.max - chan->dma.cur;
205 			if (chan->dma.free >= size)
206 				break;
207 
208 			/* not enough space left at the end of the push buffer,
209 			 * instruct the GPU to jump back to the start right
210 			 * after processing the currently pending commands.
211 			 */
212 			OUT_RING(chan, chan->push.addr | 0x20000000);
213 
214 			/* wait for GET to depart from the skips area.
215 			 * prevents writing GET==PUT and causing a race
216 			 * condition that causes us to think the GPU is
217 			 * idle when it's not.
218 			 */
219 			do {
220 				get = READ_GET(chan, &prev_get, &cnt);
221 				if (unlikely(get == -EBUSY))
222 					return -EBUSY;
223 				if (unlikely(get == -EINVAL))
224 					continue;
225 			} while (get <= NOUVEAU_DMA_SKIPS);
226 			WRITE_PUT(NOUVEAU_DMA_SKIPS);
227 
228 			/* we're now submitting commands at the start of
229 			 * the push buffer.
230 			 */
231 			chan->dma.cur  =
232 			chan->dma.put  = NOUVEAU_DMA_SKIPS;
233 		}
234 
235 		/* engine fetching ahead of us, we have space up until the
236 		 * current GET pointer.  the "- 1" is to ensure there's
237 		 * space left to emit a jump back to the beginning of the
238 		 * push buffer if we require it.  we can never get GET == PUT
239 		 * here, so this is safe.
240 		 */
241 		chan->dma.free = get - chan->dma.cur - 1;
242 	}
243 
244 	return 0;
245 }
246 
247