1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <nvif/os.h> 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/cl006b.h> 29 #include <nvif/cl506f.h> 30 #include <nvif/cl906f.h> 31 #include <nvif/cla06f.h> 32 #include <nvif/ioctl.h> 33 34 /*XXX*/ 35 #include <core/client.h> 36 37 #include "nouveau_drv.h" 38 #include "nouveau_dma.h" 39 #include "nouveau_bo.h" 40 #include "nouveau_chan.h" 41 #include "nouveau_fence.h" 42 #include "nouveau_abi16.h" 43 #include "nouveau_vmm.h" 44 45 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 46 int nouveau_vram_pushbuf; 47 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 48 49 static int 50 nouveau_channel_killed(struct nvif_notify *ntfy) 51 { 52 struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill); 53 struct nouveau_cli *cli = (void *)chan->user.client; 54 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); 55 atomic_set(&chan->killed, 1); 56 return NVIF_NOTIFY_DROP; 57 } 58 59 int 60 nouveau_channel_idle(struct nouveau_channel *chan) 61 { 62 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { 63 struct nouveau_cli *cli = (void *)chan->user.client; 64 struct nouveau_fence *fence = NULL; 65 int ret; 66 67 ret = nouveau_fence_new(chan, false, &fence); 68 if (!ret) { 69 ret = nouveau_fence_wait(fence, false, false); 70 nouveau_fence_unref(&fence); 71 } 72 73 if (ret) { 74 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 75 chan->chid, nvxx_client(&cli->base)->name); 76 return ret; 77 } 78 } 79 return 0; 80 } 81 82 void 83 nouveau_channel_del(struct nouveau_channel **pchan) 84 { 85 struct nouveau_channel *chan = *pchan; 86 if (chan) { 87 struct nouveau_cli *cli = (void *)chan->user.client; 88 bool super; 89 90 if (cli) { 91 super = cli->base.super; 92 cli->base.super = true; 93 } 94 95 if (chan->fence) 96 nouveau_fence(chan->drm)->context_del(chan); 97 nvif_object_fini(&chan->nvsw); 98 nvif_object_fini(&chan->gart); 99 nvif_object_fini(&chan->vram); 100 nvif_notify_fini(&chan->kill); 101 nvif_object_fini(&chan->user); 102 nvif_object_fini(&chan->push.ctxdma); 103 nouveau_vma_del(&chan->push.vma); 104 nouveau_bo_unmap(chan->push.buffer); 105 if (chan->push.buffer && chan->push.buffer->pin_refcnt) 106 nouveau_bo_unpin(chan->push.buffer); 107 nouveau_bo_ref(NULL, &chan->push.buffer); 108 kfree(chan); 109 110 if (cli) 111 cli->base.super = super; 112 } 113 *pchan = NULL; 114 } 115 116 static int 117 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 118 u32 size, struct nouveau_channel **pchan) 119 { 120 struct nouveau_cli *cli = (void *)device->object.client; 121 struct nv_dma_v0 args = {}; 122 struct nouveau_channel *chan; 123 u32 target; 124 int ret; 125 126 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 127 if (!chan) 128 return -ENOMEM; 129 130 chan->device = device; 131 chan->drm = drm; 132 atomic_set(&chan->killed, 0); 133 134 /* allocate memory for dma push buffer */ 135 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 136 if (nouveau_vram_pushbuf) 137 target = TTM_PL_FLAG_VRAM; 138 139 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, 140 &chan->push.buffer); 141 if (ret == 0) { 142 ret = nouveau_bo_pin(chan->push.buffer, target, false); 143 if (ret == 0) 144 ret = nouveau_bo_map(chan->push.buffer); 145 } 146 147 if (ret) { 148 nouveau_channel_del(pchan); 149 return ret; 150 } 151 152 /* create dma object covering the *entire* memory space that the 153 * pushbuf lives in, this is because the GEM code requires that 154 * we be able to call out to other (indirect) push buffers 155 */ 156 chan->push.addr = chan->push.buffer->bo.offset; 157 158 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 159 ret = nouveau_vma_new(chan->push.buffer, &cli->vmm, 160 &chan->push.vma); 161 if (ret) { 162 nouveau_channel_del(pchan); 163 return ret; 164 } 165 166 args.target = NV_DMA_V0_TARGET_VM; 167 args.access = NV_DMA_V0_ACCESS_VM; 168 args.start = 0; 169 args.limit = cli->vmm.vmm.limit - 1; 170 171 chan->push.addr = chan->push.vma->addr; 172 } else 173 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 174 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 175 /* nv04 vram pushbuf hack, retarget to its location in 176 * the framebuffer bar rather than direct vram access.. 177 * nfi why this exists, it came from the -nv ddx. 178 */ 179 args.target = NV_DMA_V0_TARGET_PCI; 180 args.access = NV_DMA_V0_ACCESS_RDWR; 181 args.start = nvxx_device(device)->func-> 182 resource_addr(nvxx_device(device), 1); 183 args.limit = args.start + device->info.ram_user - 1; 184 } else { 185 args.target = NV_DMA_V0_TARGET_VRAM; 186 args.access = NV_DMA_V0_ACCESS_RDWR; 187 args.start = 0; 188 args.limit = device->info.ram_user - 1; 189 } 190 } else { 191 if (chan->drm->agp.bridge) { 192 args.target = NV_DMA_V0_TARGET_AGP; 193 args.access = NV_DMA_V0_ACCESS_RDWR; 194 args.start = chan->drm->agp.base; 195 args.limit = chan->drm->agp.base + 196 chan->drm->agp.size - 1; 197 } else { 198 args.target = NV_DMA_V0_TARGET_VM; 199 args.access = NV_DMA_V0_ACCESS_RDWR; 200 args.start = 0; 201 args.limit = cli->vmm.vmm.limit - 1; 202 } 203 } 204 205 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, 206 &args, sizeof(args), &chan->push.ctxdma); 207 if (ret) { 208 nouveau_channel_del(pchan); 209 return ret; 210 } 211 212 return 0; 213 } 214 215 static int 216 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, 217 u32 engine, struct nouveau_channel **pchan) 218 { 219 struct nouveau_cli *cli = (void *)device->object.client; 220 static const u16 oclasses[] = { PASCAL_CHANNEL_GPFIFO_A, 221 MAXWELL_CHANNEL_GPFIFO_A, 222 KEPLER_CHANNEL_GPFIFO_B, 223 KEPLER_CHANNEL_GPFIFO_A, 224 FERMI_CHANNEL_GPFIFO, 225 G82_CHANNEL_GPFIFO, 226 NV50_CHANNEL_GPFIFO, 227 0 }; 228 const u16 *oclass = oclasses; 229 union { 230 struct nv50_channel_gpfifo_v0 nv50; 231 struct fermi_channel_gpfifo_v0 fermi; 232 struct kepler_channel_gpfifo_a_v0 kepler; 233 } args; 234 struct nouveau_channel *chan; 235 u32 size; 236 int ret; 237 238 /* allocate dma push buffer */ 239 ret = nouveau_channel_prep(drm, device, 0x12000, &chan); 240 *pchan = chan; 241 if (ret) 242 return ret; 243 244 /* create channel object */ 245 do { 246 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { 247 args.kepler.version = 0; 248 args.kepler.engines = engine; 249 args.kepler.ilength = 0x02000; 250 args.kepler.ioffset = 0x10000 + chan->push.addr; 251 args.kepler.vmm = nvif_handle(&cli->vmm.vmm.object); 252 size = sizeof(args.kepler); 253 } else 254 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { 255 args.fermi.version = 0; 256 args.fermi.ilength = 0x02000; 257 args.fermi.ioffset = 0x10000 + chan->push.addr; 258 args.fermi.vmm = nvif_handle(&cli->vmm.vmm.object); 259 size = sizeof(args.fermi); 260 } else { 261 args.nv50.version = 0; 262 args.nv50.ilength = 0x02000; 263 args.nv50.ioffset = 0x10000 + chan->push.addr; 264 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); 265 args.nv50.vmm = nvif_handle(&cli->vmm.vmm.object); 266 size = sizeof(args.nv50); 267 } 268 269 ret = nvif_object_init(&device->object, 0, *oclass++, 270 &args, size, &chan->user); 271 if (ret == 0) { 272 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) 273 chan->chid = args.kepler.chid; 274 else 275 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) 276 chan->chid = args.fermi.chid; 277 else 278 chan->chid = args.nv50.chid; 279 return ret; 280 } 281 } while (*oclass); 282 283 nouveau_channel_del(pchan); 284 return ret; 285 } 286 287 static int 288 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, 289 struct nouveau_channel **pchan) 290 { 291 static const u16 oclasses[] = { NV40_CHANNEL_DMA, 292 NV17_CHANNEL_DMA, 293 NV10_CHANNEL_DMA, 294 NV03_CHANNEL_DMA, 295 0 }; 296 const u16 *oclass = oclasses; 297 struct nv03_channel_dma_v0 args; 298 struct nouveau_channel *chan; 299 int ret; 300 301 /* allocate dma push buffer */ 302 ret = nouveau_channel_prep(drm, device, 0x10000, &chan); 303 *pchan = chan; 304 if (ret) 305 return ret; 306 307 /* create channel object */ 308 args.version = 0; 309 args.pushbuf = nvif_handle(&chan->push.ctxdma); 310 args.offset = chan->push.addr; 311 312 do { 313 ret = nvif_object_init(&device->object, 0, *oclass++, 314 &args, sizeof(args), &chan->user); 315 if (ret == 0) { 316 chan->chid = args.chid; 317 return ret; 318 } 319 } while (ret && *oclass); 320 321 nouveau_channel_del(pchan); 322 return ret; 323 } 324 325 static int 326 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 327 { 328 struct nvif_device *device = chan->device; 329 struct nouveau_cli *cli = (void *)chan->user.client; 330 struct nouveau_drm *drm = chan->drm; 331 struct nv_dma_v0 args = {}; 332 int ret, i; 333 334 nvif_object_map(&chan->user, NULL, 0); 335 336 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 337 ret = nvif_notify_init(&chan->user, nouveau_channel_killed, 338 true, NV906F_V0_NTFY_KILLED, 339 NULL, 0, 0, &chan->kill); 340 if (ret == 0) 341 ret = nvif_notify_get(&chan->kill); 342 if (ret) { 343 NV_ERROR(drm, "Failed to request channel kill " 344 "notification: %d\n", ret); 345 return ret; 346 } 347 } 348 349 /* allocate dma objects to cover all allowed vram, and gart */ 350 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 351 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 352 args.target = NV_DMA_V0_TARGET_VM; 353 args.access = NV_DMA_V0_ACCESS_VM; 354 args.start = 0; 355 args.limit = cli->vmm.vmm.limit - 1; 356 } else { 357 args.target = NV_DMA_V0_TARGET_VRAM; 358 args.access = NV_DMA_V0_ACCESS_RDWR; 359 args.start = 0; 360 args.limit = device->info.ram_user - 1; 361 } 362 363 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, 364 &args, sizeof(args), &chan->vram); 365 if (ret) 366 return ret; 367 368 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 369 args.target = NV_DMA_V0_TARGET_VM; 370 args.access = NV_DMA_V0_ACCESS_VM; 371 args.start = 0; 372 args.limit = cli->vmm.vmm.limit - 1; 373 } else 374 if (chan->drm->agp.bridge) { 375 args.target = NV_DMA_V0_TARGET_AGP; 376 args.access = NV_DMA_V0_ACCESS_RDWR; 377 args.start = chan->drm->agp.base; 378 args.limit = chan->drm->agp.base + 379 chan->drm->agp.size - 1; 380 } else { 381 args.target = NV_DMA_V0_TARGET_VM; 382 args.access = NV_DMA_V0_ACCESS_RDWR; 383 args.start = 0; 384 args.limit = cli->vmm.vmm.limit - 1; 385 } 386 387 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, 388 &args, sizeof(args), &chan->gart); 389 if (ret) 390 return ret; 391 } 392 393 /* initialise dma tracking parameters */ 394 switch (chan->user.oclass & 0x00ff) { 395 case 0x006b: 396 case 0x006e: 397 chan->user_put = 0x40; 398 chan->user_get = 0x44; 399 chan->dma.max = (0x10000 / 4) - 2; 400 break; 401 default: 402 chan->user_put = 0x40; 403 chan->user_get = 0x44; 404 chan->user_get_hi = 0x60; 405 chan->dma.ib_base = 0x10000 / 4; 406 chan->dma.ib_max = (0x02000 / 8) - 1; 407 chan->dma.ib_put = 0; 408 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 409 chan->dma.max = chan->dma.ib_base; 410 break; 411 } 412 413 chan->dma.put = 0; 414 chan->dma.cur = chan->dma.put; 415 chan->dma.free = chan->dma.max - chan->dma.cur; 416 417 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 418 if (ret) 419 return ret; 420 421 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 422 OUT_RING(chan, 0x00000000); 423 424 /* allocate software object class (used for fences on <= nv05) */ 425 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 426 ret = nvif_object_init(&chan->user, 0x006e, 427 NVIF_CLASS_SW_NV04, 428 NULL, 0, &chan->nvsw); 429 if (ret) 430 return ret; 431 432 ret = RING_SPACE(chan, 2); 433 if (ret) 434 return ret; 435 436 BEGIN_NV04(chan, NvSubSw, 0x0000, 1); 437 OUT_RING (chan, chan->nvsw.handle); 438 FIRE_RING (chan); 439 } 440 441 /* initialise synchronisation */ 442 return nouveau_fence(chan->drm)->context_new(chan); 443 } 444 445 int 446 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 447 u32 arg0, u32 arg1, struct nouveau_channel **pchan) 448 { 449 struct nouveau_cli *cli = (void *)device->object.client; 450 bool super; 451 int ret; 452 453 /* hack until fencenv50 is fixed, and agp access relaxed */ 454 super = cli->base.super; 455 cli->base.super = true; 456 457 ret = nouveau_channel_ind(drm, device, arg0, pchan); 458 if (ret) { 459 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); 460 ret = nouveau_channel_dma(drm, device, pchan); 461 if (ret) { 462 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); 463 goto done; 464 } 465 } 466 467 ret = nouveau_channel_init(*pchan, arg0, arg1); 468 if (ret) { 469 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 470 nouveau_channel_del(pchan); 471 } 472 473 done: 474 cli->base.super = super; 475 return ret; 476 } 477