1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <nvif/push006c.h> 25 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/if0020.h> 29 30 #include "nouveau_drv.h" 31 #include "nouveau_dma.h" 32 #include "nouveau_bo.h" 33 #include "nouveau_chan.h" 34 #include "nouveau_fence.h" 35 #include "nouveau_abi16.h" 36 #include "nouveau_vmm.h" 37 #include "nouveau_svm.h" 38 39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 40 int nouveau_vram_pushbuf; 41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 42 43 void 44 nouveau_channel_kill(struct nouveau_channel *chan) 45 { 46 atomic_set(&chan->killed, 1); 47 if (chan->fence) 48 nouveau_fence_context_kill(chan->fence, -ENODEV); 49 } 50 51 static int 52 nouveau_channel_killed(struct nvif_event *event, void *repv, u32 repc) 53 { 54 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill); 55 struct nouveau_cli *cli = (void *)chan->user.client; 56 57 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); 58 59 if (unlikely(!atomic_read(&chan->killed))) 60 nouveau_channel_kill(chan); 61 62 return NVIF_EVENT_DROP; 63 } 64 65 int 66 nouveau_channel_idle(struct nouveau_channel *chan) 67 { 68 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { 69 struct nouveau_cli *cli = (void *)chan->user.client; 70 struct nouveau_fence *fence = NULL; 71 int ret; 72 73 ret = nouveau_fence_new(&fence); 74 if (!ret) { 75 ret = nouveau_fence_emit(fence, chan); 76 if (!ret) 77 ret = nouveau_fence_wait(fence, false, false); 78 nouveau_fence_unref(&fence); 79 } 80 81 if (ret) { 82 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 83 chan->chid, nvxx_client(&cli->base)->name); 84 return ret; 85 } 86 } 87 return 0; 88 } 89 90 void 91 nouveau_channel_del(struct nouveau_channel **pchan) 92 { 93 struct nouveau_channel *chan = *pchan; 94 if (chan) { 95 struct nouveau_cli *cli = (void *)chan->user.client; 96 97 if (chan->fence) 98 nouveau_fence(chan->drm)->context_del(chan); 99 100 if (cli) 101 nouveau_svmm_part(chan->vmm->svmm, chan->inst); 102 103 nvif_object_dtor(&chan->blit); 104 nvif_object_dtor(&chan->nvsw); 105 nvif_object_dtor(&chan->gart); 106 nvif_object_dtor(&chan->vram); 107 nvif_event_dtor(&chan->kill); 108 nvif_object_dtor(&chan->user); 109 nvif_mem_dtor(&chan->mem_userd); 110 nvif_object_dtor(&chan->push.ctxdma); 111 nouveau_vma_del(&chan->push.vma); 112 nouveau_bo_unmap(chan->push.buffer); 113 if (chan->push.buffer && chan->push.buffer->bo.pin_count) 114 nouveau_bo_unpin(chan->push.buffer); 115 nouveau_bo_ref(NULL, &chan->push.buffer); 116 kfree(chan); 117 } 118 *pchan = NULL; 119 } 120 121 static void 122 nouveau_channel_kick(struct nvif_push *push) 123 { 124 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push); 125 chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn); 126 FIRE_RING(chan); 127 chan->chan._push.bgn = chan->chan._push.cur; 128 } 129 130 static int 131 nouveau_channel_wait(struct nvif_push *push, u32 size) 132 { 133 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push); 134 int ret; 135 chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn); 136 ret = RING_SPACE(chan, size); 137 if (ret == 0) { 138 chan->chan._push.bgn = chan->chan._push.mem.object.map.ptr; 139 chan->chan._push.bgn = chan->chan._push.bgn + chan->dma.cur; 140 chan->chan._push.cur = chan->chan._push.bgn; 141 chan->chan._push.end = chan->chan._push.bgn + size; 142 } 143 return ret; 144 } 145 146 static int 147 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 148 u32 size, struct nouveau_channel **pchan) 149 { 150 struct nouveau_cli *cli = (void *)device->object.client; 151 struct nv_dma_v0 args = {}; 152 struct nouveau_channel *chan; 153 u32 target; 154 int ret; 155 156 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 157 if (!chan) 158 return -ENOMEM; 159 160 chan->device = device; 161 chan->drm = drm; 162 chan->vmm = nouveau_cli_vmm(cli); 163 atomic_set(&chan->killed, 0); 164 165 /* allocate memory for dma push buffer */ 166 target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT; 167 if (nouveau_vram_pushbuf) 168 target = NOUVEAU_GEM_DOMAIN_VRAM; 169 170 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, 171 &chan->push.buffer); 172 if (ret == 0) { 173 ret = nouveau_bo_pin(chan->push.buffer, target, false); 174 if (ret == 0) 175 ret = nouveau_bo_map(chan->push.buffer); 176 } 177 178 if (ret) { 179 nouveau_channel_del(pchan); 180 return ret; 181 } 182 183 chan->chan._push.mem.object.parent = cli->base.object.parent; 184 chan->chan._push.mem.object.client = &cli->base; 185 chan->chan._push.mem.object.name = "chanPush"; 186 chan->chan._push.mem.object.map.ptr = chan->push.buffer->kmap.virtual; 187 chan->chan._push.wait = nouveau_channel_wait; 188 chan->chan._push.kick = nouveau_channel_kick; 189 chan->chan.push = &chan->chan._push; 190 191 /* create dma object covering the *entire* memory space that the 192 * pushbuf lives in, this is because the GEM code requires that 193 * we be able to call out to other (indirect) push buffers 194 */ 195 chan->push.addr = chan->push.buffer->offset; 196 197 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 198 ret = nouveau_vma_new(chan->push.buffer, chan->vmm, 199 &chan->push.vma); 200 if (ret) { 201 nouveau_channel_del(pchan); 202 return ret; 203 } 204 205 chan->push.addr = chan->push.vma->addr; 206 207 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI) 208 return 0; 209 210 args.target = NV_DMA_V0_TARGET_VM; 211 args.access = NV_DMA_V0_ACCESS_VM; 212 args.start = 0; 213 args.limit = chan->vmm->vmm.limit - 1; 214 } else 215 if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) { 216 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 217 /* nv04 vram pushbuf hack, retarget to its location in 218 * the framebuffer bar rather than direct vram access.. 219 * nfi why this exists, it came from the -nv ddx. 220 */ 221 args.target = NV_DMA_V0_TARGET_PCI; 222 args.access = NV_DMA_V0_ACCESS_RDWR; 223 args.start = nvxx_device(device)->func-> 224 resource_addr(nvxx_device(device), 1); 225 args.limit = args.start + device->info.ram_user - 1; 226 } else { 227 args.target = NV_DMA_V0_TARGET_VRAM; 228 args.access = NV_DMA_V0_ACCESS_RDWR; 229 args.start = 0; 230 args.limit = device->info.ram_user - 1; 231 } 232 } else { 233 if (chan->drm->agp.bridge) { 234 args.target = NV_DMA_V0_TARGET_AGP; 235 args.access = NV_DMA_V0_ACCESS_RDWR; 236 args.start = chan->drm->agp.base; 237 args.limit = chan->drm->agp.base + 238 chan->drm->agp.size - 1; 239 } else { 240 args.target = NV_DMA_V0_TARGET_VM; 241 args.access = NV_DMA_V0_ACCESS_RDWR; 242 args.start = 0; 243 args.limit = chan->vmm->vmm.limit - 1; 244 } 245 } 246 247 ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0, 248 NV_DMA_FROM_MEMORY, &args, sizeof(args), 249 &chan->push.ctxdma); 250 if (ret) { 251 nouveau_channel_del(pchan); 252 return ret; 253 } 254 255 return 0; 256 } 257 258 static int 259 nouveau_channel_ctor(struct nouveau_drm *drm, struct nvif_device *device, bool priv, u64 runm, 260 struct nouveau_channel **pchan) 261 { 262 static const struct { 263 s32 oclass; 264 int version; 265 } hosts[] = { 266 { AMPERE_CHANNEL_GPFIFO_B, 0 }, 267 { AMPERE_CHANNEL_GPFIFO_A, 0 }, 268 { TURING_CHANNEL_GPFIFO_A, 0 }, 269 { VOLTA_CHANNEL_GPFIFO_A, 0 }, 270 { PASCAL_CHANNEL_GPFIFO_A, 0 }, 271 { MAXWELL_CHANNEL_GPFIFO_A, 0 }, 272 { KEPLER_CHANNEL_GPFIFO_B, 0 }, 273 { KEPLER_CHANNEL_GPFIFO_A, 0 }, 274 { FERMI_CHANNEL_GPFIFO , 0 }, 275 { G82_CHANNEL_GPFIFO , 0 }, 276 { NV50_CHANNEL_GPFIFO , 0 }, 277 { NV40_CHANNEL_DMA , 0 }, 278 { NV17_CHANNEL_DMA , 0 }, 279 { NV10_CHANNEL_DMA , 0 }, 280 { NV03_CHANNEL_DMA , 0 }, 281 {} 282 }; 283 struct { 284 struct nvif_chan_v0 chan; 285 char name[TASK_COMM_LEN+16]; 286 } args; 287 struct nouveau_cli *cli = (void *)device->object.client; 288 struct nouveau_channel *chan; 289 const u64 plength = 0x10000; 290 const u64 ioffset = plength; 291 const u64 ilength = 0x02000; 292 char name[TASK_COMM_LEN]; 293 int cid, ret; 294 u64 size; 295 296 cid = nvif_mclass(&device->object, hosts); 297 if (cid < 0) 298 return cid; 299 300 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) 301 size = plength; 302 else 303 size = ioffset + ilength; 304 305 /* allocate dma push buffer */ 306 ret = nouveau_channel_prep(drm, device, size, &chan); 307 *pchan = chan; 308 if (ret) 309 return ret; 310 311 /* create channel object */ 312 args.chan.version = 0; 313 args.chan.namelen = sizeof(args.name); 314 args.chan.runlist = __ffs64(runm); 315 args.chan.runq = 0; 316 args.chan.priv = priv; 317 args.chan.devm = BIT(0); 318 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) { 319 args.chan.vmm = 0; 320 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma); 321 args.chan.offset = chan->push.addr; 322 args.chan.length = 0; 323 } else { 324 args.chan.vmm = nvif_handle(&chan->vmm->vmm.object); 325 if (hosts[cid].oclass < FERMI_CHANNEL_GPFIFO) 326 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma); 327 else 328 args.chan.ctxdma = 0; 329 args.chan.offset = ioffset + chan->push.addr; 330 args.chan.length = ilength; 331 } 332 args.chan.huserd = 0; 333 args.chan.ouserd = 0; 334 335 /* allocate userd */ 336 if (hosts[cid].oclass >= VOLTA_CHANNEL_GPFIFO_A) { 337 ret = nvif_mem_ctor(&cli->mmu, "abi16ChanUSERD", NVIF_CLASS_MEM_GF100, 338 NVIF_MEM_VRAM | NVIF_MEM_COHERENT | NVIF_MEM_MAPPABLE, 339 0, PAGE_SIZE, NULL, 0, &chan->mem_userd); 340 if (ret) 341 return ret; 342 343 args.chan.huserd = nvif_handle(&chan->mem_userd.object); 344 args.chan.ouserd = 0; 345 346 chan->userd = &chan->mem_userd.object; 347 } else { 348 chan->userd = &chan->user; 349 } 350 351 get_task_comm(name, current); 352 snprintf(args.name, sizeof(args.name), "%s[%d]", name, task_pid_nr(current)); 353 354 ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, hosts[cid].oclass, 355 &args, sizeof(args), &chan->user); 356 if (ret) { 357 nouveau_channel_del(pchan); 358 return ret; 359 } 360 361 chan->runlist = args.chan.runlist; 362 chan->chid = args.chan.chid; 363 chan->inst = args.chan.inst; 364 chan->token = args.chan.token; 365 return 0; 366 } 367 368 static int 369 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 370 { 371 struct nvif_device *device = chan->device; 372 struct nouveau_drm *drm = chan->drm; 373 struct nv_dma_v0 args = {}; 374 int ret, i; 375 376 ret = nvif_object_map(chan->userd, NULL, 0); 377 if (ret) 378 return ret; 379 380 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 381 struct { 382 struct nvif_event_v0 base; 383 struct nvif_chan_event_v0 host; 384 } args; 385 386 args.host.version = 0; 387 args.host.type = NVIF_CHAN_EVENT_V0_KILLED; 388 389 ret = nvif_event_ctor(&chan->user, "abi16ChanKilled", chan->chid, 390 nouveau_channel_killed, false, 391 &args.base, sizeof(args), &chan->kill); 392 if (ret == 0) 393 ret = nvif_event_allow(&chan->kill); 394 if (ret) { 395 NV_ERROR(drm, "Failed to request channel kill " 396 "notification: %d\n", ret); 397 return ret; 398 } 399 } 400 401 /* allocate dma objects to cover all allowed vram, and gart */ 402 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 403 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 404 args.target = NV_DMA_V0_TARGET_VM; 405 args.access = NV_DMA_V0_ACCESS_VM; 406 args.start = 0; 407 args.limit = chan->vmm->vmm.limit - 1; 408 } else { 409 args.target = NV_DMA_V0_TARGET_VRAM; 410 args.access = NV_DMA_V0_ACCESS_RDWR; 411 args.start = 0; 412 args.limit = device->info.ram_user - 1; 413 } 414 415 ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram, 416 NV_DMA_IN_MEMORY, &args, sizeof(args), 417 &chan->vram); 418 if (ret) 419 return ret; 420 421 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 422 args.target = NV_DMA_V0_TARGET_VM; 423 args.access = NV_DMA_V0_ACCESS_VM; 424 args.start = 0; 425 args.limit = chan->vmm->vmm.limit - 1; 426 } else 427 if (chan->drm->agp.bridge) { 428 args.target = NV_DMA_V0_TARGET_AGP; 429 args.access = NV_DMA_V0_ACCESS_RDWR; 430 args.start = chan->drm->agp.base; 431 args.limit = chan->drm->agp.base + 432 chan->drm->agp.size - 1; 433 } else { 434 args.target = NV_DMA_V0_TARGET_VM; 435 args.access = NV_DMA_V0_ACCESS_RDWR; 436 args.start = 0; 437 args.limit = chan->vmm->vmm.limit - 1; 438 } 439 440 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart, 441 NV_DMA_IN_MEMORY, &args, sizeof(args), 442 &chan->gart); 443 if (ret) 444 return ret; 445 } 446 447 /* initialise dma tracking parameters */ 448 switch (chan->user.oclass & 0x00ff) { 449 case 0x006b: 450 case 0x006e: 451 chan->user_put = 0x40; 452 chan->user_get = 0x44; 453 chan->dma.max = (0x10000 / 4) - 2; 454 break; 455 default: 456 chan->user_put = 0x40; 457 chan->user_get = 0x44; 458 chan->user_get_hi = 0x60; 459 chan->dma.ib_base = 0x10000 / 4; 460 chan->dma.ib_max = (0x02000 / 8) - 1; 461 chan->dma.ib_put = 0; 462 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 463 chan->dma.max = chan->dma.ib_base; 464 break; 465 } 466 467 chan->dma.put = 0; 468 chan->dma.cur = chan->dma.put; 469 chan->dma.free = chan->dma.max - chan->dma.cur; 470 471 ret = PUSH_WAIT(chan->chan.push, NOUVEAU_DMA_SKIPS); 472 if (ret) 473 return ret; 474 475 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 476 PUSH_DATA(chan->chan.push, 0x00000000); 477 478 /* allocate software object class (used for fences on <= nv05) */ 479 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 480 ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e, 481 NVIF_CLASS_SW_NV04, 482 NULL, 0, &chan->nvsw); 483 if (ret) 484 return ret; 485 486 ret = PUSH_WAIT(chan->chan.push, 2); 487 if (ret) 488 return ret; 489 490 PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle); 491 PUSH_KICK(chan->chan.push); 492 } 493 494 /* initialise synchronisation */ 495 return nouveau_fence(chan->drm)->context_new(chan); 496 } 497 498 int 499 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 500 bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan) 501 { 502 struct nouveau_cli *cli = (void *)device->object.client; 503 int ret; 504 505 ret = nouveau_channel_ctor(drm, device, priv, runm, pchan); 506 if (ret) { 507 NV_PRINTK(dbg, cli, "channel create, %d\n", ret); 508 return ret; 509 } 510 511 ret = nouveau_channel_init(*pchan, vram, gart); 512 if (ret) { 513 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 514 nouveau_channel_del(pchan); 515 return ret; 516 } 517 518 ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst); 519 if (ret) 520 nouveau_channel_del(pchan); 521 522 return ret; 523 } 524 525 void 526 nouveau_channels_fini(struct nouveau_drm *drm) 527 { 528 kfree(drm->runl); 529 } 530 531 int 532 nouveau_channels_init(struct nouveau_drm *drm) 533 { 534 struct { 535 struct nv_device_info_v1 m; 536 struct { 537 struct nv_device_info_v1_data channels; 538 struct nv_device_info_v1_data runlists; 539 } v; 540 } args = { 541 .m.version = 1, 542 .m.count = sizeof(args.v) / sizeof(args.v.channels), 543 .v.channels.mthd = NV_DEVICE_HOST_CHANNELS, 544 .v.runlists.mthd = NV_DEVICE_HOST_RUNLISTS, 545 }; 546 struct nvif_object *device = &drm->client.device.object; 547 int ret, i; 548 549 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); 550 if (ret || 551 args.v.runlists.mthd == NV_DEVICE_INFO_INVALID || !args.v.runlists.data || 552 args.v.channels.mthd == NV_DEVICE_INFO_INVALID) 553 return -ENODEV; 554 555 drm->chan_nr = drm->chan_total = args.v.channels.data; 556 drm->runl_nr = fls64(args.v.runlists.data); 557 drm->runl = kcalloc(drm->runl_nr, sizeof(*drm->runl), GFP_KERNEL); 558 if (!drm->runl) 559 return -ENOMEM; 560 561 if (drm->chan_nr == 0) { 562 for (i = 0; i < drm->runl_nr; i++) { 563 if (!(args.v.runlists.data & BIT(i))) 564 continue; 565 566 args.v.channels.mthd = NV_DEVICE_HOST_RUNLIST_CHANNELS; 567 args.v.channels.data = i; 568 569 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); 570 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID) 571 return -ENODEV; 572 573 drm->runl[i].chan_nr = args.v.channels.data; 574 drm->runl[i].chan_id_base = drm->chan_total; 575 drm->runl[i].context_base = dma_fence_context_alloc(drm->runl[i].chan_nr); 576 577 drm->chan_total += drm->runl[i].chan_nr; 578 } 579 } else { 580 drm->runl[0].context_base = dma_fence_context_alloc(drm->chan_nr); 581 for (i = 1; i < drm->runl_nr; i++) 582 drm->runl[i].context_base = drm->runl[0].context_base; 583 584 } 585 586 return 0; 587 } 588