1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <nvif/os.h> 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/cl006b.h> 29 #include <nvif/cl506f.h> 30 #include <nvif/cl906f.h> 31 #include <nvif/cla06f.h> 32 #include <nvif/ioctl.h> 33 34 /*XXX*/ 35 #include <core/client.h> 36 37 #include "nouveau_drv.h" 38 #include "nouveau_dma.h" 39 #include "nouveau_bo.h" 40 #include "nouveau_chan.h" 41 #include "nouveau_fence.h" 42 #include "nouveau_abi16.h" 43 #include "nouveau_vmm.h" 44 45 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 46 int nouveau_vram_pushbuf; 47 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 48 49 static int 50 nouveau_channel_killed(struct nvif_notify *ntfy) 51 { 52 struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill); 53 struct nouveau_cli *cli = (void *)chan->user.client; 54 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); 55 atomic_set(&chan->killed, 1); 56 return NVIF_NOTIFY_DROP; 57 } 58 59 int 60 nouveau_channel_idle(struct nouveau_channel *chan) 61 { 62 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { 63 struct nouveau_cli *cli = (void *)chan->user.client; 64 struct nouveau_fence *fence = NULL; 65 int ret; 66 67 ret = nouveau_fence_new(chan, false, &fence); 68 if (!ret) { 69 ret = nouveau_fence_wait(fence, false, false); 70 nouveau_fence_unref(&fence); 71 } 72 73 if (ret) { 74 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 75 chan->chid, nvxx_client(&cli->base)->name); 76 return ret; 77 } 78 } 79 return 0; 80 } 81 82 void 83 nouveau_channel_del(struct nouveau_channel **pchan) 84 { 85 struct nouveau_channel *chan = *pchan; 86 if (chan) { 87 struct nouveau_cli *cli = (void *)chan->user.client; 88 bool super; 89 90 if (cli) { 91 super = cli->base.super; 92 cli->base.super = true; 93 } 94 95 if (chan->fence) 96 nouveau_fence(chan->drm)->context_del(chan); 97 nvif_object_fini(&chan->nvsw); 98 nvif_object_fini(&chan->gart); 99 nvif_object_fini(&chan->vram); 100 nvif_notify_fini(&chan->kill); 101 nvif_object_fini(&chan->user); 102 nvif_object_fini(&chan->push.ctxdma); 103 nouveau_vma_del(&chan->push.vma); 104 nouveau_bo_unmap(chan->push.buffer); 105 if (chan->push.buffer && chan->push.buffer->pin_refcnt) 106 nouveau_bo_unpin(chan->push.buffer); 107 nouveau_bo_ref(NULL, &chan->push.buffer); 108 kfree(chan); 109 110 if (cli) 111 cli->base.super = super; 112 } 113 *pchan = NULL; 114 } 115 116 static int 117 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 118 u32 size, struct nouveau_channel **pchan) 119 { 120 struct nouveau_cli *cli = (void *)device->object.client; 121 struct nv_dma_v0 args = {}; 122 struct nouveau_channel *chan; 123 u32 target; 124 int ret; 125 126 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 127 if (!chan) 128 return -ENOMEM; 129 130 chan->device = device; 131 chan->drm = drm; 132 atomic_set(&chan->killed, 0); 133 134 /* allocate memory for dma push buffer */ 135 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 136 if (nouveau_vram_pushbuf) 137 target = TTM_PL_FLAG_VRAM; 138 139 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, 140 &chan->push.buffer); 141 if (ret == 0) { 142 ret = nouveau_bo_pin(chan->push.buffer, target, false); 143 if (ret == 0) 144 ret = nouveau_bo_map(chan->push.buffer); 145 } 146 147 if (ret) { 148 nouveau_channel_del(pchan); 149 return ret; 150 } 151 152 /* create dma object covering the *entire* memory space that the 153 * pushbuf lives in, this is because the GEM code requires that 154 * we be able to call out to other (indirect) push buffers 155 */ 156 chan->push.addr = chan->push.buffer->bo.offset; 157 158 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 159 ret = nouveau_vma_new(chan->push.buffer, &cli->vmm, 160 &chan->push.vma); 161 if (ret) { 162 nouveau_channel_del(pchan); 163 return ret; 164 } 165 166 chan->push.addr = chan->push.vma->addr; 167 168 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI) 169 return 0; 170 171 args.target = NV_DMA_V0_TARGET_VM; 172 args.access = NV_DMA_V0_ACCESS_VM; 173 args.start = 0; 174 args.limit = cli->vmm.vmm.limit - 1; 175 } else 176 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 177 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 178 /* nv04 vram pushbuf hack, retarget to its location in 179 * the framebuffer bar rather than direct vram access.. 180 * nfi why this exists, it came from the -nv ddx. 181 */ 182 args.target = NV_DMA_V0_TARGET_PCI; 183 args.access = NV_DMA_V0_ACCESS_RDWR; 184 args.start = nvxx_device(device)->func-> 185 resource_addr(nvxx_device(device), 1); 186 args.limit = args.start + device->info.ram_user - 1; 187 } else { 188 args.target = NV_DMA_V0_TARGET_VRAM; 189 args.access = NV_DMA_V0_ACCESS_RDWR; 190 args.start = 0; 191 args.limit = device->info.ram_user - 1; 192 } 193 } else { 194 if (chan->drm->agp.bridge) { 195 args.target = NV_DMA_V0_TARGET_AGP; 196 args.access = NV_DMA_V0_ACCESS_RDWR; 197 args.start = chan->drm->agp.base; 198 args.limit = chan->drm->agp.base + 199 chan->drm->agp.size - 1; 200 } else { 201 args.target = NV_DMA_V0_TARGET_VM; 202 args.access = NV_DMA_V0_ACCESS_RDWR; 203 args.start = 0; 204 args.limit = cli->vmm.vmm.limit - 1; 205 } 206 } 207 208 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, 209 &args, sizeof(args), &chan->push.ctxdma); 210 if (ret) { 211 nouveau_channel_del(pchan); 212 return ret; 213 } 214 215 return 0; 216 } 217 218 static int 219 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, 220 u64 runlist, struct nouveau_channel **pchan) 221 { 222 struct nouveau_cli *cli = (void *)device->object.client; 223 static const u16 oclasses[] = { VOLTA_CHANNEL_GPFIFO_A, 224 PASCAL_CHANNEL_GPFIFO_A, 225 MAXWELL_CHANNEL_GPFIFO_A, 226 KEPLER_CHANNEL_GPFIFO_B, 227 KEPLER_CHANNEL_GPFIFO_A, 228 FERMI_CHANNEL_GPFIFO, 229 G82_CHANNEL_GPFIFO, 230 NV50_CHANNEL_GPFIFO, 231 0 }; 232 const u16 *oclass = oclasses; 233 union { 234 struct nv50_channel_gpfifo_v0 nv50; 235 struct fermi_channel_gpfifo_v0 fermi; 236 struct kepler_channel_gpfifo_a_v0 kepler; 237 } args; 238 struct nouveau_channel *chan; 239 u32 size; 240 int ret; 241 242 /* allocate dma push buffer */ 243 ret = nouveau_channel_prep(drm, device, 0x12000, &chan); 244 *pchan = chan; 245 if (ret) 246 return ret; 247 248 /* create channel object */ 249 do { 250 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { 251 args.kepler.version = 0; 252 args.kepler.ilength = 0x02000; 253 args.kepler.ioffset = 0x10000 + chan->push.addr; 254 args.kepler.runlist = runlist; 255 args.kepler.vmm = nvif_handle(&cli->vmm.vmm.object); 256 size = sizeof(args.kepler); 257 } else 258 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { 259 args.fermi.version = 0; 260 args.fermi.ilength = 0x02000; 261 args.fermi.ioffset = 0x10000 + chan->push.addr; 262 args.fermi.vmm = nvif_handle(&cli->vmm.vmm.object); 263 size = sizeof(args.fermi); 264 } else { 265 args.nv50.version = 0; 266 args.nv50.ilength = 0x02000; 267 args.nv50.ioffset = 0x10000 + chan->push.addr; 268 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); 269 args.nv50.vmm = nvif_handle(&cli->vmm.vmm.object); 270 size = sizeof(args.nv50); 271 } 272 273 ret = nvif_object_init(&device->object, 0, *oclass++, 274 &args, size, &chan->user); 275 if (ret == 0) { 276 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) 277 chan->chid = args.kepler.chid; 278 else 279 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) 280 chan->chid = args.fermi.chid; 281 else 282 chan->chid = args.nv50.chid; 283 return ret; 284 } 285 } while (*oclass); 286 287 nouveau_channel_del(pchan); 288 return ret; 289 } 290 291 static int 292 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, 293 struct nouveau_channel **pchan) 294 { 295 static const u16 oclasses[] = { NV40_CHANNEL_DMA, 296 NV17_CHANNEL_DMA, 297 NV10_CHANNEL_DMA, 298 NV03_CHANNEL_DMA, 299 0 }; 300 const u16 *oclass = oclasses; 301 struct nv03_channel_dma_v0 args; 302 struct nouveau_channel *chan; 303 int ret; 304 305 /* allocate dma push buffer */ 306 ret = nouveau_channel_prep(drm, device, 0x10000, &chan); 307 *pchan = chan; 308 if (ret) 309 return ret; 310 311 /* create channel object */ 312 args.version = 0; 313 args.pushbuf = nvif_handle(&chan->push.ctxdma); 314 args.offset = chan->push.addr; 315 316 do { 317 ret = nvif_object_init(&device->object, 0, *oclass++, 318 &args, sizeof(args), &chan->user); 319 if (ret == 0) { 320 chan->chid = args.chid; 321 return ret; 322 } 323 } while (ret && *oclass); 324 325 nouveau_channel_del(pchan); 326 return ret; 327 } 328 329 static int 330 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 331 { 332 struct nvif_device *device = chan->device; 333 struct nouveau_cli *cli = (void *)chan->user.client; 334 struct nouveau_drm *drm = chan->drm; 335 struct nv_dma_v0 args = {}; 336 int ret, i; 337 338 nvif_object_map(&chan->user, NULL, 0); 339 340 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 341 ret = nvif_notify_init(&chan->user, nouveau_channel_killed, 342 true, NV906F_V0_NTFY_KILLED, 343 NULL, 0, 0, &chan->kill); 344 if (ret == 0) 345 ret = nvif_notify_get(&chan->kill); 346 if (ret) { 347 NV_ERROR(drm, "Failed to request channel kill " 348 "notification: %d\n", ret); 349 return ret; 350 } 351 } 352 353 /* allocate dma objects to cover all allowed vram, and gart */ 354 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 355 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 356 args.target = NV_DMA_V0_TARGET_VM; 357 args.access = NV_DMA_V0_ACCESS_VM; 358 args.start = 0; 359 args.limit = cli->vmm.vmm.limit - 1; 360 } else { 361 args.target = NV_DMA_V0_TARGET_VRAM; 362 args.access = NV_DMA_V0_ACCESS_RDWR; 363 args.start = 0; 364 args.limit = device->info.ram_user - 1; 365 } 366 367 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, 368 &args, sizeof(args), &chan->vram); 369 if (ret) 370 return ret; 371 372 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 373 args.target = NV_DMA_V0_TARGET_VM; 374 args.access = NV_DMA_V0_ACCESS_VM; 375 args.start = 0; 376 args.limit = cli->vmm.vmm.limit - 1; 377 } else 378 if (chan->drm->agp.bridge) { 379 args.target = NV_DMA_V0_TARGET_AGP; 380 args.access = NV_DMA_V0_ACCESS_RDWR; 381 args.start = chan->drm->agp.base; 382 args.limit = chan->drm->agp.base + 383 chan->drm->agp.size - 1; 384 } else { 385 args.target = NV_DMA_V0_TARGET_VM; 386 args.access = NV_DMA_V0_ACCESS_RDWR; 387 args.start = 0; 388 args.limit = cli->vmm.vmm.limit - 1; 389 } 390 391 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, 392 &args, sizeof(args), &chan->gart); 393 if (ret) 394 return ret; 395 } 396 397 /* initialise dma tracking parameters */ 398 switch (chan->user.oclass & 0x00ff) { 399 case 0x006b: 400 case 0x006e: 401 chan->user_put = 0x40; 402 chan->user_get = 0x44; 403 chan->dma.max = (0x10000 / 4) - 2; 404 break; 405 default: 406 chan->user_put = 0x40; 407 chan->user_get = 0x44; 408 chan->user_get_hi = 0x60; 409 chan->dma.ib_base = 0x10000 / 4; 410 chan->dma.ib_max = (0x02000 / 8) - 1; 411 chan->dma.ib_put = 0; 412 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 413 chan->dma.max = chan->dma.ib_base; 414 break; 415 } 416 417 chan->dma.put = 0; 418 chan->dma.cur = chan->dma.put; 419 chan->dma.free = chan->dma.max - chan->dma.cur; 420 421 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 422 if (ret) 423 return ret; 424 425 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 426 OUT_RING(chan, 0x00000000); 427 428 /* allocate software object class (used for fences on <= nv05) */ 429 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 430 ret = nvif_object_init(&chan->user, 0x006e, 431 NVIF_CLASS_SW_NV04, 432 NULL, 0, &chan->nvsw); 433 if (ret) 434 return ret; 435 436 ret = RING_SPACE(chan, 2); 437 if (ret) 438 return ret; 439 440 BEGIN_NV04(chan, NvSubSw, 0x0000, 1); 441 OUT_RING (chan, chan->nvsw.handle); 442 FIRE_RING (chan); 443 } 444 445 /* initialise synchronisation */ 446 return nouveau_fence(chan->drm)->context_new(chan); 447 } 448 449 int 450 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 451 u32 arg0, u32 arg1, struct nouveau_channel **pchan) 452 { 453 struct nouveau_cli *cli = (void *)device->object.client; 454 bool super; 455 int ret; 456 457 /* hack until fencenv50 is fixed, and agp access relaxed */ 458 super = cli->base.super; 459 cli->base.super = true; 460 461 ret = nouveau_channel_ind(drm, device, arg0, pchan); 462 if (ret) { 463 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); 464 ret = nouveau_channel_dma(drm, device, pchan); 465 if (ret) { 466 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); 467 goto done; 468 } 469 } 470 471 ret = nouveau_channel_init(*pchan, arg0, arg1); 472 if (ret) { 473 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 474 nouveau_channel_del(pchan); 475 } 476 477 done: 478 cli->base.super = super; 479 return ret; 480 } 481 482 int 483 nouveau_channels_init(struct nouveau_drm *drm) 484 { 485 struct { 486 struct nv_device_info_v1 m; 487 struct { 488 struct nv_device_info_v1_data channels; 489 } v; 490 } args = { 491 .m.version = 1, 492 .m.count = sizeof(args.v) / sizeof(args.v.channels), 493 .v.channels.mthd = NV_DEVICE_FIFO_CHANNELS, 494 }; 495 struct nvif_object *device = &drm->client.device.object; 496 int ret; 497 498 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); 499 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID) 500 return -ENODEV; 501 502 drm->chan.nr = args.v.channels.data; 503 drm->chan.context_base = dma_fence_context_alloc(drm->chan.nr); 504 return 0; 505 } 506