1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <nvif/push006c.h> 25 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/if0020.h> 29 30 #include "nouveau_drv.h" 31 #include "nouveau_dma.h" 32 #include "nouveau_bo.h" 33 #include "nouveau_chan.h" 34 #include "nouveau_fence.h" 35 #include "nouveau_abi16.h" 36 #include "nouveau_vmm.h" 37 #include "nouveau_svm.h" 38 39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 40 int nouveau_vram_pushbuf; 41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 42 43 static int 44 nouveau_channel_killed(struct nvif_event *event, void *repv, u32 repc) 45 { 46 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill); 47 struct nouveau_cli *cli = (void *)chan->user.client; 48 49 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); 50 atomic_set(&chan->killed, 1); 51 if (chan->fence) 52 nouveau_fence_context_kill(chan->fence, -ENODEV); 53 54 return NVIF_EVENT_DROP; 55 } 56 57 int 58 nouveau_channel_idle(struct nouveau_channel *chan) 59 { 60 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { 61 struct nouveau_cli *cli = (void *)chan->user.client; 62 struct nouveau_fence *fence = NULL; 63 int ret; 64 65 ret = nouveau_fence_new(chan, false, &fence); 66 if (!ret) { 67 ret = nouveau_fence_wait(fence, false, false); 68 nouveau_fence_unref(&fence); 69 } 70 71 if (ret) { 72 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 73 chan->chid, nvxx_client(&cli->base)->name); 74 return ret; 75 } 76 } 77 return 0; 78 } 79 80 void 81 nouveau_channel_del(struct nouveau_channel **pchan) 82 { 83 struct nouveau_channel *chan = *pchan; 84 if (chan) { 85 struct nouveau_cli *cli = (void *)chan->user.client; 86 87 if (chan->fence) 88 nouveau_fence(chan->drm)->context_del(chan); 89 90 if (cli) 91 nouveau_svmm_part(chan->vmm->svmm, chan->inst); 92 93 nvif_object_dtor(&chan->blit); 94 nvif_object_dtor(&chan->nvsw); 95 nvif_object_dtor(&chan->gart); 96 nvif_object_dtor(&chan->vram); 97 nvif_event_dtor(&chan->kill); 98 nvif_object_dtor(&chan->user); 99 nvif_mem_dtor(&chan->mem_userd); 100 nvif_object_dtor(&chan->push.ctxdma); 101 nouveau_vma_del(&chan->push.vma); 102 nouveau_bo_unmap(chan->push.buffer); 103 if (chan->push.buffer && chan->push.buffer->bo.pin_count) 104 nouveau_bo_unpin(chan->push.buffer); 105 nouveau_bo_ref(NULL, &chan->push.buffer); 106 kfree(chan); 107 } 108 *pchan = NULL; 109 } 110 111 static void 112 nouveau_channel_kick(struct nvif_push *push) 113 { 114 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push); 115 chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn); 116 FIRE_RING(chan); 117 chan->chan._push.bgn = chan->chan._push.cur; 118 } 119 120 static int 121 nouveau_channel_wait(struct nvif_push *push, u32 size) 122 { 123 struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push); 124 int ret; 125 chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn); 126 ret = RING_SPACE(chan, size); 127 if (ret == 0) { 128 chan->chan._push.bgn = chan->chan._push.mem.object.map.ptr; 129 chan->chan._push.bgn = chan->chan._push.bgn + chan->dma.cur; 130 chan->chan._push.cur = chan->chan._push.bgn; 131 chan->chan._push.end = chan->chan._push.bgn + size; 132 } 133 return ret; 134 } 135 136 static int 137 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 138 u32 size, struct nouveau_channel **pchan) 139 { 140 struct nouveau_cli *cli = (void *)device->object.client; 141 struct nv_dma_v0 args = {}; 142 struct nouveau_channel *chan; 143 u32 target; 144 int ret; 145 146 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 147 if (!chan) 148 return -ENOMEM; 149 150 chan->device = device; 151 chan->drm = drm; 152 chan->vmm = cli->svm.cli ? &cli->svm : &cli->vmm; 153 atomic_set(&chan->killed, 0); 154 155 /* allocate memory for dma push buffer */ 156 target = NOUVEAU_GEM_DOMAIN_GART | NOUVEAU_GEM_DOMAIN_COHERENT; 157 if (nouveau_vram_pushbuf) 158 target = NOUVEAU_GEM_DOMAIN_VRAM; 159 160 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, 161 &chan->push.buffer); 162 if (ret == 0) { 163 ret = nouveau_bo_pin(chan->push.buffer, target, false); 164 if (ret == 0) 165 ret = nouveau_bo_map(chan->push.buffer); 166 } 167 168 if (ret) { 169 nouveau_channel_del(pchan); 170 return ret; 171 } 172 173 chan->chan._push.mem.object.parent = cli->base.object.parent; 174 chan->chan._push.mem.object.client = &cli->base; 175 chan->chan._push.mem.object.name = "chanPush"; 176 chan->chan._push.mem.object.map.ptr = chan->push.buffer->kmap.virtual; 177 chan->chan._push.wait = nouveau_channel_wait; 178 chan->chan._push.kick = nouveau_channel_kick; 179 chan->chan.push = &chan->chan._push; 180 181 /* create dma object covering the *entire* memory space that the 182 * pushbuf lives in, this is because the GEM code requires that 183 * we be able to call out to other (indirect) push buffers 184 */ 185 chan->push.addr = chan->push.buffer->offset; 186 187 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 188 ret = nouveau_vma_new(chan->push.buffer, chan->vmm, 189 &chan->push.vma); 190 if (ret) { 191 nouveau_channel_del(pchan); 192 return ret; 193 } 194 195 chan->push.addr = chan->push.vma->addr; 196 197 if (device->info.family >= NV_DEVICE_INFO_V0_FERMI) 198 return 0; 199 200 args.target = NV_DMA_V0_TARGET_VM; 201 args.access = NV_DMA_V0_ACCESS_VM; 202 args.start = 0; 203 args.limit = chan->vmm->vmm.limit - 1; 204 } else 205 if (chan->push.buffer->bo.resource->mem_type == TTM_PL_VRAM) { 206 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 207 /* nv04 vram pushbuf hack, retarget to its location in 208 * the framebuffer bar rather than direct vram access.. 209 * nfi why this exists, it came from the -nv ddx. 210 */ 211 args.target = NV_DMA_V0_TARGET_PCI; 212 args.access = NV_DMA_V0_ACCESS_RDWR; 213 args.start = nvxx_device(device)->func-> 214 resource_addr(nvxx_device(device), 1); 215 args.limit = args.start + device->info.ram_user - 1; 216 } else { 217 args.target = NV_DMA_V0_TARGET_VRAM; 218 args.access = NV_DMA_V0_ACCESS_RDWR; 219 args.start = 0; 220 args.limit = device->info.ram_user - 1; 221 } 222 } else { 223 if (chan->drm->agp.bridge) { 224 args.target = NV_DMA_V0_TARGET_AGP; 225 args.access = NV_DMA_V0_ACCESS_RDWR; 226 args.start = chan->drm->agp.base; 227 args.limit = chan->drm->agp.base + 228 chan->drm->agp.size - 1; 229 } else { 230 args.target = NV_DMA_V0_TARGET_VM; 231 args.access = NV_DMA_V0_ACCESS_RDWR; 232 args.start = 0; 233 args.limit = chan->vmm->vmm.limit - 1; 234 } 235 } 236 237 ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0, 238 NV_DMA_FROM_MEMORY, &args, sizeof(args), 239 &chan->push.ctxdma); 240 if (ret) { 241 nouveau_channel_del(pchan); 242 return ret; 243 } 244 245 return 0; 246 } 247 248 static int 249 nouveau_channel_ctor(struct nouveau_drm *drm, struct nvif_device *device, bool priv, u64 runm, 250 struct nouveau_channel **pchan) 251 { 252 static const struct { 253 s32 oclass; 254 int version; 255 } hosts[] = { 256 { AMPERE_CHANNEL_GPFIFO_B, 0 }, 257 { AMPERE_CHANNEL_GPFIFO_A, 0 }, 258 { TURING_CHANNEL_GPFIFO_A, 0 }, 259 { VOLTA_CHANNEL_GPFIFO_A, 0 }, 260 { PASCAL_CHANNEL_GPFIFO_A, 0 }, 261 { MAXWELL_CHANNEL_GPFIFO_A, 0 }, 262 { KEPLER_CHANNEL_GPFIFO_B, 0 }, 263 { KEPLER_CHANNEL_GPFIFO_A, 0 }, 264 { FERMI_CHANNEL_GPFIFO , 0 }, 265 { G82_CHANNEL_GPFIFO , 0 }, 266 { NV50_CHANNEL_GPFIFO , 0 }, 267 { NV40_CHANNEL_DMA , 0 }, 268 { NV17_CHANNEL_DMA , 0 }, 269 { NV10_CHANNEL_DMA , 0 }, 270 { NV03_CHANNEL_DMA , 0 }, 271 {} 272 }; 273 struct { 274 struct nvif_chan_v0 chan; 275 char name[TASK_COMM_LEN+16]; 276 } args; 277 struct nouveau_cli *cli = (void *)device->object.client; 278 struct nouveau_channel *chan; 279 const u64 plength = 0x10000; 280 const u64 ioffset = plength; 281 const u64 ilength = 0x02000; 282 char name[TASK_COMM_LEN]; 283 int cid, ret; 284 u64 size; 285 286 cid = nvif_mclass(&device->object, hosts); 287 if (cid < 0) 288 return cid; 289 290 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) 291 size = plength; 292 else 293 size = ioffset + ilength; 294 295 /* allocate dma push buffer */ 296 ret = nouveau_channel_prep(drm, device, size, &chan); 297 *pchan = chan; 298 if (ret) 299 return ret; 300 301 /* create channel object */ 302 args.chan.version = 0; 303 args.chan.namelen = sizeof(args.name); 304 args.chan.runlist = __ffs64(runm); 305 args.chan.runq = 0; 306 args.chan.priv = priv; 307 args.chan.devm = BIT(0); 308 if (hosts[cid].oclass < NV50_CHANNEL_GPFIFO) { 309 args.chan.vmm = 0; 310 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma); 311 args.chan.offset = chan->push.addr; 312 args.chan.length = 0; 313 } else { 314 args.chan.vmm = nvif_handle(&chan->vmm->vmm.object); 315 if (hosts[cid].oclass < FERMI_CHANNEL_GPFIFO) 316 args.chan.ctxdma = nvif_handle(&chan->push.ctxdma); 317 else 318 args.chan.ctxdma = 0; 319 args.chan.offset = ioffset + chan->push.addr; 320 args.chan.length = ilength; 321 } 322 args.chan.huserd = 0; 323 args.chan.ouserd = 0; 324 325 /* allocate userd */ 326 if (hosts[cid].oclass >= VOLTA_CHANNEL_GPFIFO_A) { 327 ret = nvif_mem_ctor(&cli->mmu, "abi16ChanUSERD", NVIF_CLASS_MEM_GF100, 328 NVIF_MEM_VRAM | NVIF_MEM_COHERENT | NVIF_MEM_MAPPABLE, 329 0, PAGE_SIZE, NULL, 0, &chan->mem_userd); 330 if (ret) 331 return ret; 332 333 args.chan.huserd = nvif_handle(&chan->mem_userd.object); 334 args.chan.ouserd = 0; 335 336 chan->userd = &chan->mem_userd.object; 337 } else { 338 chan->userd = &chan->user; 339 } 340 341 get_task_comm(name, current); 342 snprintf(args.name, sizeof(args.name), "%s[%d]", name, task_pid_nr(current)); 343 344 ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, hosts[cid].oclass, 345 &args, sizeof(args), &chan->user); 346 if (ret) { 347 nouveau_channel_del(pchan); 348 return ret; 349 } 350 351 chan->runlist = args.chan.runlist; 352 chan->chid = args.chan.chid; 353 chan->inst = args.chan.inst; 354 chan->token = args.chan.token; 355 return 0; 356 } 357 358 static int 359 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 360 { 361 struct nvif_device *device = chan->device; 362 struct nouveau_drm *drm = chan->drm; 363 struct nv_dma_v0 args = {}; 364 int ret, i; 365 366 ret = nvif_object_map(chan->userd, NULL, 0); 367 if (ret) 368 return ret; 369 370 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 371 struct { 372 struct nvif_event_v0 base; 373 struct nvif_chan_event_v0 host; 374 } args; 375 376 args.host.version = 0; 377 args.host.type = NVIF_CHAN_EVENT_V0_KILLED; 378 379 ret = nvif_event_ctor(&chan->user, "abi16ChanKilled", chan->chid, 380 nouveau_channel_killed, false, 381 &args.base, sizeof(args), &chan->kill); 382 if (ret == 0) 383 ret = nvif_event_allow(&chan->kill); 384 if (ret) { 385 NV_ERROR(drm, "Failed to request channel kill " 386 "notification: %d\n", ret); 387 return ret; 388 } 389 } 390 391 /* allocate dma objects to cover all allowed vram, and gart */ 392 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 393 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 394 args.target = NV_DMA_V0_TARGET_VM; 395 args.access = NV_DMA_V0_ACCESS_VM; 396 args.start = 0; 397 args.limit = chan->vmm->vmm.limit - 1; 398 } else { 399 args.target = NV_DMA_V0_TARGET_VRAM; 400 args.access = NV_DMA_V0_ACCESS_RDWR; 401 args.start = 0; 402 args.limit = device->info.ram_user - 1; 403 } 404 405 ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram, 406 NV_DMA_IN_MEMORY, &args, sizeof(args), 407 &chan->vram); 408 if (ret) 409 return ret; 410 411 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 412 args.target = NV_DMA_V0_TARGET_VM; 413 args.access = NV_DMA_V0_ACCESS_VM; 414 args.start = 0; 415 args.limit = chan->vmm->vmm.limit - 1; 416 } else 417 if (chan->drm->agp.bridge) { 418 args.target = NV_DMA_V0_TARGET_AGP; 419 args.access = NV_DMA_V0_ACCESS_RDWR; 420 args.start = chan->drm->agp.base; 421 args.limit = chan->drm->agp.base + 422 chan->drm->agp.size - 1; 423 } else { 424 args.target = NV_DMA_V0_TARGET_VM; 425 args.access = NV_DMA_V0_ACCESS_RDWR; 426 args.start = 0; 427 args.limit = chan->vmm->vmm.limit - 1; 428 } 429 430 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart, 431 NV_DMA_IN_MEMORY, &args, sizeof(args), 432 &chan->gart); 433 if (ret) 434 return ret; 435 } 436 437 /* initialise dma tracking parameters */ 438 switch (chan->user.oclass & 0x00ff) { 439 case 0x006b: 440 case 0x006e: 441 chan->user_put = 0x40; 442 chan->user_get = 0x44; 443 chan->dma.max = (0x10000 / 4) - 2; 444 break; 445 default: 446 chan->user_put = 0x40; 447 chan->user_get = 0x44; 448 chan->user_get_hi = 0x60; 449 chan->dma.ib_base = 0x10000 / 4; 450 chan->dma.ib_max = (0x02000 / 8) - 1; 451 chan->dma.ib_put = 0; 452 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 453 chan->dma.max = chan->dma.ib_base; 454 break; 455 } 456 457 chan->dma.put = 0; 458 chan->dma.cur = chan->dma.put; 459 chan->dma.free = chan->dma.max - chan->dma.cur; 460 461 ret = PUSH_WAIT(chan->chan.push, NOUVEAU_DMA_SKIPS); 462 if (ret) 463 return ret; 464 465 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 466 PUSH_DATA(chan->chan.push, 0x00000000); 467 468 /* allocate software object class (used for fences on <= nv05) */ 469 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 470 ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e, 471 NVIF_CLASS_SW_NV04, 472 NULL, 0, &chan->nvsw); 473 if (ret) 474 return ret; 475 476 ret = PUSH_WAIT(chan->chan.push, 2); 477 if (ret) 478 return ret; 479 480 PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle); 481 PUSH_KICK(chan->chan.push); 482 } 483 484 /* initialise synchronisation */ 485 return nouveau_fence(chan->drm)->context_new(chan); 486 } 487 488 int 489 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 490 bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan) 491 { 492 struct nouveau_cli *cli = (void *)device->object.client; 493 int ret; 494 495 ret = nouveau_channel_ctor(drm, device, priv, runm, pchan); 496 if (ret) { 497 NV_PRINTK(dbg, cli, "channel create, %d\n", ret); 498 return ret; 499 } 500 501 ret = nouveau_channel_init(*pchan, vram, gart); 502 if (ret) { 503 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 504 nouveau_channel_del(pchan); 505 return ret; 506 } 507 508 ret = nouveau_svmm_join((*pchan)->vmm->svmm, (*pchan)->inst); 509 if (ret) 510 nouveau_channel_del(pchan); 511 512 return ret; 513 } 514 515 void 516 nouveau_channels_fini(struct nouveau_drm *drm) 517 { 518 kfree(drm->runl); 519 } 520 521 int 522 nouveau_channels_init(struct nouveau_drm *drm) 523 { 524 struct { 525 struct nv_device_info_v1 m; 526 struct { 527 struct nv_device_info_v1_data channels; 528 struct nv_device_info_v1_data runlists; 529 } v; 530 } args = { 531 .m.version = 1, 532 .m.count = sizeof(args.v) / sizeof(args.v.channels), 533 .v.channels.mthd = NV_DEVICE_HOST_CHANNELS, 534 .v.runlists.mthd = NV_DEVICE_HOST_RUNLISTS, 535 }; 536 struct nvif_object *device = &drm->client.device.object; 537 int ret, i; 538 539 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); 540 if (ret || 541 args.v.runlists.mthd == NV_DEVICE_INFO_INVALID || !args.v.runlists.data || 542 args.v.channels.mthd == NV_DEVICE_INFO_INVALID) 543 return -ENODEV; 544 545 drm->chan_nr = drm->chan_total = args.v.channels.data; 546 drm->runl_nr = fls64(args.v.runlists.data); 547 drm->runl = kcalloc(drm->runl_nr, sizeof(*drm->runl), GFP_KERNEL); 548 if (!drm->runl) 549 return -ENOMEM; 550 551 if (drm->chan_nr == 0) { 552 for (i = 0; i < drm->runl_nr; i++) { 553 if (!(args.v.runlists.data & BIT(i))) 554 continue; 555 556 args.v.channels.mthd = NV_DEVICE_HOST_RUNLIST_CHANNELS; 557 args.v.channels.data = i; 558 559 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args)); 560 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID) 561 return -ENODEV; 562 563 drm->runl[i].chan_nr = args.v.channels.data; 564 drm->runl[i].chan_id_base = drm->chan_total; 565 drm->runl[i].context_base = dma_fence_context_alloc(drm->runl[i].chan_nr); 566 567 drm->chan_total += drm->runl[i].chan_nr; 568 } 569 } else { 570 drm->runl[0].context_base = dma_fence_context_alloc(drm->chan_nr); 571 for (i = 1; i < drm->runl_nr; i++) 572 drm->runl[i].context_base = drm->runl[0].context_base; 573 574 } 575 576 return 0; 577 } 578