1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <nvif/os.h> 26 #include <nvif/class.h> 27 #include <nvif/ioctl.h> 28 29 /*XXX*/ 30 #include <core/client.h> 31 32 #include "nouveau_drm.h" 33 #include "nouveau_dma.h" 34 #include "nouveau_bo.h" 35 #include "nouveau_chan.h" 36 #include "nouveau_fence.h" 37 #include "nouveau_abi16.h" 38 39 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 40 int nouveau_vram_pushbuf; 41 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 42 43 int 44 nouveau_channel_idle(struct nouveau_channel *chan) 45 { 46 struct nouveau_cli *cli = (void *)chan->user.client; 47 struct nouveau_fence *fence = NULL; 48 int ret; 49 50 ret = nouveau_fence_new(chan, false, &fence); 51 if (!ret) { 52 ret = nouveau_fence_wait(fence, false, false); 53 nouveau_fence_unref(&fence); 54 } 55 56 if (ret) 57 NV_PRINTK(err, cli, "failed to idle channel 0x%08x [%s]\n", 58 chan->user.handle, nvxx_client(&cli->base)->name); 59 return ret; 60 } 61 62 void 63 nouveau_channel_del(struct nouveau_channel **pchan) 64 { 65 struct nouveau_channel *chan = *pchan; 66 if (chan) { 67 if (chan->fence) { 68 nouveau_channel_idle(chan); 69 nouveau_fence(chan->drm)->context_del(chan); 70 } 71 nvif_object_fini(&chan->nvsw); 72 nvif_object_fini(&chan->gart); 73 nvif_object_fini(&chan->vram); 74 nvif_object_fini(&chan->user); 75 nvif_object_fini(&chan->push.ctxdma); 76 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); 77 nouveau_bo_unmap(chan->push.buffer); 78 if (chan->push.buffer && chan->push.buffer->pin_refcnt) 79 nouveau_bo_unpin(chan->push.buffer); 80 nouveau_bo_ref(NULL, &chan->push.buffer); 81 kfree(chan); 82 } 83 *pchan = NULL; 84 } 85 86 static int 87 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 88 u32 handle, u32 size, struct nouveau_channel **pchan) 89 { 90 struct nouveau_cli *cli = (void *)device->object.client; 91 struct nvkm_mmu *mmu = nvxx_mmu(device); 92 struct nv_dma_v0 args = {}; 93 struct nouveau_channel *chan; 94 u32 target; 95 int ret; 96 97 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 98 if (!chan) 99 return -ENOMEM; 100 101 chan->device = device; 102 chan->drm = drm; 103 104 /* allocate memory for dma push buffer */ 105 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 106 if (nouveau_vram_pushbuf) 107 target = TTM_PL_FLAG_VRAM; 108 109 ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL, 110 &chan->push.buffer); 111 if (ret == 0) { 112 ret = nouveau_bo_pin(chan->push.buffer, target, false); 113 if (ret == 0) 114 ret = nouveau_bo_map(chan->push.buffer); 115 } 116 117 if (ret) { 118 nouveau_channel_del(pchan); 119 return ret; 120 } 121 122 /* create dma object covering the *entire* memory space that the 123 * pushbuf lives in, this is because the GEM code requires that 124 * we be able to call out to other (indirect) push buffers 125 */ 126 chan->push.vma.offset = chan->push.buffer->bo.offset; 127 128 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 129 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm, 130 &chan->push.vma); 131 if (ret) { 132 nouveau_channel_del(pchan); 133 return ret; 134 } 135 136 args.target = NV_DMA_V0_TARGET_VM; 137 args.access = NV_DMA_V0_ACCESS_VM; 138 args.start = 0; 139 args.limit = cli->vm->mmu->limit - 1; 140 } else 141 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 142 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 143 /* nv04 vram pushbuf hack, retarget to its location in 144 * the framebuffer bar rather than direct vram access.. 145 * nfi why this exists, it came from the -nv ddx. 146 */ 147 args.target = NV_DMA_V0_TARGET_PCI; 148 args.access = NV_DMA_V0_ACCESS_RDWR; 149 args.start = nv_device_resource_start(nvxx_device(device), 1); 150 args.limit = args.start + device->info.ram_user - 1; 151 } else { 152 args.target = NV_DMA_V0_TARGET_VRAM; 153 args.access = NV_DMA_V0_ACCESS_RDWR; 154 args.start = 0; 155 args.limit = device->info.ram_user - 1; 156 } 157 } else { 158 if (chan->drm->agp.stat == ENABLED) { 159 args.target = NV_DMA_V0_TARGET_AGP; 160 args.access = NV_DMA_V0_ACCESS_RDWR; 161 args.start = chan->drm->agp.base; 162 args.limit = chan->drm->agp.base + 163 chan->drm->agp.size - 1; 164 } else { 165 args.target = NV_DMA_V0_TARGET_VM; 166 args.access = NV_DMA_V0_ACCESS_RDWR; 167 args.start = 0; 168 args.limit = mmu->limit - 1; 169 } 170 } 171 172 ret = nvif_object_init(&device->object, NVDRM_PUSH | 173 (handle & 0xffff), NV_DMA_FROM_MEMORY, 174 &args, sizeof(args), &chan->push.ctxdma); 175 if (ret) { 176 nouveau_channel_del(pchan); 177 return ret; 178 } 179 180 return 0; 181 } 182 183 static int 184 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, 185 u32 handle, u32 engine, struct nouveau_channel **pchan) 186 { 187 static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A, 188 KEPLER_CHANNEL_GPFIFO_A, 189 FERMI_CHANNEL_GPFIFO, 190 G82_CHANNEL_GPFIFO, 191 NV50_CHANNEL_GPFIFO, 192 0 }; 193 const u16 *oclass = oclasses; 194 union { 195 struct nv50_channel_gpfifo_v0 nv50; 196 struct fermi_channel_gpfifo_v0 fermi; 197 struct kepler_channel_gpfifo_a_v0 kepler; 198 } args; 199 struct nouveau_channel *chan; 200 u32 size; 201 int ret; 202 203 /* allocate dma push buffer */ 204 ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan); 205 *pchan = chan; 206 if (ret) 207 return ret; 208 209 /* create channel object */ 210 do { 211 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { 212 args.kepler.version = 0; 213 args.kepler.engine = engine; 214 args.kepler.ilength = 0x02000; 215 args.kepler.ioffset = 0x10000 + chan->push.vma.offset; 216 args.kepler.vm = 0; 217 size = sizeof(args.kepler); 218 } else 219 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { 220 args.fermi.version = 0; 221 args.fermi.ilength = 0x02000; 222 args.fermi.ioffset = 0x10000 + chan->push.vma.offset; 223 args.fermi.vm = 0; 224 size = sizeof(args.fermi); 225 } else { 226 args.nv50.version = 0; 227 args.nv50.ilength = 0x02000; 228 args.nv50.ioffset = 0x10000 + chan->push.vma.offset; 229 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); 230 args.nv50.vm = 0; 231 size = sizeof(args.nv50); 232 } 233 234 ret = nvif_object_init(&device->object, handle, *oclass++, 235 &args, size, &chan->user); 236 if (ret == 0) { 237 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) 238 chan->chid = args.kepler.chid; 239 else 240 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) 241 chan->chid = args.fermi.chid; 242 else 243 chan->chid = args.nv50.chid; 244 return ret; 245 } 246 } while (*oclass); 247 248 nouveau_channel_del(pchan); 249 return ret; 250 } 251 252 static int 253 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, 254 u32 handle, struct nouveau_channel **pchan) 255 { 256 static const u16 oclasses[] = { NV40_CHANNEL_DMA, 257 NV17_CHANNEL_DMA, 258 NV10_CHANNEL_DMA, 259 NV03_CHANNEL_DMA, 260 0 }; 261 const u16 *oclass = oclasses; 262 struct nv03_channel_dma_v0 args; 263 struct nouveau_channel *chan; 264 int ret; 265 266 /* allocate dma push buffer */ 267 ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan); 268 *pchan = chan; 269 if (ret) 270 return ret; 271 272 /* create channel object */ 273 args.version = 0; 274 args.pushbuf = nvif_handle(&chan->push.ctxdma); 275 args.offset = chan->push.vma.offset; 276 277 do { 278 ret = nvif_object_init(&device->object, handle, *oclass++, 279 &args, sizeof(args), &chan->user); 280 if (ret == 0) { 281 chan->chid = args.chid; 282 return ret; 283 } 284 } while (ret && *oclass); 285 286 nouveau_channel_del(pchan); 287 return ret; 288 } 289 290 static int 291 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 292 { 293 struct nvif_device *device = chan->device; 294 struct nouveau_cli *cli = (void *)chan->user.client; 295 struct nvkm_mmu *mmu = nvxx_mmu(device); 296 struct nvkm_sw_chan *swch; 297 struct nv_dma_v0 args = {}; 298 int ret, i; 299 300 nvif_object_map(&chan->user); 301 302 /* allocate dma objects to cover all allowed vram, and gart */ 303 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 304 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 305 args.target = NV_DMA_V0_TARGET_VM; 306 args.access = NV_DMA_V0_ACCESS_VM; 307 args.start = 0; 308 args.limit = cli->vm->mmu->limit - 1; 309 } else { 310 args.target = NV_DMA_V0_TARGET_VRAM; 311 args.access = NV_DMA_V0_ACCESS_RDWR; 312 args.start = 0; 313 args.limit = device->info.ram_user - 1; 314 } 315 316 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, 317 &args, sizeof(args), &chan->vram); 318 if (ret) 319 return ret; 320 321 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 322 args.target = NV_DMA_V0_TARGET_VM; 323 args.access = NV_DMA_V0_ACCESS_VM; 324 args.start = 0; 325 args.limit = cli->vm->mmu->limit - 1; 326 } else 327 if (chan->drm->agp.stat == ENABLED) { 328 args.target = NV_DMA_V0_TARGET_AGP; 329 args.access = NV_DMA_V0_ACCESS_RDWR; 330 args.start = chan->drm->agp.base; 331 args.limit = chan->drm->agp.base + 332 chan->drm->agp.size - 1; 333 } else { 334 args.target = NV_DMA_V0_TARGET_VM; 335 args.access = NV_DMA_V0_ACCESS_RDWR; 336 args.start = 0; 337 args.limit = mmu->limit - 1; 338 } 339 340 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, 341 &args, sizeof(args), &chan->gart); 342 if (ret) 343 return ret; 344 } 345 346 /* initialise dma tracking parameters */ 347 switch (chan->user.oclass & 0x00ff) { 348 case 0x006b: 349 case 0x006e: 350 chan->user_put = 0x40; 351 chan->user_get = 0x44; 352 chan->dma.max = (0x10000 / 4) - 2; 353 break; 354 default: 355 chan->user_put = 0x40; 356 chan->user_get = 0x44; 357 chan->user_get_hi = 0x60; 358 chan->dma.ib_base = 0x10000 / 4; 359 chan->dma.ib_max = (0x02000 / 8) - 1; 360 chan->dma.ib_put = 0; 361 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 362 chan->dma.max = chan->dma.ib_base; 363 break; 364 } 365 366 chan->dma.put = 0; 367 chan->dma.cur = chan->dma.put; 368 chan->dma.free = chan->dma.max - chan->dma.cur; 369 370 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 371 if (ret) 372 return ret; 373 374 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 375 OUT_RING(chan, 0x00000000); 376 377 /* allocate software object class (used for fences on <= nv05) */ 378 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 379 ret = nvif_object_init(&chan->user, 0x006e, 380 NVIF_IOCTL_NEW_V0_SW_NV04, 381 NULL, 0, &chan->nvsw); 382 if (ret) 383 return ret; 384 385 swch = (void *)nvxx_object(&chan->nvsw)->parent; 386 swch->flip = nouveau_flip_complete; 387 swch->flip_data = chan; 388 389 ret = RING_SPACE(chan, 2); 390 if (ret) 391 return ret; 392 393 BEGIN_NV04(chan, NvSubSw, 0x0000, 1); 394 OUT_RING (chan, chan->nvsw.handle); 395 FIRE_RING (chan); 396 } 397 398 /* initialise synchronisation */ 399 return nouveau_fence(chan->drm)->context_new(chan); 400 } 401 402 int 403 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 404 u32 handle, u32 arg0, u32 arg1, 405 struct nouveau_channel **pchan) 406 { 407 struct nouveau_cli *cli = (void *)device->object.client; 408 bool super; 409 int ret; 410 411 /* hack until fencenv50 is fixed, and agp access relaxed */ 412 super = cli->base.super; 413 cli->base.super = true; 414 415 ret = nouveau_channel_ind(drm, device, handle, arg0, pchan); 416 if (ret) { 417 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); 418 ret = nouveau_channel_dma(drm, device, handle, pchan); 419 if (ret) { 420 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); 421 goto done; 422 } 423 } 424 425 ret = nouveau_channel_init(*pchan, arg0, arg1); 426 if (ret) { 427 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 428 nouveau_channel_del(pchan); 429 } 430 431 done: 432 cli->base.super = super; 433 return ret; 434 } 435