1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <nvif/os.h> 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/cl006b.h> 29 #include <nvif/cl506f.h> 30 #include <nvif/cl906f.h> 31 #include <nvif/cla06f.h> 32 #include <nvif/ioctl.h> 33 34 /*XXX*/ 35 #include <core/client.h> 36 37 #include "nouveau_drv.h" 38 #include "nouveau_dma.h" 39 #include "nouveau_bo.h" 40 #include "nouveau_chan.h" 41 #include "nouveau_fence.h" 42 #include "nouveau_abi16.h" 43 44 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 45 int nouveau_vram_pushbuf; 46 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 47 48 int 49 nouveau_channel_idle(struct nouveau_channel *chan) 50 { 51 if (likely(chan && chan->fence)) { 52 struct nouveau_cli *cli = (void *)chan->user.client; 53 struct nouveau_fence *fence = NULL; 54 int ret; 55 56 ret = nouveau_fence_new(chan, false, &fence); 57 if (!ret) { 58 ret = nouveau_fence_wait(fence, false, false); 59 nouveau_fence_unref(&fence); 60 } 61 62 if (ret) { 63 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 64 chan->chid, nvxx_client(&cli->base)->name); 65 return ret; 66 } 67 } 68 return 0; 69 } 70 71 void 72 nouveau_channel_del(struct nouveau_channel **pchan) 73 { 74 struct nouveau_channel *chan = *pchan; 75 if (chan) { 76 if (chan->fence) 77 nouveau_fence(chan->drm)->context_del(chan); 78 nvif_object_fini(&chan->nvsw); 79 nvif_object_fini(&chan->gart); 80 nvif_object_fini(&chan->vram); 81 nvif_object_fini(&chan->user); 82 nvif_object_fini(&chan->push.ctxdma); 83 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); 84 nouveau_bo_unmap(chan->push.buffer); 85 if (chan->push.buffer && chan->push.buffer->pin_refcnt) 86 nouveau_bo_unpin(chan->push.buffer); 87 nouveau_bo_ref(NULL, &chan->push.buffer); 88 kfree(chan); 89 } 90 *pchan = NULL; 91 } 92 93 static int 94 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 95 u32 size, struct nouveau_channel **pchan) 96 { 97 struct nouveau_cli *cli = (void *)device->object.client; 98 struct nvkm_mmu *mmu = nvxx_mmu(device); 99 struct nv_dma_v0 args = {}; 100 struct nouveau_channel *chan; 101 u32 target; 102 int ret; 103 104 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 105 if (!chan) 106 return -ENOMEM; 107 108 chan->device = device; 109 chan->drm = drm; 110 111 /* allocate memory for dma push buffer */ 112 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 113 if (nouveau_vram_pushbuf) 114 target = TTM_PL_FLAG_VRAM; 115 116 ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL, 117 &chan->push.buffer); 118 if (ret == 0) { 119 ret = nouveau_bo_pin(chan->push.buffer, target, false); 120 if (ret == 0) 121 ret = nouveau_bo_map(chan->push.buffer); 122 } 123 124 if (ret) { 125 nouveau_channel_del(pchan); 126 return ret; 127 } 128 129 /* create dma object covering the *entire* memory space that the 130 * pushbuf lives in, this is because the GEM code requires that 131 * we be able to call out to other (indirect) push buffers 132 */ 133 chan->push.vma.offset = chan->push.buffer->bo.offset; 134 135 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 136 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm, 137 &chan->push.vma); 138 if (ret) { 139 nouveau_channel_del(pchan); 140 return ret; 141 } 142 143 args.target = NV_DMA_V0_TARGET_VM; 144 args.access = NV_DMA_V0_ACCESS_VM; 145 args.start = 0; 146 args.limit = cli->vm->mmu->limit - 1; 147 } else 148 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 149 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 150 /* nv04 vram pushbuf hack, retarget to its location in 151 * the framebuffer bar rather than direct vram access.. 152 * nfi why this exists, it came from the -nv ddx. 153 */ 154 args.target = NV_DMA_V0_TARGET_PCI; 155 args.access = NV_DMA_V0_ACCESS_RDWR; 156 args.start = nvxx_device(device)->func-> 157 resource_addr(nvxx_device(device), 1); 158 args.limit = args.start + device->info.ram_user - 1; 159 } else { 160 args.target = NV_DMA_V0_TARGET_VRAM; 161 args.access = NV_DMA_V0_ACCESS_RDWR; 162 args.start = 0; 163 args.limit = device->info.ram_user - 1; 164 } 165 } else { 166 if (chan->drm->agp.bridge) { 167 args.target = NV_DMA_V0_TARGET_AGP; 168 args.access = NV_DMA_V0_ACCESS_RDWR; 169 args.start = chan->drm->agp.base; 170 args.limit = chan->drm->agp.base + 171 chan->drm->agp.size - 1; 172 } else { 173 args.target = NV_DMA_V0_TARGET_VM; 174 args.access = NV_DMA_V0_ACCESS_RDWR; 175 args.start = 0; 176 args.limit = mmu->limit - 1; 177 } 178 } 179 180 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, 181 &args, sizeof(args), &chan->push.ctxdma); 182 if (ret) { 183 nouveau_channel_del(pchan); 184 return ret; 185 } 186 187 return 0; 188 } 189 190 static int 191 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, 192 u32 engine, struct nouveau_channel **pchan) 193 { 194 static const u16 oclasses[] = { PASCAL_CHANNEL_GPFIFO_A, 195 MAXWELL_CHANNEL_GPFIFO_A, 196 KEPLER_CHANNEL_GPFIFO_B, 197 KEPLER_CHANNEL_GPFIFO_A, 198 FERMI_CHANNEL_GPFIFO, 199 G82_CHANNEL_GPFIFO, 200 NV50_CHANNEL_GPFIFO, 201 0 }; 202 const u16 *oclass = oclasses; 203 union { 204 struct nv50_channel_gpfifo_v0 nv50; 205 struct fermi_channel_gpfifo_v0 fermi; 206 struct kepler_channel_gpfifo_a_v0 kepler; 207 } args; 208 struct nouveau_channel *chan; 209 u32 size; 210 int ret; 211 212 /* allocate dma push buffer */ 213 ret = nouveau_channel_prep(drm, device, 0x12000, &chan); 214 *pchan = chan; 215 if (ret) 216 return ret; 217 218 /* create channel object */ 219 do { 220 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { 221 args.kepler.version = 0; 222 args.kepler.engines = engine; 223 args.kepler.ilength = 0x02000; 224 args.kepler.ioffset = 0x10000 + chan->push.vma.offset; 225 args.kepler.vm = 0; 226 size = sizeof(args.kepler); 227 } else 228 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { 229 args.fermi.version = 0; 230 args.fermi.ilength = 0x02000; 231 args.fermi.ioffset = 0x10000 + chan->push.vma.offset; 232 args.fermi.vm = 0; 233 size = sizeof(args.fermi); 234 } else { 235 args.nv50.version = 0; 236 args.nv50.ilength = 0x02000; 237 args.nv50.ioffset = 0x10000 + chan->push.vma.offset; 238 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); 239 args.nv50.vm = 0; 240 size = sizeof(args.nv50); 241 } 242 243 ret = nvif_object_init(&device->object, 0, *oclass++, 244 &args, size, &chan->user); 245 if (ret == 0) { 246 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) 247 chan->chid = args.kepler.chid; 248 else 249 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) 250 chan->chid = args.fermi.chid; 251 else 252 chan->chid = args.nv50.chid; 253 return ret; 254 } 255 } while (*oclass); 256 257 nouveau_channel_del(pchan); 258 return ret; 259 } 260 261 static int 262 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, 263 struct nouveau_channel **pchan) 264 { 265 static const u16 oclasses[] = { NV40_CHANNEL_DMA, 266 NV17_CHANNEL_DMA, 267 NV10_CHANNEL_DMA, 268 NV03_CHANNEL_DMA, 269 0 }; 270 const u16 *oclass = oclasses; 271 struct nv03_channel_dma_v0 args; 272 struct nouveau_channel *chan; 273 int ret; 274 275 /* allocate dma push buffer */ 276 ret = nouveau_channel_prep(drm, device, 0x10000, &chan); 277 *pchan = chan; 278 if (ret) 279 return ret; 280 281 /* create channel object */ 282 args.version = 0; 283 args.pushbuf = nvif_handle(&chan->push.ctxdma); 284 args.offset = chan->push.vma.offset; 285 286 do { 287 ret = nvif_object_init(&device->object, 0, *oclass++, 288 &args, sizeof(args), &chan->user); 289 if (ret == 0) { 290 chan->chid = args.chid; 291 return ret; 292 } 293 } while (ret && *oclass); 294 295 nouveau_channel_del(pchan); 296 return ret; 297 } 298 299 static int 300 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 301 { 302 struct nvif_device *device = chan->device; 303 struct nouveau_cli *cli = (void *)chan->user.client; 304 struct nvkm_mmu *mmu = nvxx_mmu(device); 305 struct nv_dma_v0 args = {}; 306 int ret, i; 307 308 nvif_object_map(&chan->user); 309 310 /* allocate dma objects to cover all allowed vram, and gart */ 311 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 312 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 313 args.target = NV_DMA_V0_TARGET_VM; 314 args.access = NV_DMA_V0_ACCESS_VM; 315 args.start = 0; 316 args.limit = cli->vm->mmu->limit - 1; 317 } else { 318 args.target = NV_DMA_V0_TARGET_VRAM; 319 args.access = NV_DMA_V0_ACCESS_RDWR; 320 args.start = 0; 321 args.limit = device->info.ram_user - 1; 322 } 323 324 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, 325 &args, sizeof(args), &chan->vram); 326 if (ret) 327 return ret; 328 329 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 330 args.target = NV_DMA_V0_TARGET_VM; 331 args.access = NV_DMA_V0_ACCESS_VM; 332 args.start = 0; 333 args.limit = cli->vm->mmu->limit - 1; 334 } else 335 if (chan->drm->agp.bridge) { 336 args.target = NV_DMA_V0_TARGET_AGP; 337 args.access = NV_DMA_V0_ACCESS_RDWR; 338 args.start = chan->drm->agp.base; 339 args.limit = chan->drm->agp.base + 340 chan->drm->agp.size - 1; 341 } else { 342 args.target = NV_DMA_V0_TARGET_VM; 343 args.access = NV_DMA_V0_ACCESS_RDWR; 344 args.start = 0; 345 args.limit = mmu->limit - 1; 346 } 347 348 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, 349 &args, sizeof(args), &chan->gart); 350 if (ret) 351 return ret; 352 } 353 354 /* initialise dma tracking parameters */ 355 switch (chan->user.oclass & 0x00ff) { 356 case 0x006b: 357 case 0x006e: 358 chan->user_put = 0x40; 359 chan->user_get = 0x44; 360 chan->dma.max = (0x10000 / 4) - 2; 361 break; 362 default: 363 chan->user_put = 0x40; 364 chan->user_get = 0x44; 365 chan->user_get_hi = 0x60; 366 chan->dma.ib_base = 0x10000 / 4; 367 chan->dma.ib_max = (0x02000 / 8) - 1; 368 chan->dma.ib_put = 0; 369 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 370 chan->dma.max = chan->dma.ib_base; 371 break; 372 } 373 374 chan->dma.put = 0; 375 chan->dma.cur = chan->dma.put; 376 chan->dma.free = chan->dma.max - chan->dma.cur; 377 378 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 379 if (ret) 380 return ret; 381 382 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 383 OUT_RING(chan, 0x00000000); 384 385 /* allocate software object class (used for fences on <= nv05) */ 386 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 387 ret = nvif_object_init(&chan->user, 0x006e, 388 NVIF_CLASS_SW_NV04, 389 NULL, 0, &chan->nvsw); 390 if (ret) 391 return ret; 392 393 ret = RING_SPACE(chan, 2); 394 if (ret) 395 return ret; 396 397 BEGIN_NV04(chan, NvSubSw, 0x0000, 1); 398 OUT_RING (chan, chan->nvsw.handle); 399 FIRE_RING (chan); 400 } 401 402 /* initialise synchronisation */ 403 return nouveau_fence(chan->drm)->context_new(chan); 404 } 405 406 int 407 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 408 u32 arg0, u32 arg1, struct nouveau_channel **pchan) 409 { 410 struct nouveau_cli *cli = (void *)device->object.client; 411 bool super; 412 int ret; 413 414 /* hack until fencenv50 is fixed, and agp access relaxed */ 415 super = cli->base.super; 416 cli->base.super = true; 417 418 ret = nouveau_channel_ind(drm, device, arg0, pchan); 419 if (ret) { 420 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); 421 ret = nouveau_channel_dma(drm, device, pchan); 422 if (ret) { 423 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); 424 goto done; 425 } 426 } 427 428 ret = nouveau_channel_init(*pchan, arg0, arg1); 429 if (ret) { 430 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 431 nouveau_channel_del(pchan); 432 } 433 434 done: 435 cli->base.super = super; 436 return ret; 437 } 438