1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <nvif/os.h> 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/cl006b.h> 29 #include <nvif/cl506f.h> 30 #include <nvif/cl906f.h> 31 #include <nvif/cla06f.h> 32 #include <nvif/ioctl.h> 33 34 /*XXX*/ 35 #include <core/client.h> 36 37 #include "nouveau_drv.h" 38 #include "nouveau_dma.h" 39 #include "nouveau_bo.h" 40 #include "nouveau_chan.h" 41 #include "nouveau_fence.h" 42 #include "nouveau_abi16.h" 43 44 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 45 int nouveau_vram_pushbuf; 46 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 47 48 int 49 nouveau_channel_idle(struct nouveau_channel *chan) 50 { 51 if (likely(chan && chan->fence)) { 52 struct nouveau_cli *cli = (void *)chan->user.client; 53 struct nouveau_fence *fence = NULL; 54 int ret; 55 56 ret = nouveau_fence_new(chan, false, &fence); 57 if (!ret) { 58 ret = nouveau_fence_wait(fence, false, false); 59 nouveau_fence_unref(&fence); 60 } 61 62 if (ret) { 63 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 64 chan->chid, nvxx_client(&cli->base)->name); 65 return ret; 66 } 67 } 68 return 0; 69 } 70 71 void 72 nouveau_channel_del(struct nouveau_channel **pchan) 73 { 74 struct nouveau_channel *chan = *pchan; 75 if (chan) { 76 if (chan->fence) 77 nouveau_fence(chan->drm)->context_del(chan); 78 nvif_object_fini(&chan->nvsw); 79 nvif_object_fini(&chan->gart); 80 nvif_object_fini(&chan->vram); 81 nvif_object_fini(&chan->user); 82 nvif_object_fini(&chan->push.ctxdma); 83 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); 84 nouveau_bo_unmap(chan->push.buffer); 85 if (chan->push.buffer && chan->push.buffer->pin_refcnt) 86 nouveau_bo_unpin(chan->push.buffer); 87 nouveau_bo_ref(NULL, &chan->push.buffer); 88 kfree(chan); 89 } 90 *pchan = NULL; 91 } 92 93 static int 94 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 95 u32 size, struct nouveau_channel **pchan) 96 { 97 struct nouveau_cli *cli = (void *)device->object.client; 98 struct nvkm_mmu *mmu = nvxx_mmu(device); 99 struct nv_dma_v0 args = {}; 100 struct nouveau_channel *chan; 101 u32 target; 102 int ret; 103 104 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 105 if (!chan) 106 return -ENOMEM; 107 108 chan->device = device; 109 chan->drm = drm; 110 111 /* allocate memory for dma push buffer */ 112 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 113 if (nouveau_vram_pushbuf) 114 target = TTM_PL_FLAG_VRAM; 115 116 ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL, 117 &chan->push.buffer); 118 if (ret == 0) { 119 ret = nouveau_bo_pin(chan->push.buffer, target, false); 120 if (ret == 0) 121 ret = nouveau_bo_map(chan->push.buffer); 122 } 123 124 if (ret) { 125 nouveau_channel_del(pchan); 126 return ret; 127 } 128 129 /* create dma object covering the *entire* memory space that the 130 * pushbuf lives in, this is because the GEM code requires that 131 * we be able to call out to other (indirect) push buffers 132 */ 133 chan->push.vma.offset = chan->push.buffer->bo.offset; 134 135 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 136 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm, 137 &chan->push.vma); 138 if (ret) { 139 nouveau_channel_del(pchan); 140 return ret; 141 } 142 143 args.target = NV_DMA_V0_TARGET_VM; 144 args.access = NV_DMA_V0_ACCESS_VM; 145 args.start = 0; 146 args.limit = cli->vm->mmu->limit - 1; 147 } else 148 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 149 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 150 /* nv04 vram pushbuf hack, retarget to its location in 151 * the framebuffer bar rather than direct vram access.. 152 * nfi why this exists, it came from the -nv ddx. 153 */ 154 args.target = NV_DMA_V0_TARGET_PCI; 155 args.access = NV_DMA_V0_ACCESS_RDWR; 156 args.start = nvxx_device(device)->func-> 157 resource_addr(nvxx_device(device), 1); 158 args.limit = args.start + device->info.ram_user - 1; 159 } else { 160 args.target = NV_DMA_V0_TARGET_VRAM; 161 args.access = NV_DMA_V0_ACCESS_RDWR; 162 args.start = 0; 163 args.limit = device->info.ram_user - 1; 164 } 165 } else { 166 if (chan->drm->agp.bridge) { 167 args.target = NV_DMA_V0_TARGET_AGP; 168 args.access = NV_DMA_V0_ACCESS_RDWR; 169 args.start = chan->drm->agp.base; 170 args.limit = chan->drm->agp.base + 171 chan->drm->agp.size - 1; 172 } else { 173 args.target = NV_DMA_V0_TARGET_VM; 174 args.access = NV_DMA_V0_ACCESS_RDWR; 175 args.start = 0; 176 args.limit = mmu->limit - 1; 177 } 178 } 179 180 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, 181 &args, sizeof(args), &chan->push.ctxdma); 182 if (ret) { 183 nouveau_channel_del(pchan); 184 return ret; 185 } 186 187 return 0; 188 } 189 190 static int 191 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, 192 u32 engine, struct nouveau_channel **pchan) 193 { 194 static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A, 195 KEPLER_CHANNEL_GPFIFO_B, 196 KEPLER_CHANNEL_GPFIFO_A, 197 FERMI_CHANNEL_GPFIFO, 198 G82_CHANNEL_GPFIFO, 199 NV50_CHANNEL_GPFIFO, 200 0 }; 201 const u16 *oclass = oclasses; 202 union { 203 struct nv50_channel_gpfifo_v0 nv50; 204 struct fermi_channel_gpfifo_v0 fermi; 205 struct kepler_channel_gpfifo_a_v0 kepler; 206 } args; 207 struct nouveau_channel *chan; 208 u32 size; 209 int ret; 210 211 /* allocate dma push buffer */ 212 ret = nouveau_channel_prep(drm, device, 0x12000, &chan); 213 *pchan = chan; 214 if (ret) 215 return ret; 216 217 /* create channel object */ 218 do { 219 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { 220 args.kepler.version = 0; 221 args.kepler.engines = engine; 222 args.kepler.ilength = 0x02000; 223 args.kepler.ioffset = 0x10000 + chan->push.vma.offset; 224 args.kepler.vm = 0; 225 size = sizeof(args.kepler); 226 } else 227 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { 228 args.fermi.version = 0; 229 args.fermi.ilength = 0x02000; 230 args.fermi.ioffset = 0x10000 + chan->push.vma.offset; 231 args.fermi.vm = 0; 232 size = sizeof(args.fermi); 233 } else { 234 args.nv50.version = 0; 235 args.nv50.ilength = 0x02000; 236 args.nv50.ioffset = 0x10000 + chan->push.vma.offset; 237 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); 238 args.nv50.vm = 0; 239 size = sizeof(args.nv50); 240 } 241 242 ret = nvif_object_init(&device->object, 0, *oclass++, 243 &args, size, &chan->user); 244 if (ret == 0) { 245 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) 246 chan->chid = args.kepler.chid; 247 else 248 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) 249 chan->chid = args.fermi.chid; 250 else 251 chan->chid = args.nv50.chid; 252 return ret; 253 } 254 } while (*oclass); 255 256 nouveau_channel_del(pchan); 257 return ret; 258 } 259 260 static int 261 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, 262 struct nouveau_channel **pchan) 263 { 264 static const u16 oclasses[] = { NV40_CHANNEL_DMA, 265 NV17_CHANNEL_DMA, 266 NV10_CHANNEL_DMA, 267 NV03_CHANNEL_DMA, 268 0 }; 269 const u16 *oclass = oclasses; 270 struct nv03_channel_dma_v0 args; 271 struct nouveau_channel *chan; 272 int ret; 273 274 /* allocate dma push buffer */ 275 ret = nouveau_channel_prep(drm, device, 0x10000, &chan); 276 *pchan = chan; 277 if (ret) 278 return ret; 279 280 /* create channel object */ 281 args.version = 0; 282 args.pushbuf = nvif_handle(&chan->push.ctxdma); 283 args.offset = chan->push.vma.offset; 284 285 do { 286 ret = nvif_object_init(&device->object, 0, *oclass++, 287 &args, sizeof(args), &chan->user); 288 if (ret == 0) { 289 chan->chid = args.chid; 290 return ret; 291 } 292 } while (ret && *oclass); 293 294 nouveau_channel_del(pchan); 295 return ret; 296 } 297 298 static int 299 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 300 { 301 struct nvif_device *device = chan->device; 302 struct nouveau_cli *cli = (void *)chan->user.client; 303 struct nvkm_mmu *mmu = nvxx_mmu(device); 304 struct nv_dma_v0 args = {}; 305 int ret, i; 306 307 nvif_object_map(&chan->user); 308 309 /* allocate dma objects to cover all allowed vram, and gart */ 310 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 311 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 312 args.target = NV_DMA_V0_TARGET_VM; 313 args.access = NV_DMA_V0_ACCESS_VM; 314 args.start = 0; 315 args.limit = cli->vm->mmu->limit - 1; 316 } else { 317 args.target = NV_DMA_V0_TARGET_VRAM; 318 args.access = NV_DMA_V0_ACCESS_RDWR; 319 args.start = 0; 320 args.limit = device->info.ram_user - 1; 321 } 322 323 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, 324 &args, sizeof(args), &chan->vram); 325 if (ret) 326 return ret; 327 328 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 329 args.target = NV_DMA_V0_TARGET_VM; 330 args.access = NV_DMA_V0_ACCESS_VM; 331 args.start = 0; 332 args.limit = cli->vm->mmu->limit - 1; 333 } else 334 if (chan->drm->agp.bridge) { 335 args.target = NV_DMA_V0_TARGET_AGP; 336 args.access = NV_DMA_V0_ACCESS_RDWR; 337 args.start = chan->drm->agp.base; 338 args.limit = chan->drm->agp.base + 339 chan->drm->agp.size - 1; 340 } else { 341 args.target = NV_DMA_V0_TARGET_VM; 342 args.access = NV_DMA_V0_ACCESS_RDWR; 343 args.start = 0; 344 args.limit = mmu->limit - 1; 345 } 346 347 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, 348 &args, sizeof(args), &chan->gart); 349 if (ret) 350 return ret; 351 } 352 353 /* initialise dma tracking parameters */ 354 switch (chan->user.oclass & 0x00ff) { 355 case 0x006b: 356 case 0x006e: 357 chan->user_put = 0x40; 358 chan->user_get = 0x44; 359 chan->dma.max = (0x10000 / 4) - 2; 360 break; 361 default: 362 chan->user_put = 0x40; 363 chan->user_get = 0x44; 364 chan->user_get_hi = 0x60; 365 chan->dma.ib_base = 0x10000 / 4; 366 chan->dma.ib_max = (0x02000 / 8) - 1; 367 chan->dma.ib_put = 0; 368 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 369 chan->dma.max = chan->dma.ib_base; 370 break; 371 } 372 373 chan->dma.put = 0; 374 chan->dma.cur = chan->dma.put; 375 chan->dma.free = chan->dma.max - chan->dma.cur; 376 377 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 378 if (ret) 379 return ret; 380 381 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 382 OUT_RING(chan, 0x00000000); 383 384 /* allocate software object class (used for fences on <= nv05) */ 385 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 386 ret = nvif_object_init(&chan->user, 0x006e, 387 NVIF_CLASS_SW_NV04, 388 NULL, 0, &chan->nvsw); 389 if (ret) 390 return ret; 391 392 ret = RING_SPACE(chan, 2); 393 if (ret) 394 return ret; 395 396 BEGIN_NV04(chan, NvSubSw, 0x0000, 1); 397 OUT_RING (chan, chan->nvsw.handle); 398 FIRE_RING (chan); 399 } 400 401 /* initialise synchronisation */ 402 return nouveau_fence(chan->drm)->context_new(chan); 403 } 404 405 int 406 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 407 u32 arg0, u32 arg1, struct nouveau_channel **pchan) 408 { 409 struct nouveau_cli *cli = (void *)device->object.client; 410 bool super; 411 int ret; 412 413 /* hack until fencenv50 is fixed, and agp access relaxed */ 414 super = cli->base.super; 415 cli->base.super = true; 416 417 ret = nouveau_channel_ind(drm, device, arg0, pchan); 418 if (ret) { 419 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); 420 ret = nouveau_channel_dma(drm, device, pchan); 421 if (ret) { 422 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); 423 goto done; 424 } 425 } 426 427 ret = nouveau_channel_init(*pchan, arg0, arg1); 428 if (ret) { 429 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 430 nouveau_channel_del(pchan); 431 } 432 433 done: 434 cli->base.super = super; 435 return ret; 436 } 437