1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25 #include <nvif/os.h> 26 #include <nvif/class.h> 27 #include <nvif/cl0002.h> 28 #include <nvif/cl006b.h> 29 #include <nvif/cl506f.h> 30 #include <nvif/cl906f.h> 31 #include <nvif/cla06f.h> 32 #include <nvif/ioctl.h> 33 34 /*XXX*/ 35 #include <core/client.h> 36 37 #include "nouveau_drv.h" 38 #include "nouveau_dma.h" 39 #include "nouveau_bo.h" 40 #include "nouveau_chan.h" 41 #include "nouveau_fence.h" 42 #include "nouveau_abi16.h" 43 44 MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); 45 int nouveau_vram_pushbuf; 46 module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); 47 48 static int 49 nouveau_channel_killed(struct nvif_notify *ntfy) 50 { 51 struct nouveau_channel *chan = container_of(ntfy, typeof(*chan), kill); 52 struct nouveau_cli *cli = (void *)chan->user.client; 53 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); 54 atomic_set(&chan->killed, 1); 55 return NVIF_NOTIFY_DROP; 56 } 57 58 int 59 nouveau_channel_idle(struct nouveau_channel *chan) 60 { 61 if (likely(chan && chan->fence && !atomic_read(&chan->killed))) { 62 struct nouveau_cli *cli = (void *)chan->user.client; 63 struct nouveau_fence *fence = NULL; 64 int ret; 65 66 ret = nouveau_fence_new(chan, false, &fence); 67 if (!ret) { 68 ret = nouveau_fence_wait(fence, false, false); 69 nouveau_fence_unref(&fence); 70 } 71 72 if (ret) { 73 NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", 74 chan->chid, nvxx_client(&cli->base)->name); 75 return ret; 76 } 77 } 78 return 0; 79 } 80 81 void 82 nouveau_channel_del(struct nouveau_channel **pchan) 83 { 84 struct nouveau_channel *chan = *pchan; 85 if (chan) { 86 if (chan->fence) 87 nouveau_fence(chan->drm)->context_del(chan); 88 nvif_object_fini(&chan->nvsw); 89 nvif_object_fini(&chan->gart); 90 nvif_object_fini(&chan->vram); 91 nvif_notify_fini(&chan->kill); 92 nvif_object_fini(&chan->user); 93 nvif_object_fini(&chan->push.ctxdma); 94 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); 95 nouveau_bo_unmap(chan->push.buffer); 96 if (chan->push.buffer && chan->push.buffer->pin_refcnt) 97 nouveau_bo_unpin(chan->push.buffer); 98 nouveau_bo_ref(NULL, &chan->push.buffer); 99 kfree(chan); 100 } 101 *pchan = NULL; 102 } 103 104 static int 105 nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, 106 u32 size, struct nouveau_channel **pchan) 107 { 108 struct nouveau_cli *cli = (void *)device->object.client; 109 struct nvkm_mmu *mmu = nvxx_mmu(device); 110 struct nv_dma_v0 args = {}; 111 struct nouveau_channel *chan; 112 u32 target; 113 int ret; 114 115 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); 116 if (!chan) 117 return -ENOMEM; 118 119 chan->device = device; 120 chan->drm = drm; 121 atomic_set(&chan->killed, 0); 122 123 /* allocate memory for dma push buffer */ 124 target = TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; 125 if (nouveau_vram_pushbuf) 126 target = TTM_PL_FLAG_VRAM; 127 128 ret = nouveau_bo_new(cli, size, 0, target, 0, 0, NULL, NULL, 129 &chan->push.buffer); 130 if (ret == 0) { 131 ret = nouveau_bo_pin(chan->push.buffer, target, false); 132 if (ret == 0) 133 ret = nouveau_bo_map(chan->push.buffer); 134 } 135 136 if (ret) { 137 nouveau_channel_del(pchan); 138 return ret; 139 } 140 141 /* create dma object covering the *entire* memory space that the 142 * pushbuf lives in, this is because the GEM code requires that 143 * we be able to call out to other (indirect) push buffers 144 */ 145 chan->push.vma.offset = chan->push.buffer->bo.offset; 146 147 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 148 ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm, 149 &chan->push.vma); 150 if (ret) { 151 nouveau_channel_del(pchan); 152 return ret; 153 } 154 155 args.target = NV_DMA_V0_TARGET_VM; 156 args.access = NV_DMA_V0_ACCESS_VM; 157 args.start = 0; 158 args.limit = cli->vm->mmu->limit - 1; 159 } else 160 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { 161 if (device->info.family == NV_DEVICE_INFO_V0_TNT) { 162 /* nv04 vram pushbuf hack, retarget to its location in 163 * the framebuffer bar rather than direct vram access.. 164 * nfi why this exists, it came from the -nv ddx. 165 */ 166 args.target = NV_DMA_V0_TARGET_PCI; 167 args.access = NV_DMA_V0_ACCESS_RDWR; 168 args.start = nvxx_device(device)->func-> 169 resource_addr(nvxx_device(device), 1); 170 args.limit = args.start + device->info.ram_user - 1; 171 } else { 172 args.target = NV_DMA_V0_TARGET_VRAM; 173 args.access = NV_DMA_V0_ACCESS_RDWR; 174 args.start = 0; 175 args.limit = device->info.ram_user - 1; 176 } 177 } else { 178 if (chan->drm->agp.bridge) { 179 args.target = NV_DMA_V0_TARGET_AGP; 180 args.access = NV_DMA_V0_ACCESS_RDWR; 181 args.start = chan->drm->agp.base; 182 args.limit = chan->drm->agp.base + 183 chan->drm->agp.size - 1; 184 } else { 185 args.target = NV_DMA_V0_TARGET_VM; 186 args.access = NV_DMA_V0_ACCESS_RDWR; 187 args.start = 0; 188 args.limit = mmu->limit - 1; 189 } 190 } 191 192 ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, 193 &args, sizeof(args), &chan->push.ctxdma); 194 if (ret) { 195 nouveau_channel_del(pchan); 196 return ret; 197 } 198 199 return 0; 200 } 201 202 static int 203 nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, 204 u32 engine, struct nouveau_channel **pchan) 205 { 206 static const u16 oclasses[] = { PASCAL_CHANNEL_GPFIFO_A, 207 MAXWELL_CHANNEL_GPFIFO_A, 208 KEPLER_CHANNEL_GPFIFO_B, 209 KEPLER_CHANNEL_GPFIFO_A, 210 FERMI_CHANNEL_GPFIFO, 211 G82_CHANNEL_GPFIFO, 212 NV50_CHANNEL_GPFIFO, 213 0 }; 214 const u16 *oclass = oclasses; 215 union { 216 struct nv50_channel_gpfifo_v0 nv50; 217 struct fermi_channel_gpfifo_v0 fermi; 218 struct kepler_channel_gpfifo_a_v0 kepler; 219 } args; 220 struct nouveau_channel *chan; 221 u32 size; 222 int ret; 223 224 /* allocate dma push buffer */ 225 ret = nouveau_channel_prep(drm, device, 0x12000, &chan); 226 *pchan = chan; 227 if (ret) 228 return ret; 229 230 /* create channel object */ 231 do { 232 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { 233 args.kepler.version = 0; 234 args.kepler.engines = engine; 235 args.kepler.ilength = 0x02000; 236 args.kepler.ioffset = 0x10000 + chan->push.vma.offset; 237 args.kepler.vm = 0; 238 size = sizeof(args.kepler); 239 } else 240 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { 241 args.fermi.version = 0; 242 args.fermi.ilength = 0x02000; 243 args.fermi.ioffset = 0x10000 + chan->push.vma.offset; 244 args.fermi.vm = 0; 245 size = sizeof(args.fermi); 246 } else { 247 args.nv50.version = 0; 248 args.nv50.ilength = 0x02000; 249 args.nv50.ioffset = 0x10000 + chan->push.vma.offset; 250 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma); 251 args.nv50.vm = 0; 252 size = sizeof(args.nv50); 253 } 254 255 ret = nvif_object_init(&device->object, 0, *oclass++, 256 &args, size, &chan->user); 257 if (ret == 0) { 258 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) 259 chan->chid = args.kepler.chid; 260 else 261 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) 262 chan->chid = args.fermi.chid; 263 else 264 chan->chid = args.nv50.chid; 265 return ret; 266 } 267 } while (*oclass); 268 269 nouveau_channel_del(pchan); 270 return ret; 271 } 272 273 static int 274 nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, 275 struct nouveau_channel **pchan) 276 { 277 static const u16 oclasses[] = { NV40_CHANNEL_DMA, 278 NV17_CHANNEL_DMA, 279 NV10_CHANNEL_DMA, 280 NV03_CHANNEL_DMA, 281 0 }; 282 const u16 *oclass = oclasses; 283 struct nv03_channel_dma_v0 args; 284 struct nouveau_channel *chan; 285 int ret; 286 287 /* allocate dma push buffer */ 288 ret = nouveau_channel_prep(drm, device, 0x10000, &chan); 289 *pchan = chan; 290 if (ret) 291 return ret; 292 293 /* create channel object */ 294 args.version = 0; 295 args.pushbuf = nvif_handle(&chan->push.ctxdma); 296 args.offset = chan->push.vma.offset; 297 298 do { 299 ret = nvif_object_init(&device->object, 0, *oclass++, 300 &args, sizeof(args), &chan->user); 301 if (ret == 0) { 302 chan->chid = args.chid; 303 return ret; 304 } 305 } while (ret && *oclass); 306 307 nouveau_channel_del(pchan); 308 return ret; 309 } 310 311 static int 312 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) 313 { 314 struct nvif_device *device = chan->device; 315 struct nouveau_cli *cli = (void *)chan->user.client; 316 struct nouveau_drm *drm = chan->drm; 317 struct nvkm_mmu *mmu = nvxx_mmu(device); 318 struct nv_dma_v0 args = {}; 319 int ret, i; 320 321 nvif_object_map(&chan->user); 322 323 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { 324 ret = nvif_notify_init(&chan->user, nouveau_channel_killed, 325 true, NV906F_V0_NTFY_KILLED, 326 NULL, 0, 0, &chan->kill); 327 if (ret == 0) 328 ret = nvif_notify_get(&chan->kill); 329 if (ret) { 330 NV_ERROR(drm, "Failed to request channel kill " 331 "notification: %d\n", ret); 332 return ret; 333 } 334 } 335 336 /* allocate dma objects to cover all allowed vram, and gart */ 337 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { 338 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 339 args.target = NV_DMA_V0_TARGET_VM; 340 args.access = NV_DMA_V0_ACCESS_VM; 341 args.start = 0; 342 args.limit = cli->vm->mmu->limit - 1; 343 } else { 344 args.target = NV_DMA_V0_TARGET_VRAM; 345 args.access = NV_DMA_V0_ACCESS_RDWR; 346 args.start = 0; 347 args.limit = device->info.ram_user - 1; 348 } 349 350 ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, 351 &args, sizeof(args), &chan->vram); 352 if (ret) 353 return ret; 354 355 if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { 356 args.target = NV_DMA_V0_TARGET_VM; 357 args.access = NV_DMA_V0_ACCESS_VM; 358 args.start = 0; 359 args.limit = cli->vm->mmu->limit - 1; 360 } else 361 if (chan->drm->agp.bridge) { 362 args.target = NV_DMA_V0_TARGET_AGP; 363 args.access = NV_DMA_V0_ACCESS_RDWR; 364 args.start = chan->drm->agp.base; 365 args.limit = chan->drm->agp.base + 366 chan->drm->agp.size - 1; 367 } else { 368 args.target = NV_DMA_V0_TARGET_VM; 369 args.access = NV_DMA_V0_ACCESS_RDWR; 370 args.start = 0; 371 args.limit = mmu->limit - 1; 372 } 373 374 ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, 375 &args, sizeof(args), &chan->gart); 376 if (ret) 377 return ret; 378 } 379 380 /* initialise dma tracking parameters */ 381 switch (chan->user.oclass & 0x00ff) { 382 case 0x006b: 383 case 0x006e: 384 chan->user_put = 0x40; 385 chan->user_get = 0x44; 386 chan->dma.max = (0x10000 / 4) - 2; 387 break; 388 default: 389 chan->user_put = 0x40; 390 chan->user_get = 0x44; 391 chan->user_get_hi = 0x60; 392 chan->dma.ib_base = 0x10000 / 4; 393 chan->dma.ib_max = (0x02000 / 8) - 1; 394 chan->dma.ib_put = 0; 395 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; 396 chan->dma.max = chan->dma.ib_base; 397 break; 398 } 399 400 chan->dma.put = 0; 401 chan->dma.cur = chan->dma.put; 402 chan->dma.free = chan->dma.max - chan->dma.cur; 403 404 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); 405 if (ret) 406 return ret; 407 408 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 409 OUT_RING(chan, 0x00000000); 410 411 /* allocate software object class (used for fences on <= nv05) */ 412 if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { 413 ret = nvif_object_init(&chan->user, 0x006e, 414 NVIF_CLASS_SW_NV04, 415 NULL, 0, &chan->nvsw); 416 if (ret) 417 return ret; 418 419 ret = RING_SPACE(chan, 2); 420 if (ret) 421 return ret; 422 423 BEGIN_NV04(chan, NvSubSw, 0x0000, 1); 424 OUT_RING (chan, chan->nvsw.handle); 425 FIRE_RING (chan); 426 } 427 428 /* initialise synchronisation */ 429 return nouveau_fence(chan->drm)->context_new(chan); 430 } 431 432 int 433 nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, 434 u32 arg0, u32 arg1, struct nouveau_channel **pchan) 435 { 436 struct nouveau_cli *cli = (void *)device->object.client; 437 bool super; 438 int ret; 439 440 /* hack until fencenv50 is fixed, and agp access relaxed */ 441 super = cli->base.super; 442 cli->base.super = true; 443 444 ret = nouveau_channel_ind(drm, device, arg0, pchan); 445 if (ret) { 446 NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); 447 ret = nouveau_channel_dma(drm, device, pchan); 448 if (ret) { 449 NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); 450 goto done; 451 } 452 } 453 454 ret = nouveau_channel_init(*pchan, arg0, arg1); 455 if (ret) { 456 NV_PRINTK(err, cli, "channel failed to initialise, %d\n", ret); 457 nouveau_channel_del(pchan); 458 } 459 460 done: 461 cli->base.super = super; 462 return ret; 463 } 464