1 /*
2  * Copyright 2007 Dave Airlied
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  */
24 /*
25  * Authors: Dave Airlied <airlied@linux.ie>
26  *	    Ben Skeggs   <darktama@iinet.net.au>
27  *	    Jeremy Kolb  <jkolb@brandeis.edu>
28  */
29 
30 #include <linux/dma-mapping.h>
31 
32 #include "nouveau_drv.h"
33 #include "nouveau_chan.h"
34 #include "nouveau_fence.h"
35 
36 #include "nouveau_bo.h"
37 #include "nouveau_ttm.h"
38 #include "nouveau_gem.h"
39 #include "nouveau_mem.h"
40 #include "nouveau_vmm.h"
41 
42 #include <nvif/class.h>
43 #include <nvif/if500b.h>
44 #include <nvif/if900b.h>
45 
46 static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
47 			       struct ttm_resource *reg);
48 static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
49 
50 /*
51  * NV10-NV40 tiling helpers
52  */
53 
54 static void
55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
56 			   u32 addr, u32 size, u32 pitch, u32 flags)
57 {
58 	struct nouveau_drm *drm = nouveau_drm(dev);
59 	int i = reg - drm->tile.reg;
60 	struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
61 	struct nvkm_fb_tile *tile = &fb->tile.region[i];
62 
63 	nouveau_fence_unref(&reg->fence);
64 
65 	if (tile->pitch)
66 		nvkm_fb_tile_fini(fb, i, tile);
67 
68 	if (pitch)
69 		nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
70 
71 	nvkm_fb_tile_prog(fb, i, tile);
72 }
73 
74 static struct nouveau_drm_tile *
75 nv10_bo_get_tile_region(struct drm_device *dev, int i)
76 {
77 	struct nouveau_drm *drm = nouveau_drm(dev);
78 	struct nouveau_drm_tile *tile = &drm->tile.reg[i];
79 
80 	spin_lock(&drm->tile.lock);
81 
82 	if (!tile->used &&
83 	    (!tile->fence || nouveau_fence_done(tile->fence)))
84 		tile->used = true;
85 	else
86 		tile = NULL;
87 
88 	spin_unlock(&drm->tile.lock);
89 	return tile;
90 }
91 
92 static void
93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 			struct dma_fence *fence)
95 {
96 	struct nouveau_drm *drm = nouveau_drm(dev);
97 
98 	if (tile) {
99 		spin_lock(&drm->tile.lock);
100 		tile->fence = (struct nouveau_fence *)dma_fence_get(fence);
101 		tile->used = false;
102 		spin_unlock(&drm->tile.lock);
103 	}
104 }
105 
106 static struct nouveau_drm_tile *
107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
108 		   u32 size, u32 pitch, u32 zeta)
109 {
110 	struct nouveau_drm *drm = nouveau_drm(dev);
111 	struct nvkm_fb *fb = nvxx_fb(&drm->client.device);
112 	struct nouveau_drm_tile *tile, *found = NULL;
113 	int i;
114 
115 	for (i = 0; i < fb->tile.regions; i++) {
116 		tile = nv10_bo_get_tile_region(dev, i);
117 
118 		if (pitch && !found) {
119 			found = tile;
120 			continue;
121 
122 		} else if (tile && fb->tile.region[i].pitch) {
123 			/* Kill an unused tile region. */
124 			nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
125 		}
126 
127 		nv10_bo_put_tile_region(dev, tile, NULL);
128 	}
129 
130 	if (found)
131 		nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta);
132 	return found;
133 }
134 
135 static void
136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
137 {
138 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
139 	struct drm_device *dev = drm->dev;
140 	struct nouveau_bo *nvbo = nouveau_bo(bo);
141 
142 	WARN_ON(nvbo->bo.pin_count > 0);
143 	nouveau_bo_del_io_reserve_lru(bo);
144 	nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
145 
146 	/*
147 	 * If nouveau_bo_new() allocated this buffer, the GEM object was never
148 	 * initialized, so don't attempt to release it.
149 	 */
150 	if (bo->base.dev)
151 		drm_gem_object_release(&bo->base);
152 	else
153 		dma_resv_fini(&bo->base._resv);
154 
155 	kfree(nvbo);
156 }
157 
158 static inline u64
159 roundup_64(u64 x, u32 y)
160 {
161 	x += y - 1;
162 	do_div(x, y);
163 	return x * y;
164 }
165 
166 static void
167 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size)
168 {
169 	struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
170 	struct nvif_device *device = &drm->client.device;
171 
172 	if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
173 		if (nvbo->mode) {
174 			if (device->info.chipset >= 0x40) {
175 				*align = 65536;
176 				*size = roundup_64(*size, 64 * nvbo->mode);
177 
178 			} else if (device->info.chipset >= 0x30) {
179 				*align = 32768;
180 				*size = roundup_64(*size, 64 * nvbo->mode);
181 
182 			} else if (device->info.chipset >= 0x20) {
183 				*align = 16384;
184 				*size = roundup_64(*size, 64 * nvbo->mode);
185 
186 			} else if (device->info.chipset >= 0x10) {
187 				*align = 16384;
188 				*size = roundup_64(*size, 32 * nvbo->mode);
189 			}
190 		}
191 	} else {
192 		*size = roundup_64(*size, (1 << nvbo->page));
193 		*align = max((1 <<  nvbo->page), *align);
194 	}
195 
196 	*size = roundup_64(*size, PAGE_SIZE);
197 }
198 
199 struct nouveau_bo *
200 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain,
201 		 u32 tile_mode, u32 tile_flags)
202 {
203 	struct nouveau_drm *drm = cli->drm;
204 	struct nouveau_bo *nvbo;
205 	struct nvif_mmu *mmu = &cli->mmu;
206 	struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm;
207 	int i, pi = -1;
208 
209 	if (!*size) {
210 		NV_WARN(drm, "skipped size %016llx\n", *size);
211 		return ERR_PTR(-EINVAL);
212 	}
213 
214 	nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
215 	if (!nvbo)
216 		return ERR_PTR(-ENOMEM);
217 	INIT_LIST_HEAD(&nvbo->head);
218 	INIT_LIST_HEAD(&nvbo->entry);
219 	INIT_LIST_HEAD(&nvbo->vma_list);
220 	nvbo->bo.bdev = &drm->ttm.bdev;
221 
222 	/* This is confusing, and doesn't actually mean we want an uncached
223 	 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated
224 	 * into in nouveau_gem_new().
225 	 */
226 	if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) {
227 		/* Determine if we can get a cache-coherent map, forcing
228 		 * uncached mapping if we can't.
229 		 */
230 		if (!nouveau_drm_use_coherent_gpu_mapping(drm))
231 			nvbo->force_coherent = true;
232 	}
233 
234 	if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) {
235 		nvbo->kind = (tile_flags & 0x0000ff00) >> 8;
236 		if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
237 			kfree(nvbo);
238 			return ERR_PTR(-EINVAL);
239 		}
240 
241 		nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind;
242 	} else
243 	if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
244 		nvbo->kind = (tile_flags & 0x00007f00) >> 8;
245 		nvbo->comp = (tile_flags & 0x00030000) >> 16;
246 		if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) {
247 			kfree(nvbo);
248 			return ERR_PTR(-EINVAL);
249 		}
250 	} else {
251 		nvbo->zeta = (tile_flags & 0x00000007);
252 	}
253 	nvbo->mode = tile_mode;
254 	nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG);
255 
256 	/* Determine the desirable target GPU page size for the buffer. */
257 	for (i = 0; i < vmm->page_nr; i++) {
258 		/* Because we cannot currently allow VMM maps to fail
259 		 * during buffer migration, we need to determine page
260 		 * size for the buffer up-front, and pre-allocate its
261 		 * page tables.
262 		 *
263 		 * Skip page sizes that can't support needed domains.
264 		 */
265 		if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE &&
266 		    (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram)
267 			continue;
268 		if ((domain & NOUVEAU_GEM_DOMAIN_GART) &&
269 		    (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT))
270 			continue;
271 
272 		/* Select this page size if it's the first that supports
273 		 * the potential memory domains, or when it's compatible
274 		 * with the requested compression settings.
275 		 */
276 		if (pi < 0 || !nvbo->comp || vmm->page[i].comp)
277 			pi = i;
278 
279 		/* Stop once the buffer is larger than the current page size. */
280 		if (*size >= 1ULL << vmm->page[i].shift)
281 			break;
282 	}
283 
284 	if (WARN_ON(pi < 0)) {
285 		kfree(nvbo);
286 		return ERR_PTR(-EINVAL);
287 	}
288 
289 	/* Disable compression if suitable settings couldn't be found. */
290 	if (nvbo->comp && !vmm->page[pi].comp) {
291 		if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100)
292 			nvbo->kind = mmu->kind[nvbo->kind];
293 		nvbo->comp = 0;
294 	}
295 	nvbo->page = vmm->page[pi].shift;
296 
297 	nouveau_bo_fixup_align(nvbo, align, size);
298 
299 	return nvbo;
300 }
301 
302 int
303 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain,
304 		struct sg_table *sg, struct dma_resv *robj)
305 {
306 	int type = sg ? ttm_bo_type_sg : ttm_bo_type_device;
307 	int ret;
308 
309 	nouveau_bo_placement_set(nvbo, domain, 0);
310 	INIT_LIST_HEAD(&nvbo->io_reserve_lru);
311 
312 	ret = ttm_bo_init_validate(nvbo->bo.bdev, &nvbo->bo, type,
313 				   &nvbo->placement, align >> PAGE_SHIFT, false,
314 				   sg, robj, nouveau_bo_del_ttm);
315 	if (ret) {
316 		/* ttm will call nouveau_bo_del_ttm if it fails.. */
317 		return ret;
318 	}
319 
320 	return 0;
321 }
322 
323 int
324 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align,
325 	       uint32_t domain, uint32_t tile_mode, uint32_t tile_flags,
326 	       struct sg_table *sg, struct dma_resv *robj,
327 	       struct nouveau_bo **pnvbo)
328 {
329 	struct nouveau_bo *nvbo;
330 	int ret;
331 
332 	nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode,
333 				tile_flags);
334 	if (IS_ERR(nvbo))
335 		return PTR_ERR(nvbo);
336 
337 	nvbo->bo.base.size = size;
338 	dma_resv_init(&nvbo->bo.base._resv);
339 	drm_vma_node_reset(&nvbo->bo.base.vma_node);
340 
341 	ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj);
342 	if (ret)
343 		return ret;
344 
345 	*pnvbo = nvbo;
346 	return 0;
347 }
348 
349 static void
350 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain)
351 {
352 	*n = 0;
353 
354 	if (domain & NOUVEAU_GEM_DOMAIN_VRAM) {
355 		pl[*n].mem_type = TTM_PL_VRAM;
356 		pl[*n].flags = 0;
357 		(*n)++;
358 	}
359 	if (domain & NOUVEAU_GEM_DOMAIN_GART) {
360 		pl[*n].mem_type = TTM_PL_TT;
361 		pl[*n].flags = 0;
362 		(*n)++;
363 	}
364 	if (domain & NOUVEAU_GEM_DOMAIN_CPU) {
365 		pl[*n].mem_type = TTM_PL_SYSTEM;
366 		pl[(*n)++].flags = 0;
367 	}
368 }
369 
370 static void
371 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain)
372 {
373 	struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
374 	u64 vram_size = drm->client.device.info.ram_size;
375 	unsigned i, fpfn, lpfn;
376 
377 	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
378 	    nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) &&
379 	    nvbo->bo.base.size < vram_size / 4) {
380 		/*
381 		 * Make sure that the color and depth buffers are handled
382 		 * by independent memory controller units. Up to a 9x
383 		 * speed up when alpha-blending and depth-test are enabled
384 		 * at the same time.
385 		 */
386 		if (nvbo->zeta) {
387 			fpfn = (vram_size / 2) >> PAGE_SHIFT;
388 			lpfn = ~0;
389 		} else {
390 			fpfn = 0;
391 			lpfn = (vram_size / 2) >> PAGE_SHIFT;
392 		}
393 		for (i = 0; i < nvbo->placement.num_placement; ++i) {
394 			nvbo->placements[i].fpfn = fpfn;
395 			nvbo->placements[i].lpfn = lpfn;
396 		}
397 		for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
398 			nvbo->busy_placements[i].fpfn = fpfn;
399 			nvbo->busy_placements[i].lpfn = lpfn;
400 		}
401 	}
402 }
403 
404 void
405 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain,
406 			 uint32_t busy)
407 {
408 	struct ttm_placement *pl = &nvbo->placement;
409 
410 	pl->placement = nvbo->placements;
411 	set_placement_list(nvbo->placements, &pl->num_placement, domain);
412 
413 	pl->busy_placement = nvbo->busy_placements;
414 	set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
415 			   domain | busy);
416 
417 	set_placement_range(nvbo, domain);
418 }
419 
420 int
421 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig)
422 {
423 	struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
424 	struct ttm_buffer_object *bo = &nvbo->bo;
425 	bool force = false, evict = false;
426 	int ret;
427 
428 	ret = ttm_bo_reserve(bo, false, false, NULL);
429 	if (ret)
430 		return ret;
431 
432 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
433 	    domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) {
434 		if (!nvbo->contig) {
435 			nvbo->contig = true;
436 			force = true;
437 			evict = true;
438 		}
439 	}
440 
441 	if (nvbo->bo.pin_count) {
442 		bool error = evict;
443 
444 		switch (bo->resource->mem_type) {
445 		case TTM_PL_VRAM:
446 			error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM);
447 			break;
448 		case TTM_PL_TT:
449 			error |= !(domain & NOUVEAU_GEM_DOMAIN_GART);
450 			break;
451 		default:
452 			break;
453 		}
454 
455 		if (error) {
456 			NV_ERROR(drm, "bo %p pinned elsewhere: "
457 				      "0x%08x vs 0x%08x\n", bo,
458 				 bo->resource->mem_type, domain);
459 			ret = -EBUSY;
460 		}
461 		ttm_bo_pin(&nvbo->bo);
462 		goto out;
463 	}
464 
465 	if (evict) {
466 		nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
467 		ret = nouveau_bo_validate(nvbo, false, false);
468 		if (ret)
469 			goto out;
470 	}
471 
472 	nouveau_bo_placement_set(nvbo, domain, 0);
473 	ret = nouveau_bo_validate(nvbo, false, false);
474 	if (ret)
475 		goto out;
476 
477 	ttm_bo_pin(&nvbo->bo);
478 
479 	switch (bo->resource->mem_type) {
480 	case TTM_PL_VRAM:
481 		drm->gem.vram_available -= bo->base.size;
482 		break;
483 	case TTM_PL_TT:
484 		drm->gem.gart_available -= bo->base.size;
485 		break;
486 	default:
487 		break;
488 	}
489 
490 out:
491 	if (force && ret)
492 		nvbo->contig = false;
493 	ttm_bo_unreserve(bo);
494 	return ret;
495 }
496 
497 int
498 nouveau_bo_unpin(struct nouveau_bo *nvbo)
499 {
500 	struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
501 	struct ttm_buffer_object *bo = &nvbo->bo;
502 	int ret;
503 
504 	ret = ttm_bo_reserve(bo, false, false, NULL);
505 	if (ret)
506 		return ret;
507 
508 	ttm_bo_unpin(&nvbo->bo);
509 	if (!nvbo->bo.pin_count) {
510 		switch (bo->resource->mem_type) {
511 		case TTM_PL_VRAM:
512 			drm->gem.vram_available += bo->base.size;
513 			break;
514 		case TTM_PL_TT:
515 			drm->gem.gart_available += bo->base.size;
516 			break;
517 		default:
518 			break;
519 		}
520 	}
521 
522 	ttm_bo_unreserve(bo);
523 	return 0;
524 }
525 
526 int
527 nouveau_bo_map(struct nouveau_bo *nvbo)
528 {
529 	int ret;
530 
531 	ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL);
532 	if (ret)
533 		return ret;
534 
535 	ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.resource->num_pages, &nvbo->kmap);
536 
537 	ttm_bo_unreserve(&nvbo->bo);
538 	return ret;
539 }
540 
541 void
542 nouveau_bo_unmap(struct nouveau_bo *nvbo)
543 {
544 	if (!nvbo)
545 		return;
546 
547 	ttm_bo_kunmap(&nvbo->kmap);
548 }
549 
550 void
551 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
552 {
553 	struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
554 	struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
555 	int i, j;
556 
557 	if (!ttm_dma || !ttm_dma->dma_address)
558 		return;
559 	if (!ttm_dma->pages) {
560 		NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
561 		return;
562 	}
563 
564 	/* Don't waste time looping if the object is coherent */
565 	if (nvbo->force_coherent)
566 		return;
567 
568 	i = 0;
569 	while (i < ttm_dma->num_pages) {
570 		struct page *p = ttm_dma->pages[i];
571 		size_t num_pages = 1;
572 
573 		for (j = i + 1; j < ttm_dma->num_pages; ++j) {
574 			if (++p != ttm_dma->pages[j])
575 				break;
576 
577 			++num_pages;
578 		}
579 		dma_sync_single_for_device(drm->dev->dev,
580 					   ttm_dma->dma_address[i],
581 					   num_pages * PAGE_SIZE, DMA_TO_DEVICE);
582 		i += num_pages;
583 	}
584 }
585 
586 void
587 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
588 {
589 	struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
590 	struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm;
591 	int i, j;
592 
593 	if (!ttm_dma || !ttm_dma->dma_address)
594 		return;
595 	if (!ttm_dma->pages) {
596 		NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma);
597 		return;
598 	}
599 
600 	/* Don't waste time looping if the object is coherent */
601 	if (nvbo->force_coherent)
602 		return;
603 
604 	i = 0;
605 	while (i < ttm_dma->num_pages) {
606 		struct page *p = ttm_dma->pages[i];
607 		size_t num_pages = 1;
608 
609 		for (j = i + 1; j < ttm_dma->num_pages; ++j) {
610 			if (++p != ttm_dma->pages[j])
611 				break;
612 
613 			++num_pages;
614 		}
615 
616 		dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i],
617 					num_pages * PAGE_SIZE, DMA_FROM_DEVICE);
618 		i += num_pages;
619 	}
620 }
621 
622 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo)
623 {
624 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
625 	struct nouveau_bo *nvbo = nouveau_bo(bo);
626 
627 	mutex_lock(&drm->ttm.io_reserve_mutex);
628 	list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru);
629 	mutex_unlock(&drm->ttm.io_reserve_mutex);
630 }
631 
632 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo)
633 {
634 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
635 	struct nouveau_bo *nvbo = nouveau_bo(bo);
636 
637 	mutex_lock(&drm->ttm.io_reserve_mutex);
638 	list_del_init(&nvbo->io_reserve_lru);
639 	mutex_unlock(&drm->ttm.io_reserve_mutex);
640 }
641 
642 int
643 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
644 		    bool no_wait_gpu)
645 {
646 	struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
647 	int ret;
648 
649 	ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx);
650 	if (ret)
651 		return ret;
652 
653 	nouveau_bo_sync_for_device(nvbo);
654 
655 	return 0;
656 }
657 
658 void
659 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
660 {
661 	bool is_iomem;
662 	u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
663 
664 	mem += index;
665 
666 	if (is_iomem)
667 		iowrite16_native(val, (void __force __iomem *)mem);
668 	else
669 		*mem = val;
670 }
671 
672 u32
673 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
674 {
675 	bool is_iomem;
676 	u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
677 
678 	mem += index;
679 
680 	if (is_iomem)
681 		return ioread32_native((void __force __iomem *)mem);
682 	else
683 		return *mem;
684 }
685 
686 void
687 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
688 {
689 	bool is_iomem;
690 	u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
691 
692 	mem += index;
693 
694 	if (is_iomem)
695 		iowrite32_native(val, (void __force __iomem *)mem);
696 	else
697 		*mem = val;
698 }
699 
700 static struct ttm_tt *
701 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags)
702 {
703 #if IS_ENABLED(CONFIG_AGP)
704 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
705 
706 	if (drm->agp.bridge) {
707 		return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags);
708 	}
709 #endif
710 
711 	return nouveau_sgdma_create_ttm(bo, page_flags);
712 }
713 
714 static int
715 nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
716 		    struct ttm_resource *reg)
717 {
718 #if IS_ENABLED(CONFIG_AGP)
719 	struct nouveau_drm *drm = nouveau_bdev(bdev);
720 #endif
721 	if (!reg)
722 		return -EINVAL;
723 #if IS_ENABLED(CONFIG_AGP)
724 	if (drm->agp.bridge)
725 		return ttm_agp_bind(ttm, reg);
726 #endif
727 	return nouveau_sgdma_bind(bdev, ttm, reg);
728 }
729 
730 static void
731 nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
732 {
733 #if IS_ENABLED(CONFIG_AGP)
734 	struct nouveau_drm *drm = nouveau_bdev(bdev);
735 
736 	if (drm->agp.bridge) {
737 		ttm_agp_unbind(ttm);
738 		return;
739 	}
740 #endif
741 	nouveau_sgdma_unbind(bdev, ttm);
742 }
743 
744 static void
745 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
746 {
747 	struct nouveau_bo *nvbo = nouveau_bo(bo);
748 
749 	switch (bo->resource->mem_type) {
750 	case TTM_PL_VRAM:
751 		nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART,
752 					 NOUVEAU_GEM_DOMAIN_CPU);
753 		break;
754 	default:
755 		nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0);
756 		break;
757 	}
758 
759 	*pl = nvbo->placement;
760 }
761 
762 static int
763 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
764 		     struct ttm_resource *reg)
765 {
766 	struct nouveau_mem *old_mem = nouveau_mem(bo->resource);
767 	struct nouveau_mem *new_mem = nouveau_mem(reg);
768 	struct nvif_vmm *vmm = &drm->client.vmm.vmm;
769 	int ret;
770 
771 	ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0,
772 			   old_mem->mem.size, &old_mem->vma[0]);
773 	if (ret)
774 		return ret;
775 
776 	ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0,
777 			   new_mem->mem.size, &old_mem->vma[1]);
778 	if (ret)
779 		goto done;
780 
781 	ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]);
782 	if (ret)
783 		goto done;
784 
785 	ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]);
786 done:
787 	if (ret) {
788 		nvif_vmm_put(vmm, &old_mem->vma[1]);
789 		nvif_vmm_put(vmm, &old_mem->vma[0]);
790 	}
791 	return 0;
792 }
793 
794 static int
795 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict,
796 		     struct ttm_operation_ctx *ctx,
797 		     struct ttm_resource *new_reg)
798 {
799 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
800 	struct nouveau_channel *chan = drm->ttm.chan;
801 	struct nouveau_cli *cli = (void *)chan->user.client;
802 	struct nouveau_fence *fence;
803 	int ret;
804 
805 	/* create temporary vmas for the transfer and attach them to the
806 	 * old nvkm_mem node, these will get cleaned up after ttm has
807 	 * destroyed the ttm_resource
808 	 */
809 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
810 		ret = nouveau_bo_move_prep(drm, bo, new_reg);
811 		if (ret)
812 			return ret;
813 	}
814 
815 	if (drm_drv_uses_atomic_modeset(drm->dev))
816 		mutex_lock(&cli->mutex);
817 	else
818 		mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
819 	ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible);
820 	if (ret == 0) {
821 		ret = drm->ttm.move(chan, bo, bo->resource, new_reg);
822 		if (ret == 0) {
823 			ret = nouveau_fence_new(chan, false, &fence);
824 			if (ret == 0) {
825 				ret = ttm_bo_move_accel_cleanup(bo,
826 								&fence->base,
827 								evict, false,
828 								new_reg);
829 				nouveau_fence_unref(&fence);
830 			}
831 		}
832 	}
833 	mutex_unlock(&cli->mutex);
834 	return ret;
835 }
836 
837 void
838 nouveau_bo_move_init(struct nouveau_drm *drm)
839 {
840 	static const struct _method_table {
841 		const char *name;
842 		int engine;
843 		s32 oclass;
844 		int (*exec)(struct nouveau_channel *,
845 			    struct ttm_buffer_object *,
846 			    struct ttm_resource *, struct ttm_resource *);
847 		int (*init)(struct nouveau_channel *, u32 handle);
848 	} _methods[] = {
849 		{  "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },
850 		{  "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init },
851 		{  "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init },
852 		{  "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init },
853 		{  "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init },
854 		{  "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init },
855 		{  "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init },
856 		{  "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init },
857 		{  "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init },
858 		{  "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init },
859 		{  "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init },
860 		{  "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
861 		{  "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
862 		{ "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
863 		{ "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
864 		{  "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
865 		{ "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
866 		{  "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
867 		{  "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
868 		{  "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
869 		{},
870 	};
871 	const struct _method_table *mthd = _methods;
872 	const char *name = "CPU";
873 	int ret;
874 
875 	do {
876 		struct nouveau_channel *chan;
877 
878 		if (mthd->engine)
879 			chan = drm->cechan;
880 		else
881 			chan = drm->channel;
882 		if (chan == NULL)
883 			continue;
884 
885 		ret = nvif_object_ctor(&chan->user, "ttmBoMove",
886 				       mthd->oclass | (mthd->engine << 16),
887 				       mthd->oclass, NULL, 0,
888 				       &drm->ttm.copy);
889 		if (ret == 0) {
890 			ret = mthd->init(chan, drm->ttm.copy.handle);
891 			if (ret) {
892 				nvif_object_dtor(&drm->ttm.copy);
893 				continue;
894 			}
895 
896 			drm->ttm.move = mthd->exec;
897 			drm->ttm.chan = chan;
898 			name = mthd->name;
899 			break;
900 		}
901 	} while ((++mthd)->exec);
902 
903 	NV_INFO(drm, "MM: using %s for buffer copies\n", name);
904 }
905 
906 static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo,
907 				 struct ttm_resource *new_reg)
908 {
909 	struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL;
910 	struct nouveau_bo *nvbo = nouveau_bo(bo);
911 	struct nouveau_vma *vma;
912 
913 	/* ttm can now (stupidly) pass the driver bos it didn't create... */
914 	if (bo->destroy != nouveau_bo_del_ttm)
915 		return;
916 
917 	nouveau_bo_del_io_reserve_lru(bo);
918 
919 	if (mem && new_reg->mem_type != TTM_PL_SYSTEM &&
920 	    mem->mem.page == nvbo->page) {
921 		list_for_each_entry(vma, &nvbo->vma_list, head) {
922 			nouveau_vma_map(vma, mem);
923 		}
924 	} else {
925 		list_for_each_entry(vma, &nvbo->vma_list, head) {
926 			WARN_ON(ttm_bo_wait(bo, false, false));
927 			nouveau_vma_unmap(vma);
928 		}
929 	}
930 
931 	if (new_reg)
932 		nvbo->offset = (new_reg->start << PAGE_SHIFT);
933 
934 }
935 
936 static int
937 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg,
938 		   struct nouveau_drm_tile **new_tile)
939 {
940 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
941 	struct drm_device *dev = drm->dev;
942 	struct nouveau_bo *nvbo = nouveau_bo(bo);
943 	u64 offset = new_reg->start << PAGE_SHIFT;
944 
945 	*new_tile = NULL;
946 	if (new_reg->mem_type != TTM_PL_VRAM)
947 		return 0;
948 
949 	if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
950 		*new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size,
951 					       nvbo->mode, nvbo->zeta);
952 	}
953 
954 	return 0;
955 }
956 
957 static void
958 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
959 		      struct nouveau_drm_tile *new_tile,
960 		      struct nouveau_drm_tile **old_tile)
961 {
962 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
963 	struct drm_device *dev = drm->dev;
964 	struct dma_fence *fence;
965 	int ret;
966 
967 	ret = dma_resv_get_singleton(bo->base.resv, DMA_RESV_USAGE_WRITE,
968 				     &fence);
969 	if (ret)
970 		dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_WRITE,
971 				      false, MAX_SCHEDULE_TIMEOUT);
972 
973 	nv10_bo_put_tile_region(dev, *old_tile, fence);
974 	*old_tile = new_tile;
975 }
976 
977 static int
978 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict,
979 		struct ttm_operation_ctx *ctx,
980 		struct ttm_resource *new_reg,
981 		struct ttm_place *hop)
982 {
983 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
984 	struct nouveau_bo *nvbo = nouveau_bo(bo);
985 	struct ttm_resource *old_reg = bo->resource;
986 	struct nouveau_drm_tile *new_tile = NULL;
987 	int ret = 0;
988 
989 
990 	if (new_reg->mem_type == TTM_PL_TT) {
991 		ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg);
992 		if (ret)
993 			return ret;
994 	}
995 
996 	nouveau_bo_move_ntfy(bo, new_reg);
997 	ret = ttm_bo_wait_ctx(bo, ctx);
998 	if (ret)
999 		goto out_ntfy;
1000 
1001 	if (nvbo->bo.pin_count)
1002 		NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1003 
1004 	if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1005 		ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile);
1006 		if (ret)
1007 			goto out_ntfy;
1008 	}
1009 
1010 	/* Fake bo copy. */
1011 	if (!old_reg || (old_reg->mem_type == TTM_PL_SYSTEM &&
1012 			 !bo->ttm)) {
1013 		ttm_bo_move_null(bo, new_reg);
1014 		goto out;
1015 	}
1016 
1017 	if (old_reg->mem_type == TTM_PL_SYSTEM &&
1018 	    new_reg->mem_type == TTM_PL_TT) {
1019 		ttm_bo_move_null(bo, new_reg);
1020 		goto out;
1021 	}
1022 
1023 	if (old_reg->mem_type == TTM_PL_TT &&
1024 	    new_reg->mem_type == TTM_PL_SYSTEM) {
1025 		nouveau_ttm_tt_unbind(bo->bdev, bo->ttm);
1026 		ttm_resource_free(bo, &bo->resource);
1027 		ttm_bo_assign_mem(bo, new_reg);
1028 		goto out;
1029 	}
1030 
1031 	/* Hardware assisted copy. */
1032 	if (drm->ttm.move) {
1033 		if ((old_reg->mem_type == TTM_PL_SYSTEM &&
1034 		     new_reg->mem_type == TTM_PL_VRAM) ||
1035 		    (old_reg->mem_type == TTM_PL_VRAM &&
1036 		     new_reg->mem_type == TTM_PL_SYSTEM)) {
1037 			hop->fpfn = 0;
1038 			hop->lpfn = 0;
1039 			hop->mem_type = TTM_PL_TT;
1040 			hop->flags = 0;
1041 			return -EMULTIHOP;
1042 		}
1043 		ret = nouveau_bo_move_m2mf(bo, evict, ctx,
1044 					   new_reg);
1045 	} else
1046 		ret = -ENODEV;
1047 
1048 	if (ret) {
1049 		/* Fallback to software copy. */
1050 		ret = ttm_bo_move_memcpy(bo, ctx, new_reg);
1051 	}
1052 
1053 out:
1054 	if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1055 		if (ret)
1056 			nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1057 		else
1058 			nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1059 	}
1060 out_ntfy:
1061 	if (ret) {
1062 		nouveau_bo_move_ntfy(bo, bo->resource);
1063 	}
1064 	return ret;
1065 }
1066 
1067 static void
1068 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm,
1069 			       struct ttm_resource *reg)
1070 {
1071 	struct nouveau_mem *mem = nouveau_mem(reg);
1072 
1073 	if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1074 		switch (reg->mem_type) {
1075 		case TTM_PL_TT:
1076 			if (mem->kind)
1077 				nvif_object_unmap_handle(&mem->mem.object);
1078 			break;
1079 		case TTM_PL_VRAM:
1080 			nvif_object_unmap_handle(&mem->mem.object);
1081 			break;
1082 		default:
1083 			break;
1084 		}
1085 	}
1086 }
1087 
1088 static int
1089 nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg)
1090 {
1091 	struct nouveau_drm *drm = nouveau_bdev(bdev);
1092 	struct nvkm_device *device = nvxx_device(&drm->client.device);
1093 	struct nouveau_mem *mem = nouveau_mem(reg);
1094 	struct nvif_mmu *mmu = &drm->client.mmu;
1095 	int ret;
1096 
1097 	mutex_lock(&drm->ttm.io_reserve_mutex);
1098 retry:
1099 	switch (reg->mem_type) {
1100 	case TTM_PL_SYSTEM:
1101 		/* System memory */
1102 		ret = 0;
1103 		goto out;
1104 	case TTM_PL_TT:
1105 #if IS_ENABLED(CONFIG_AGP)
1106 		if (drm->agp.bridge) {
1107 			reg->bus.offset = (reg->start << PAGE_SHIFT) +
1108 				drm->agp.base;
1109 			reg->bus.is_iomem = !drm->agp.cma;
1110 			reg->bus.caching = ttm_write_combined;
1111 		}
1112 #endif
1113 		if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 ||
1114 		    !mem->kind) {
1115 			/* untiled */
1116 			ret = 0;
1117 			break;
1118 		}
1119 		fallthrough;	/* tiled memory */
1120 	case TTM_PL_VRAM:
1121 		reg->bus.offset = (reg->start << PAGE_SHIFT) +
1122 			device->func->resource_addr(device, 1);
1123 		reg->bus.is_iomem = true;
1124 
1125 		/* Some BARs do not support being ioremapped WC */
1126 		if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
1127 		    mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED)
1128 			reg->bus.caching = ttm_uncached;
1129 		else
1130 			reg->bus.caching = ttm_write_combined;
1131 
1132 		if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) {
1133 			union {
1134 				struct nv50_mem_map_v0 nv50;
1135 				struct gf100_mem_map_v0 gf100;
1136 			} args;
1137 			u64 handle, length;
1138 			u32 argc = 0;
1139 
1140 			switch (mem->mem.object.oclass) {
1141 			case NVIF_CLASS_MEM_NV50:
1142 				args.nv50.version = 0;
1143 				args.nv50.ro = 0;
1144 				args.nv50.kind = mem->kind;
1145 				args.nv50.comp = mem->comp;
1146 				argc = sizeof(args.nv50);
1147 				break;
1148 			case NVIF_CLASS_MEM_GF100:
1149 				args.gf100.version = 0;
1150 				args.gf100.ro = 0;
1151 				args.gf100.kind = mem->kind;
1152 				argc = sizeof(args.gf100);
1153 				break;
1154 			default:
1155 				WARN_ON(1);
1156 				break;
1157 			}
1158 
1159 			ret = nvif_object_map_handle(&mem->mem.object,
1160 						     &args, argc,
1161 						     &handle, &length);
1162 			if (ret != 1) {
1163 				if (WARN_ON(ret == 0))
1164 					ret = -EINVAL;
1165 				goto out;
1166 			}
1167 
1168 			reg->bus.offset = handle;
1169 		}
1170 		ret = 0;
1171 		break;
1172 	default:
1173 		ret = -EINVAL;
1174 	}
1175 
1176 out:
1177 	if (ret == -ENOSPC) {
1178 		struct nouveau_bo *nvbo;
1179 
1180 		nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru,
1181 						typeof(*nvbo),
1182 						io_reserve_lru);
1183 		if (nvbo) {
1184 			list_del_init(&nvbo->io_reserve_lru);
1185 			drm_vma_node_unmap(&nvbo->bo.base.vma_node,
1186 					   bdev->dev_mapping);
1187 			nouveau_ttm_io_mem_free_locked(drm, nvbo->bo.resource);
1188 			goto retry;
1189 		}
1190 
1191 	}
1192 	mutex_unlock(&drm->ttm.io_reserve_mutex);
1193 	return ret;
1194 }
1195 
1196 static void
1197 nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg)
1198 {
1199 	struct nouveau_drm *drm = nouveau_bdev(bdev);
1200 
1201 	mutex_lock(&drm->ttm.io_reserve_mutex);
1202 	nouveau_ttm_io_mem_free_locked(drm, reg);
1203 	mutex_unlock(&drm->ttm.io_reserve_mutex);
1204 }
1205 
1206 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1207 {
1208 	struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1209 	struct nouveau_bo *nvbo = nouveau_bo(bo);
1210 	struct nvkm_device *device = nvxx_device(&drm->client.device);
1211 	u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT;
1212 	int i, ret;
1213 
1214 	/* as long as the bo isn't in vram, and isn't tiled, we've got
1215 	 * nothing to do here.
1216 	 */
1217 	if (bo->resource->mem_type != TTM_PL_VRAM) {
1218 		if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1219 		    !nvbo->kind)
1220 			return 0;
1221 
1222 		if (bo->resource->mem_type != TTM_PL_SYSTEM)
1223 			return 0;
1224 
1225 		nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0);
1226 
1227 	} else {
1228 		/* make sure bo is in mappable vram */
1229 		if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1230 		    bo->resource->start + bo->resource->num_pages < mappable)
1231 			return 0;
1232 
1233 		for (i = 0; i < nvbo->placement.num_placement; ++i) {
1234 			nvbo->placements[i].fpfn = 0;
1235 			nvbo->placements[i].lpfn = mappable;
1236 		}
1237 
1238 		for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1239 			nvbo->busy_placements[i].fpfn = 0;
1240 			nvbo->busy_placements[i].lpfn = mappable;
1241 		}
1242 
1243 		nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0);
1244 	}
1245 
1246 	ret = nouveau_bo_validate(nvbo, false, false);
1247 	if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS))
1248 		return VM_FAULT_NOPAGE;
1249 	else if (unlikely(ret))
1250 		return VM_FAULT_SIGBUS;
1251 
1252 	ttm_bo_move_to_lru_tail_unlocked(bo);
1253 	return 0;
1254 }
1255 
1256 static int
1257 nouveau_ttm_tt_populate(struct ttm_device *bdev,
1258 			struct ttm_tt *ttm, struct ttm_operation_ctx *ctx)
1259 {
1260 	struct ttm_tt *ttm_dma = (void *)ttm;
1261 	struct nouveau_drm *drm;
1262 	bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1263 
1264 	if (ttm_tt_is_populated(ttm))
1265 		return 0;
1266 
1267 	if (slave && ttm->sg) {
1268 		drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address,
1269 					       ttm->num_pages);
1270 		return 0;
1271 	}
1272 
1273 	drm = nouveau_bdev(bdev);
1274 
1275 	return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx);
1276 }
1277 
1278 static void
1279 nouveau_ttm_tt_unpopulate(struct ttm_device *bdev,
1280 			  struct ttm_tt *ttm)
1281 {
1282 	struct nouveau_drm *drm;
1283 	bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
1284 
1285 	if (slave)
1286 		return;
1287 
1288 	nouveau_ttm_tt_unbind(bdev, ttm);
1289 
1290 	drm = nouveau_bdev(bdev);
1291 
1292 	return ttm_pool_free(&drm->ttm.bdev.pool, ttm);
1293 }
1294 
1295 static void
1296 nouveau_ttm_tt_destroy(struct ttm_device *bdev,
1297 		       struct ttm_tt *ttm)
1298 {
1299 #if IS_ENABLED(CONFIG_AGP)
1300 	struct nouveau_drm *drm = nouveau_bdev(bdev);
1301 	if (drm->agp.bridge) {
1302 		ttm_agp_destroy(ttm);
1303 		return;
1304 	}
1305 #endif
1306 	nouveau_sgdma_destroy(bdev, ttm);
1307 }
1308 
1309 void
1310 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1311 {
1312 	struct dma_resv *resv = nvbo->bo.base.resv;
1313 
1314 	if (!fence)
1315 		return;
1316 
1317 	dma_resv_add_fence(resv, &fence->base, exclusive ?
1318 			   DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_READ);
1319 }
1320 
1321 static void
1322 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1323 {
1324 	nouveau_bo_move_ntfy(bo, NULL);
1325 }
1326 
1327 struct ttm_device_funcs nouveau_bo_driver = {
1328 	.ttm_tt_create = &nouveau_ttm_tt_create,
1329 	.ttm_tt_populate = &nouveau_ttm_tt_populate,
1330 	.ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1331 	.ttm_tt_destroy = &nouveau_ttm_tt_destroy,
1332 	.eviction_valuable = ttm_bo_eviction_valuable,
1333 	.evict_flags = nouveau_bo_evict_flags,
1334 	.delete_mem_notify = nouveau_bo_delete_mem_notify,
1335 	.move = nouveau_bo_move,
1336 	.io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1337 	.io_mem_free = &nouveau_ttm_io_mem_free,
1338 };
1339