1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 #include <linux/swiotlb.h> 32 33 #include "nouveau_drv.h" 34 #include "nouveau_dma.h" 35 #include "nouveau_fence.h" 36 37 #include "nouveau_bo.h" 38 #include "nouveau_ttm.h" 39 #include "nouveau_gem.h" 40 #include "nouveau_mem.h" 41 #include "nouveau_vmm.h" 42 43 #include <nvif/class.h> 44 #include <nvif/if500b.h> 45 #include <nvif/if900b.h> 46 47 /* 48 * NV10-NV40 tiling helpers 49 */ 50 51 static void 52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 53 u32 addr, u32 size, u32 pitch, u32 flags) 54 { 55 struct nouveau_drm *drm = nouveau_drm(dev); 56 int i = reg - drm->tile.reg; 57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 58 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 59 60 nouveau_fence_unref(®->fence); 61 62 if (tile->pitch) 63 nvkm_fb_tile_fini(fb, i, tile); 64 65 if (pitch) 66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 67 68 nvkm_fb_tile_prog(fb, i, tile); 69 } 70 71 static struct nouveau_drm_tile * 72 nv10_bo_get_tile_region(struct drm_device *dev, int i) 73 { 74 struct nouveau_drm *drm = nouveau_drm(dev); 75 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 76 77 spin_lock(&drm->tile.lock); 78 79 if (!tile->used && 80 (!tile->fence || nouveau_fence_done(tile->fence))) 81 tile->used = true; 82 else 83 tile = NULL; 84 85 spin_unlock(&drm->tile.lock); 86 return tile; 87 } 88 89 static void 90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 91 struct dma_fence *fence) 92 { 93 struct nouveau_drm *drm = nouveau_drm(dev); 94 95 if (tile) { 96 spin_lock(&drm->tile.lock); 97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 98 tile->used = false; 99 spin_unlock(&drm->tile.lock); 100 } 101 } 102 103 static struct nouveau_drm_tile * 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 105 u32 size, u32 pitch, u32 zeta) 106 { 107 struct nouveau_drm *drm = nouveau_drm(dev); 108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 109 struct nouveau_drm_tile *tile, *found = NULL; 110 int i; 111 112 for (i = 0; i < fb->tile.regions; i++) { 113 tile = nv10_bo_get_tile_region(dev, i); 114 115 if (pitch && !found) { 116 found = tile; 117 continue; 118 119 } else if (tile && fb->tile.region[i].pitch) { 120 /* Kill an unused tile region. */ 121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 122 } 123 124 nv10_bo_put_tile_region(dev, tile, NULL); 125 } 126 127 if (found) 128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 129 return found; 130 } 131 132 static void 133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 134 { 135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 136 struct drm_device *dev = drm->dev; 137 struct nouveau_bo *nvbo = nouveau_bo(bo); 138 139 if (unlikely(nvbo->gem.filp)) 140 DRM_ERROR("bo %p still attached to GEM object\n", bo); 141 WARN_ON(nvbo->pin_refcnt > 0); 142 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 143 kfree(nvbo); 144 } 145 146 static inline u64 147 roundup_64(u64 x, u32 y) 148 { 149 x += y - 1; 150 do_div(x, y); 151 return x * y; 152 } 153 154 static void 155 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, 156 int *align, u64 *size) 157 { 158 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 159 struct nvif_device *device = &drm->client.device; 160 161 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 162 if (nvbo->mode) { 163 if (device->info.chipset >= 0x40) { 164 *align = 65536; 165 *size = roundup_64(*size, 64 * nvbo->mode); 166 167 } else if (device->info.chipset >= 0x30) { 168 *align = 32768; 169 *size = roundup_64(*size, 64 * nvbo->mode); 170 171 } else if (device->info.chipset >= 0x20) { 172 *align = 16384; 173 *size = roundup_64(*size, 64 * nvbo->mode); 174 175 } else if (device->info.chipset >= 0x10) { 176 *align = 16384; 177 *size = roundup_64(*size, 32 * nvbo->mode); 178 } 179 } 180 } else { 181 *size = roundup_64(*size, (1 << nvbo->page)); 182 *align = max((1 << nvbo->page), *align); 183 } 184 185 *size = roundup_64(*size, PAGE_SIZE); 186 } 187 188 int 189 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 190 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, 191 struct sg_table *sg, struct reservation_object *robj, 192 struct nouveau_bo **pnvbo) 193 { 194 struct nouveau_drm *drm = cli->drm; 195 struct nouveau_bo *nvbo; 196 struct nvif_mmu *mmu = &cli->mmu; 197 struct nvif_vmm *vmm = &cli->vmm.vmm; 198 size_t acc_size; 199 int type = ttm_bo_type_device; 200 int ret, i, pi = -1; 201 202 if (!size) { 203 NV_WARN(drm, "skipped size %016llx\n", size); 204 return -EINVAL; 205 } 206 207 if (sg) 208 type = ttm_bo_type_sg; 209 210 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 211 if (!nvbo) 212 return -ENOMEM; 213 INIT_LIST_HEAD(&nvbo->head); 214 INIT_LIST_HEAD(&nvbo->entry); 215 INIT_LIST_HEAD(&nvbo->vma_list); 216 nvbo->bo.bdev = &drm->ttm.bdev; 217 nvbo->cli = cli; 218 219 /* This is confusing, and doesn't actually mean we want an uncached 220 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 221 * into in nouveau_gem_new(). 222 */ 223 if (flags & TTM_PL_FLAG_UNCACHED) { 224 /* Determine if we can get a cache-coherent map, forcing 225 * uncached mapping if we can't. 226 */ 227 if (mmu->type[drm->ttm.type_host].type & NVIF_MEM_UNCACHED) 228 nvbo->force_coherent = true; 229 } 230 231 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 232 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 233 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 234 kfree(nvbo); 235 return -EINVAL; 236 } 237 238 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 239 } else 240 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 241 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 242 nvbo->comp = (tile_flags & 0x00030000) >> 16; 243 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 244 kfree(nvbo); 245 return -EINVAL; 246 } 247 } else { 248 nvbo->zeta = (tile_flags & 0x00000007); 249 } 250 nvbo->mode = tile_mode; 251 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 252 253 /* Determine the desirable target GPU page size for the buffer. */ 254 for (i = 0; i < vmm->page_nr; i++) { 255 /* Because we cannot currently allow VMM maps to fail 256 * during buffer migration, we need to determine page 257 * size for the buffer up-front, and pre-allocate its 258 * page tables. 259 * 260 * Skip page sizes that can't support needed domains. 261 */ 262 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 263 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram) 264 continue; 265 if ((flags & TTM_PL_FLAG_TT ) && !vmm->page[i].host) 266 continue; 267 268 /* Select this page size if it's the first that supports 269 * the potential memory domains, or when it's compatible 270 * with the requested compression settings. 271 */ 272 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 273 pi = i; 274 275 /* Stop once the buffer is larger than the current page size. */ 276 if (size >= 1ULL << vmm->page[i].shift) 277 break; 278 } 279 280 if (WARN_ON(pi < 0)) 281 return -EINVAL; 282 283 /* Disable compression if suitable settings couldn't be found. */ 284 if (nvbo->comp && !vmm->page[pi].comp) { 285 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 286 nvbo->kind = mmu->kind[nvbo->kind]; 287 nvbo->comp = 0; 288 } 289 nvbo->page = vmm->page[pi].shift; 290 291 nouveau_bo_fixup_align(nvbo, flags, &align, &size); 292 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; 293 nouveau_bo_placement_set(nvbo, flags, 0); 294 295 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, 296 sizeof(struct nouveau_bo)); 297 298 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, 299 type, &nvbo->placement, 300 align >> PAGE_SHIFT, false, NULL, acc_size, sg, 301 robj, nouveau_bo_del_ttm); 302 if (ret) { 303 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 304 return ret; 305 } 306 307 *pnvbo = nvbo; 308 return 0; 309 } 310 311 static void 312 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) 313 { 314 *n = 0; 315 316 if (type & TTM_PL_FLAG_VRAM) 317 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; 318 if (type & TTM_PL_FLAG_TT) 319 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; 320 if (type & TTM_PL_FLAG_SYSTEM) 321 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; 322 } 323 324 static void 325 set_placement_range(struct nouveau_bo *nvbo, uint32_t type) 326 { 327 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 328 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; 329 unsigned i, fpfn, lpfn; 330 331 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 332 nvbo->mode && (type & TTM_PL_FLAG_VRAM) && 333 nvbo->bo.mem.num_pages < vram_pages / 4) { 334 /* 335 * Make sure that the color and depth buffers are handled 336 * by independent memory controller units. Up to a 9x 337 * speed up when alpha-blending and depth-test are enabled 338 * at the same time. 339 */ 340 if (nvbo->zeta) { 341 fpfn = vram_pages / 2; 342 lpfn = ~0; 343 } else { 344 fpfn = 0; 345 lpfn = vram_pages / 2; 346 } 347 for (i = 0; i < nvbo->placement.num_placement; ++i) { 348 nvbo->placements[i].fpfn = fpfn; 349 nvbo->placements[i].lpfn = lpfn; 350 } 351 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 352 nvbo->busy_placements[i].fpfn = fpfn; 353 nvbo->busy_placements[i].lpfn = lpfn; 354 } 355 } 356 } 357 358 void 359 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) 360 { 361 struct ttm_placement *pl = &nvbo->placement; 362 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : 363 TTM_PL_MASK_CACHING) | 364 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); 365 366 pl->placement = nvbo->placements; 367 set_placement_list(nvbo->placements, &pl->num_placement, 368 type, flags); 369 370 pl->busy_placement = nvbo->busy_placements; 371 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 372 type | busy, flags); 373 374 set_placement_range(nvbo, type); 375 } 376 377 int 378 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) 379 { 380 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 381 struct ttm_buffer_object *bo = &nvbo->bo; 382 bool force = false, evict = false; 383 int ret; 384 385 ret = ttm_bo_reserve(bo, false, false, NULL); 386 if (ret) 387 return ret; 388 389 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 390 memtype == TTM_PL_FLAG_VRAM && contig) { 391 if (!nvbo->contig) { 392 nvbo->contig = true; 393 force = true; 394 evict = true; 395 } 396 } 397 398 if (nvbo->pin_refcnt) { 399 if (!(memtype & (1 << bo->mem.mem_type)) || evict) { 400 NV_ERROR(drm, "bo %p pinned elsewhere: " 401 "0x%08x vs 0x%08x\n", bo, 402 1 << bo->mem.mem_type, memtype); 403 ret = -EBUSY; 404 } 405 nvbo->pin_refcnt++; 406 goto out; 407 } 408 409 if (evict) { 410 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); 411 ret = nouveau_bo_validate(nvbo, false, false); 412 if (ret) 413 goto out; 414 } 415 416 nvbo->pin_refcnt++; 417 nouveau_bo_placement_set(nvbo, memtype, 0); 418 419 /* drop pin_refcnt temporarily, so we don't trip the assertion 420 * in nouveau_bo_move() that makes sure we're not trying to 421 * move a pinned buffer 422 */ 423 nvbo->pin_refcnt--; 424 ret = nouveau_bo_validate(nvbo, false, false); 425 if (ret) 426 goto out; 427 nvbo->pin_refcnt++; 428 429 switch (bo->mem.mem_type) { 430 case TTM_PL_VRAM: 431 drm->gem.vram_available -= bo->mem.size; 432 break; 433 case TTM_PL_TT: 434 drm->gem.gart_available -= bo->mem.size; 435 break; 436 default: 437 break; 438 } 439 440 out: 441 if (force && ret) 442 nvbo->contig = false; 443 ttm_bo_unreserve(bo); 444 return ret; 445 } 446 447 int 448 nouveau_bo_unpin(struct nouveau_bo *nvbo) 449 { 450 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 451 struct ttm_buffer_object *bo = &nvbo->bo; 452 int ret, ref; 453 454 ret = ttm_bo_reserve(bo, false, false, NULL); 455 if (ret) 456 return ret; 457 458 ref = --nvbo->pin_refcnt; 459 WARN_ON_ONCE(ref < 0); 460 if (ref) 461 goto out; 462 463 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); 464 465 ret = nouveau_bo_validate(nvbo, false, false); 466 if (ret == 0) { 467 switch (bo->mem.mem_type) { 468 case TTM_PL_VRAM: 469 drm->gem.vram_available += bo->mem.size; 470 break; 471 case TTM_PL_TT: 472 drm->gem.gart_available += bo->mem.size; 473 break; 474 default: 475 break; 476 } 477 } 478 479 out: 480 ttm_bo_unreserve(bo); 481 return ret; 482 } 483 484 int 485 nouveau_bo_map(struct nouveau_bo *nvbo) 486 { 487 int ret; 488 489 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 490 if (ret) 491 return ret; 492 493 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 494 495 ttm_bo_unreserve(&nvbo->bo); 496 return ret; 497 } 498 499 void 500 nouveau_bo_unmap(struct nouveau_bo *nvbo) 501 { 502 if (!nvbo) 503 return; 504 505 ttm_bo_kunmap(&nvbo->kmap); 506 } 507 508 void 509 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 510 { 511 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 512 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 513 int i; 514 515 if (!ttm_dma) 516 return; 517 518 /* Don't waste time looping if the object is coherent */ 519 if (nvbo->force_coherent) 520 return; 521 522 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 523 dma_sync_single_for_device(drm->dev->dev, 524 ttm_dma->dma_address[i], 525 PAGE_SIZE, DMA_TO_DEVICE); 526 } 527 528 void 529 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 530 { 531 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 532 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 533 int i; 534 535 if (!ttm_dma) 536 return; 537 538 /* Don't waste time looping if the object is coherent */ 539 if (nvbo->force_coherent) 540 return; 541 542 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 543 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 544 PAGE_SIZE, DMA_FROM_DEVICE); 545 } 546 547 int 548 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 549 bool no_wait_gpu) 550 { 551 int ret; 552 553 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, 554 interruptible, no_wait_gpu); 555 if (ret) 556 return ret; 557 558 nouveau_bo_sync_for_device(nvbo); 559 560 return 0; 561 } 562 563 void 564 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 565 { 566 bool is_iomem; 567 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 568 569 mem += index; 570 571 if (is_iomem) 572 iowrite16_native(val, (void __force __iomem *)mem); 573 else 574 *mem = val; 575 } 576 577 u32 578 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 579 { 580 bool is_iomem; 581 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 582 583 mem += index; 584 585 if (is_iomem) 586 return ioread32_native((void __force __iomem *)mem); 587 else 588 return *mem; 589 } 590 591 void 592 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 593 { 594 bool is_iomem; 595 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 596 597 mem += index; 598 599 if (is_iomem) 600 iowrite32_native(val, (void __force __iomem *)mem); 601 else 602 *mem = val; 603 } 604 605 static struct ttm_tt * 606 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, 607 uint32_t page_flags, struct page *dummy_read) 608 { 609 #if IS_ENABLED(CONFIG_AGP) 610 struct nouveau_drm *drm = nouveau_bdev(bdev); 611 612 if (drm->agp.bridge) { 613 return ttm_agp_tt_create(bdev, drm->agp.bridge, size, 614 page_flags, dummy_read); 615 } 616 #endif 617 618 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read); 619 } 620 621 static int 622 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 623 { 624 /* We'll do this from user space. */ 625 return 0; 626 } 627 628 static int 629 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 630 struct ttm_mem_type_manager *man) 631 { 632 struct nouveau_drm *drm = nouveau_bdev(bdev); 633 struct nvif_mmu *mmu = &drm->client.mmu; 634 635 switch (type) { 636 case TTM_PL_SYSTEM: 637 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 638 man->available_caching = TTM_PL_MASK_CACHING; 639 man->default_caching = TTM_PL_FLAG_CACHED; 640 break; 641 case TTM_PL_VRAM: 642 man->flags = TTM_MEMTYPE_FLAG_FIXED | 643 TTM_MEMTYPE_FLAG_MAPPABLE; 644 man->available_caching = TTM_PL_FLAG_UNCACHED | 645 TTM_PL_FLAG_WC; 646 man->default_caching = TTM_PL_FLAG_WC; 647 648 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 649 /* Some BARs do not support being ioremapped WC */ 650 const u8 type = mmu->type[drm->ttm.type_vram].type; 651 if (type & NVIF_MEM_UNCACHED) { 652 man->available_caching = TTM_PL_FLAG_UNCACHED; 653 man->default_caching = TTM_PL_FLAG_UNCACHED; 654 } 655 656 man->func = &nouveau_vram_manager; 657 man->io_reserve_fastpath = false; 658 man->use_io_reserve_lru = true; 659 } else { 660 man->func = &ttm_bo_manager_func; 661 } 662 break; 663 case TTM_PL_TT: 664 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) 665 man->func = &nouveau_gart_manager; 666 else 667 if (!drm->agp.bridge) 668 man->func = &nv04_gart_manager; 669 else 670 man->func = &ttm_bo_manager_func; 671 672 if (drm->agp.bridge) { 673 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 674 man->available_caching = TTM_PL_FLAG_UNCACHED | 675 TTM_PL_FLAG_WC; 676 man->default_caching = TTM_PL_FLAG_WC; 677 } else { 678 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | 679 TTM_MEMTYPE_FLAG_CMA; 680 man->available_caching = TTM_PL_MASK_CACHING; 681 man->default_caching = TTM_PL_FLAG_CACHED; 682 } 683 684 break; 685 default: 686 return -EINVAL; 687 } 688 return 0; 689 } 690 691 static void 692 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 693 { 694 struct nouveau_bo *nvbo = nouveau_bo(bo); 695 696 switch (bo->mem.mem_type) { 697 case TTM_PL_VRAM: 698 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 699 TTM_PL_FLAG_SYSTEM); 700 break; 701 default: 702 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); 703 break; 704 } 705 706 *pl = nvbo->placement; 707 } 708 709 710 static int 711 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) 712 { 713 int ret = RING_SPACE(chan, 2); 714 if (ret == 0) { 715 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 716 OUT_RING (chan, handle & 0x0000ffff); 717 FIRE_RING (chan); 718 } 719 return ret; 720 } 721 722 static int 723 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 724 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 725 { 726 struct nouveau_mem *mem = nouveau_mem(old_reg); 727 int ret = RING_SPACE(chan, 10); 728 if (ret == 0) { 729 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); 730 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 731 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 732 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 733 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 734 OUT_RING (chan, PAGE_SIZE); 735 OUT_RING (chan, PAGE_SIZE); 736 OUT_RING (chan, PAGE_SIZE); 737 OUT_RING (chan, new_reg->num_pages); 738 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); 739 } 740 return ret; 741 } 742 743 static int 744 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) 745 { 746 int ret = RING_SPACE(chan, 2); 747 if (ret == 0) { 748 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 749 OUT_RING (chan, handle); 750 } 751 return ret; 752 } 753 754 static int 755 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 756 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 757 { 758 struct nouveau_mem *mem = nouveau_mem(old_reg); 759 u64 src_offset = mem->vma[0].addr; 760 u64 dst_offset = mem->vma[1].addr; 761 u32 page_count = new_reg->num_pages; 762 int ret; 763 764 page_count = new_reg->num_pages; 765 while (page_count) { 766 int line_count = (page_count > 8191) ? 8191 : page_count; 767 768 ret = RING_SPACE(chan, 11); 769 if (ret) 770 return ret; 771 772 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); 773 OUT_RING (chan, upper_32_bits(src_offset)); 774 OUT_RING (chan, lower_32_bits(src_offset)); 775 OUT_RING (chan, upper_32_bits(dst_offset)); 776 OUT_RING (chan, lower_32_bits(dst_offset)); 777 OUT_RING (chan, PAGE_SIZE); 778 OUT_RING (chan, PAGE_SIZE); 779 OUT_RING (chan, PAGE_SIZE); 780 OUT_RING (chan, line_count); 781 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 782 OUT_RING (chan, 0x00000110); 783 784 page_count -= line_count; 785 src_offset += (PAGE_SIZE * line_count); 786 dst_offset += (PAGE_SIZE * line_count); 787 } 788 789 return 0; 790 } 791 792 static int 793 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 794 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 795 { 796 struct nouveau_mem *mem = nouveau_mem(old_reg); 797 u64 src_offset = mem->vma[0].addr; 798 u64 dst_offset = mem->vma[1].addr; 799 u32 page_count = new_reg->num_pages; 800 int ret; 801 802 page_count = new_reg->num_pages; 803 while (page_count) { 804 int line_count = (page_count > 2047) ? 2047 : page_count; 805 806 ret = RING_SPACE(chan, 12); 807 if (ret) 808 return ret; 809 810 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); 811 OUT_RING (chan, upper_32_bits(dst_offset)); 812 OUT_RING (chan, lower_32_bits(dst_offset)); 813 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); 814 OUT_RING (chan, upper_32_bits(src_offset)); 815 OUT_RING (chan, lower_32_bits(src_offset)); 816 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 817 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 818 OUT_RING (chan, PAGE_SIZE); /* line_length */ 819 OUT_RING (chan, line_count); 820 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 821 OUT_RING (chan, 0x00100110); 822 823 page_count -= line_count; 824 src_offset += (PAGE_SIZE * line_count); 825 dst_offset += (PAGE_SIZE * line_count); 826 } 827 828 return 0; 829 } 830 831 static int 832 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 833 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 834 { 835 struct nouveau_mem *mem = nouveau_mem(old_reg); 836 u64 src_offset = mem->vma[0].addr; 837 u64 dst_offset = mem->vma[1].addr; 838 u32 page_count = new_reg->num_pages; 839 int ret; 840 841 page_count = new_reg->num_pages; 842 while (page_count) { 843 int line_count = (page_count > 8191) ? 8191 : page_count; 844 845 ret = RING_SPACE(chan, 11); 846 if (ret) 847 return ret; 848 849 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 850 OUT_RING (chan, upper_32_bits(src_offset)); 851 OUT_RING (chan, lower_32_bits(src_offset)); 852 OUT_RING (chan, upper_32_bits(dst_offset)); 853 OUT_RING (chan, lower_32_bits(dst_offset)); 854 OUT_RING (chan, PAGE_SIZE); 855 OUT_RING (chan, PAGE_SIZE); 856 OUT_RING (chan, PAGE_SIZE); 857 OUT_RING (chan, line_count); 858 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); 859 OUT_RING (chan, 0x00000110); 860 861 page_count -= line_count; 862 src_offset += (PAGE_SIZE * line_count); 863 dst_offset += (PAGE_SIZE * line_count); 864 } 865 866 return 0; 867 } 868 869 static int 870 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 871 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 872 { 873 struct nouveau_mem *mem = nouveau_mem(old_reg); 874 int ret = RING_SPACE(chan, 7); 875 if (ret == 0) { 876 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); 877 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 878 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 879 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 880 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 881 OUT_RING (chan, 0x00000000 /* COPY */); 882 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 883 } 884 return ret; 885 } 886 887 static int 888 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 889 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 890 { 891 struct nouveau_mem *mem = nouveau_mem(old_reg); 892 int ret = RING_SPACE(chan, 7); 893 if (ret == 0) { 894 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); 895 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 896 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 897 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 898 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 899 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 900 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); 901 } 902 return ret; 903 } 904 905 static int 906 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) 907 { 908 int ret = RING_SPACE(chan, 6); 909 if (ret == 0) { 910 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 911 OUT_RING (chan, handle); 912 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); 913 OUT_RING (chan, chan->drm->ntfy.handle); 914 OUT_RING (chan, chan->vram.handle); 915 OUT_RING (chan, chan->vram.handle); 916 } 917 918 return ret; 919 } 920 921 static int 922 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 923 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 924 { 925 struct nouveau_mem *mem = nouveau_mem(old_reg); 926 u64 length = (new_reg->num_pages << PAGE_SHIFT); 927 u64 src_offset = mem->vma[0].addr; 928 u64 dst_offset = mem->vma[1].addr; 929 int src_tiled = !!mem->kind; 930 int dst_tiled = !!nouveau_mem(new_reg)->kind; 931 int ret; 932 933 while (length) { 934 u32 amount, stride, height; 935 936 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); 937 if (ret) 938 return ret; 939 940 amount = min(length, (u64)(4 * 1024 * 1024)); 941 stride = 16 * 4; 942 height = amount / stride; 943 944 if (src_tiled) { 945 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); 946 OUT_RING (chan, 0); 947 OUT_RING (chan, 0); 948 OUT_RING (chan, stride); 949 OUT_RING (chan, height); 950 OUT_RING (chan, 1); 951 OUT_RING (chan, 0); 952 OUT_RING (chan, 0); 953 } else { 954 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); 955 OUT_RING (chan, 1); 956 } 957 if (dst_tiled) { 958 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); 959 OUT_RING (chan, 0); 960 OUT_RING (chan, 0); 961 OUT_RING (chan, stride); 962 OUT_RING (chan, height); 963 OUT_RING (chan, 1); 964 OUT_RING (chan, 0); 965 OUT_RING (chan, 0); 966 } else { 967 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); 968 OUT_RING (chan, 1); 969 } 970 971 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); 972 OUT_RING (chan, upper_32_bits(src_offset)); 973 OUT_RING (chan, upper_32_bits(dst_offset)); 974 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 975 OUT_RING (chan, lower_32_bits(src_offset)); 976 OUT_RING (chan, lower_32_bits(dst_offset)); 977 OUT_RING (chan, stride); 978 OUT_RING (chan, stride); 979 OUT_RING (chan, stride); 980 OUT_RING (chan, height); 981 OUT_RING (chan, 0x00000101); 982 OUT_RING (chan, 0x00000000); 983 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 984 OUT_RING (chan, 0); 985 986 length -= amount; 987 src_offset += amount; 988 dst_offset += amount; 989 } 990 991 return 0; 992 } 993 994 static int 995 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) 996 { 997 int ret = RING_SPACE(chan, 4); 998 if (ret == 0) { 999 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 1000 OUT_RING (chan, handle); 1001 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); 1002 OUT_RING (chan, chan->drm->ntfy.handle); 1003 } 1004 1005 return ret; 1006 } 1007 1008 static inline uint32_t 1009 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, 1010 struct nouveau_channel *chan, struct ttm_mem_reg *reg) 1011 { 1012 if (reg->mem_type == TTM_PL_TT) 1013 return NvDmaTT; 1014 return chan->vram.handle; 1015 } 1016 1017 static int 1018 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 1019 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 1020 { 1021 u32 src_offset = old_reg->start << PAGE_SHIFT; 1022 u32 dst_offset = new_reg->start << PAGE_SHIFT; 1023 u32 page_count = new_reg->num_pages; 1024 int ret; 1025 1026 ret = RING_SPACE(chan, 3); 1027 if (ret) 1028 return ret; 1029 1030 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); 1031 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); 1032 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); 1033 1034 page_count = new_reg->num_pages; 1035 while (page_count) { 1036 int line_count = (page_count > 2047) ? 2047 : page_count; 1037 1038 ret = RING_SPACE(chan, 11); 1039 if (ret) 1040 return ret; 1041 1042 BEGIN_NV04(chan, NvSubCopy, 1043 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 1044 OUT_RING (chan, src_offset); 1045 OUT_RING (chan, dst_offset); 1046 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 1047 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 1048 OUT_RING (chan, PAGE_SIZE); /* line_length */ 1049 OUT_RING (chan, line_count); 1050 OUT_RING (chan, 0x00000101); 1051 OUT_RING (chan, 0x00000000); 1052 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 1053 OUT_RING (chan, 0); 1054 1055 page_count -= line_count; 1056 src_offset += (PAGE_SIZE * line_count); 1057 dst_offset += (PAGE_SIZE * line_count); 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int 1064 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 1065 struct ttm_mem_reg *reg) 1066 { 1067 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 1068 struct nouveau_mem *new_mem = nouveau_mem(reg); 1069 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 1070 int ret; 1071 1072 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 1073 old_mem->mem.size, &old_mem->vma[0]); 1074 if (ret) 1075 return ret; 1076 1077 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 1078 new_mem->mem.size, &old_mem->vma[1]); 1079 if (ret) 1080 goto done; 1081 1082 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 1083 if (ret) 1084 goto done; 1085 1086 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 1087 done: 1088 if (ret) { 1089 nvif_vmm_put(vmm, &old_mem->vma[1]); 1090 nvif_vmm_put(vmm, &old_mem->vma[0]); 1091 } 1092 return 0; 1093 } 1094 1095 static int 1096 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, 1097 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1098 { 1099 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1100 struct nouveau_channel *chan = drm->ttm.chan; 1101 struct nouveau_cli *cli = (void *)chan->user.client; 1102 struct nouveau_fence *fence; 1103 int ret; 1104 1105 /* create temporary vmas for the transfer and attach them to the 1106 * old nvkm_mem node, these will get cleaned up after ttm has 1107 * destroyed the ttm_mem_reg 1108 */ 1109 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 1110 ret = nouveau_bo_move_prep(drm, bo, new_reg); 1111 if (ret) 1112 return ret; 1113 } 1114 1115 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 1116 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); 1117 if (ret == 0) { 1118 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 1119 if (ret == 0) { 1120 ret = nouveau_fence_new(chan, false, &fence); 1121 if (ret == 0) { 1122 ret = ttm_bo_move_accel_cleanup(bo, 1123 &fence->base, 1124 evict, 1125 new_reg); 1126 nouveau_fence_unref(&fence); 1127 } 1128 } 1129 } 1130 mutex_unlock(&cli->mutex); 1131 return ret; 1132 } 1133 1134 void 1135 nouveau_bo_move_init(struct nouveau_drm *drm) 1136 { 1137 static const struct { 1138 const char *name; 1139 int engine; 1140 s32 oclass; 1141 int (*exec)(struct nouveau_channel *, 1142 struct ttm_buffer_object *, 1143 struct ttm_mem_reg *, struct ttm_mem_reg *); 1144 int (*init)(struct nouveau_channel *, u32 handle); 1145 } _methods[] = { 1146 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 1147 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1148 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1149 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1150 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1151 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1152 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1153 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1154 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 1155 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 1156 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 1157 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 1158 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 1159 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 1160 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 1161 {}, 1162 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, 1163 }, *mthd = _methods; 1164 const char *name = "CPU"; 1165 int ret; 1166 1167 do { 1168 struct nouveau_channel *chan; 1169 1170 if (mthd->engine) 1171 chan = drm->cechan; 1172 else 1173 chan = drm->channel; 1174 if (chan == NULL) 1175 continue; 1176 1177 ret = nvif_object_init(&chan->user, 1178 mthd->oclass | (mthd->engine << 16), 1179 mthd->oclass, NULL, 0, 1180 &drm->ttm.copy); 1181 if (ret == 0) { 1182 ret = mthd->init(chan, drm->ttm.copy.handle); 1183 if (ret) { 1184 nvif_object_fini(&drm->ttm.copy); 1185 continue; 1186 } 1187 1188 drm->ttm.move = mthd->exec; 1189 drm->ttm.chan = chan; 1190 name = mthd->name; 1191 break; 1192 } 1193 } while ((++mthd)->exec); 1194 1195 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 1196 } 1197 1198 static int 1199 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 1200 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1201 { 1202 struct ttm_place placement_memtype = { 1203 .fpfn = 0, 1204 .lpfn = 0, 1205 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1206 }; 1207 struct ttm_placement placement; 1208 struct ttm_mem_reg tmp_reg; 1209 int ret; 1210 1211 placement.num_placement = placement.num_busy_placement = 1; 1212 placement.placement = placement.busy_placement = &placement_memtype; 1213 1214 tmp_reg = *new_reg; 1215 tmp_reg.mm_node = NULL; 1216 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); 1217 if (ret) 1218 return ret; 1219 1220 ret = ttm_tt_bind(bo->ttm, &tmp_reg); 1221 if (ret) 1222 goto out; 1223 1224 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); 1225 if (ret) 1226 goto out; 1227 1228 ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, new_reg); 1229 out: 1230 ttm_bo_mem_put(bo, &tmp_reg); 1231 return ret; 1232 } 1233 1234 static int 1235 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 1236 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1237 { 1238 struct ttm_place placement_memtype = { 1239 .fpfn = 0, 1240 .lpfn = 0, 1241 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1242 }; 1243 struct ttm_placement placement; 1244 struct ttm_mem_reg tmp_reg; 1245 int ret; 1246 1247 placement.num_placement = placement.num_busy_placement = 1; 1248 placement.placement = placement.busy_placement = &placement_memtype; 1249 1250 tmp_reg = *new_reg; 1251 tmp_reg.mm_node = NULL; 1252 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, intr, no_wait_gpu); 1253 if (ret) 1254 return ret; 1255 1256 ret = ttm_bo_move_ttm(bo, intr, no_wait_gpu, &tmp_reg); 1257 if (ret) 1258 goto out; 1259 1260 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); 1261 if (ret) 1262 goto out; 1263 1264 out: 1265 ttm_bo_mem_put(bo, &tmp_reg); 1266 return ret; 1267 } 1268 1269 static void 1270 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, 1271 struct ttm_mem_reg *new_reg) 1272 { 1273 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 1274 struct nouveau_bo *nvbo = nouveau_bo(bo); 1275 struct nouveau_vma *vma; 1276 1277 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 1278 if (bo->destroy != nouveau_bo_del_ttm) 1279 return; 1280 1281 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 1282 mem->mem.page == nvbo->page) { 1283 list_for_each_entry(vma, &nvbo->vma_list, head) { 1284 nouveau_vma_map(vma, mem); 1285 } 1286 } else { 1287 list_for_each_entry(vma, &nvbo->vma_list, head) { 1288 WARN_ON(ttm_bo_wait(bo, false, false)); 1289 nouveau_vma_unmap(vma); 1290 } 1291 } 1292 } 1293 1294 static int 1295 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg, 1296 struct nouveau_drm_tile **new_tile) 1297 { 1298 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1299 struct drm_device *dev = drm->dev; 1300 struct nouveau_bo *nvbo = nouveau_bo(bo); 1301 u64 offset = new_reg->start << PAGE_SHIFT; 1302 1303 *new_tile = NULL; 1304 if (new_reg->mem_type != TTM_PL_VRAM) 1305 return 0; 1306 1307 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 1308 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, 1309 nvbo->mode, nvbo->zeta); 1310 } 1311 1312 return 0; 1313 } 1314 1315 static void 1316 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 1317 struct nouveau_drm_tile *new_tile, 1318 struct nouveau_drm_tile **old_tile) 1319 { 1320 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1321 struct drm_device *dev = drm->dev; 1322 struct dma_fence *fence = reservation_object_get_excl(bo->resv); 1323 1324 nv10_bo_put_tile_region(dev, *old_tile, fence); 1325 *old_tile = new_tile; 1326 } 1327 1328 static int 1329 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, 1330 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1331 { 1332 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1333 struct nouveau_bo *nvbo = nouveau_bo(bo); 1334 struct ttm_mem_reg *old_reg = &bo->mem; 1335 struct nouveau_drm_tile *new_tile = NULL; 1336 int ret = 0; 1337 1338 ret = ttm_bo_wait(bo, intr, no_wait_gpu); 1339 if (ret) 1340 return ret; 1341 1342 if (nvbo->pin_refcnt) 1343 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 1344 1345 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1346 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 1347 if (ret) 1348 return ret; 1349 } 1350 1351 /* Fake bo copy. */ 1352 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 1353 BUG_ON(bo->mem.mm_node != NULL); 1354 bo->mem = *new_reg; 1355 new_reg->mm_node = NULL; 1356 goto out; 1357 } 1358 1359 /* Hardware assisted copy. */ 1360 if (drm->ttm.move) { 1361 if (new_reg->mem_type == TTM_PL_SYSTEM) 1362 ret = nouveau_bo_move_flipd(bo, evict, intr, 1363 no_wait_gpu, new_reg); 1364 else if (old_reg->mem_type == TTM_PL_SYSTEM) 1365 ret = nouveau_bo_move_flips(bo, evict, intr, 1366 no_wait_gpu, new_reg); 1367 else 1368 ret = nouveau_bo_move_m2mf(bo, evict, intr, 1369 no_wait_gpu, new_reg); 1370 if (!ret) 1371 goto out; 1372 } 1373 1374 /* Fallback to software copy. */ 1375 ret = ttm_bo_wait(bo, intr, no_wait_gpu); 1376 if (ret == 0) 1377 ret = ttm_bo_move_memcpy(bo, intr, no_wait_gpu, new_reg); 1378 1379 out: 1380 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1381 if (ret) 1382 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1383 else 1384 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1385 } 1386 1387 return ret; 1388 } 1389 1390 static int 1391 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 1392 { 1393 struct nouveau_bo *nvbo = nouveau_bo(bo); 1394 1395 return drm_vma_node_verify_access(&nvbo->gem.vma_node, 1396 filp->private_data); 1397 } 1398 1399 static int 1400 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1401 { 1402 struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type]; 1403 struct nouveau_drm *drm = nouveau_bdev(bdev); 1404 struct nvkm_device *device = nvxx_device(&drm->client.device); 1405 struct nouveau_mem *mem = nouveau_mem(reg); 1406 1407 reg->bus.addr = NULL; 1408 reg->bus.offset = 0; 1409 reg->bus.size = reg->num_pages << PAGE_SHIFT; 1410 reg->bus.base = 0; 1411 reg->bus.is_iomem = false; 1412 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 1413 return -EINVAL; 1414 switch (reg->mem_type) { 1415 case TTM_PL_SYSTEM: 1416 /* System memory */ 1417 return 0; 1418 case TTM_PL_TT: 1419 #if IS_ENABLED(CONFIG_AGP) 1420 if (drm->agp.bridge) { 1421 reg->bus.offset = reg->start << PAGE_SHIFT; 1422 reg->bus.base = drm->agp.base; 1423 reg->bus.is_iomem = !drm->agp.cma; 1424 } 1425 #endif 1426 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) 1427 /* untiled */ 1428 break; 1429 /* fallthrough, tiled memory */ 1430 case TTM_PL_VRAM: 1431 reg->bus.offset = reg->start << PAGE_SHIFT; 1432 reg->bus.base = device->func->resource_addr(device, 1); 1433 reg->bus.is_iomem = true; 1434 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1435 union { 1436 struct nv50_mem_map_v0 nv50; 1437 struct gf100_mem_map_v0 gf100; 1438 } args; 1439 u64 handle, length; 1440 u32 argc = 0; 1441 int ret; 1442 1443 switch (mem->mem.object.oclass) { 1444 case NVIF_CLASS_MEM_NV50: 1445 args.nv50.version = 0; 1446 args.nv50.ro = 0; 1447 args.nv50.kind = mem->kind; 1448 args.nv50.comp = mem->comp; 1449 break; 1450 case NVIF_CLASS_MEM_GF100: 1451 args.gf100.version = 0; 1452 args.gf100.ro = 0; 1453 args.gf100.kind = mem->kind; 1454 break; 1455 default: 1456 WARN_ON(1); 1457 break; 1458 } 1459 1460 ret = nvif_object_map_handle(&mem->mem.object, 1461 &argc, argc, 1462 &handle, &length); 1463 if (ret != 1) 1464 return ret ? ret : -EINVAL; 1465 1466 reg->bus.base = 0; 1467 reg->bus.offset = handle; 1468 } 1469 break; 1470 default: 1471 return -EINVAL; 1472 } 1473 return 0; 1474 } 1475 1476 static void 1477 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1478 { 1479 struct nouveau_drm *drm = nouveau_bdev(bdev); 1480 struct nouveau_mem *mem = nouveau_mem(reg); 1481 1482 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1483 switch (reg->mem_type) { 1484 case TTM_PL_TT: 1485 if (mem->kind) 1486 nvif_object_unmap_handle(&mem->mem.object); 1487 break; 1488 case TTM_PL_VRAM: 1489 nvif_object_unmap_handle(&mem->mem.object); 1490 break; 1491 default: 1492 break; 1493 } 1494 } 1495 } 1496 1497 static int 1498 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1499 { 1500 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1501 struct nouveau_bo *nvbo = nouveau_bo(bo); 1502 struct nvkm_device *device = nvxx_device(&drm->client.device); 1503 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1504 int i, ret; 1505 1506 /* as long as the bo isn't in vram, and isn't tiled, we've got 1507 * nothing to do here. 1508 */ 1509 if (bo->mem.mem_type != TTM_PL_VRAM) { 1510 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1511 !nvbo->kind) 1512 return 0; 1513 1514 if (bo->mem.mem_type == TTM_PL_SYSTEM) { 1515 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); 1516 1517 ret = nouveau_bo_validate(nvbo, false, false); 1518 if (ret) 1519 return ret; 1520 } 1521 return 0; 1522 } 1523 1524 /* make sure bo is in mappable vram */ 1525 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1526 bo->mem.start + bo->mem.num_pages < mappable) 1527 return 0; 1528 1529 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1530 nvbo->placements[i].fpfn = 0; 1531 nvbo->placements[i].lpfn = mappable; 1532 } 1533 1534 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1535 nvbo->busy_placements[i].fpfn = 0; 1536 nvbo->busy_placements[i].lpfn = mappable; 1537 } 1538 1539 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); 1540 return nouveau_bo_validate(nvbo, false, false); 1541 } 1542 1543 static int 1544 nouveau_ttm_tt_populate(struct ttm_tt *ttm) 1545 { 1546 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1547 struct nouveau_drm *drm; 1548 struct device *dev; 1549 unsigned i; 1550 int r; 1551 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1552 1553 if (ttm->state != tt_unpopulated) 1554 return 0; 1555 1556 if (slave && ttm->sg) { 1557 /* make userspace faulting work */ 1558 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1559 ttm_dma->dma_address, ttm->num_pages); 1560 ttm->state = tt_unbound; 1561 return 0; 1562 } 1563 1564 drm = nouveau_bdev(ttm->bdev); 1565 dev = drm->dev->dev; 1566 1567 #if IS_ENABLED(CONFIG_AGP) 1568 if (drm->agp.bridge) { 1569 return ttm_agp_tt_populate(ttm); 1570 } 1571 #endif 1572 1573 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1574 if (swiotlb_nr_tbl()) { 1575 return ttm_dma_populate((void *)ttm, dev); 1576 } 1577 #endif 1578 1579 r = ttm_pool_populate(ttm); 1580 if (r) { 1581 return r; 1582 } 1583 1584 for (i = 0; i < ttm->num_pages; i++) { 1585 dma_addr_t addr; 1586 1587 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE, 1588 DMA_BIDIRECTIONAL); 1589 1590 if (dma_mapping_error(dev, addr)) { 1591 while (i--) { 1592 dma_unmap_page(dev, ttm_dma->dma_address[i], 1593 PAGE_SIZE, DMA_BIDIRECTIONAL); 1594 ttm_dma->dma_address[i] = 0; 1595 } 1596 ttm_pool_unpopulate(ttm); 1597 return -EFAULT; 1598 } 1599 1600 ttm_dma->dma_address[i] = addr; 1601 } 1602 return 0; 1603 } 1604 1605 static void 1606 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) 1607 { 1608 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1609 struct nouveau_drm *drm; 1610 struct device *dev; 1611 unsigned i; 1612 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1613 1614 if (slave) 1615 return; 1616 1617 drm = nouveau_bdev(ttm->bdev); 1618 dev = drm->dev->dev; 1619 1620 #if IS_ENABLED(CONFIG_AGP) 1621 if (drm->agp.bridge) { 1622 ttm_agp_tt_unpopulate(ttm); 1623 return; 1624 } 1625 #endif 1626 1627 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1628 if (swiotlb_nr_tbl()) { 1629 ttm_dma_unpopulate((void *)ttm, dev); 1630 return; 1631 } 1632 #endif 1633 1634 for (i = 0; i < ttm->num_pages; i++) { 1635 if (ttm_dma->dma_address[i]) { 1636 dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE, 1637 DMA_BIDIRECTIONAL); 1638 } 1639 } 1640 1641 ttm_pool_unpopulate(ttm); 1642 } 1643 1644 void 1645 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1646 { 1647 struct reservation_object *resv = nvbo->bo.resv; 1648 1649 if (exclusive) 1650 reservation_object_add_excl_fence(resv, &fence->base); 1651 else if (fence) 1652 reservation_object_add_shared_fence(resv, &fence->base); 1653 } 1654 1655 struct ttm_bo_driver nouveau_bo_driver = { 1656 .ttm_tt_create = &nouveau_ttm_tt_create, 1657 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1658 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1659 .invalidate_caches = nouveau_bo_invalidate_caches, 1660 .init_mem_type = nouveau_bo_init_mem_type, 1661 .eviction_valuable = ttm_bo_eviction_valuable, 1662 .evict_flags = nouveau_bo_evict_flags, 1663 .move_notify = nouveau_bo_move_ntfy, 1664 .move = nouveau_bo_move, 1665 .verify_access = nouveau_bo_verify_access, 1666 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, 1667 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1668 .io_mem_free = &nouveau_ttm_io_mem_free, 1669 .io_mem_pfn = ttm_bo_default_io_mem_pfn, 1670 }; 1671