1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 #include <linux/swiotlb.h> 32 33 #include "nouveau_drv.h" 34 #include "nouveau_dma.h" 35 #include "nouveau_fence.h" 36 37 #include "nouveau_bo.h" 38 #include "nouveau_ttm.h" 39 #include "nouveau_gem.h" 40 #include "nouveau_mem.h" 41 #include "nouveau_vmm.h" 42 43 #include <nvif/class.h> 44 #include <nvif/if500b.h> 45 #include <nvif/if900b.h> 46 47 /* 48 * NV10-NV40 tiling helpers 49 */ 50 51 static void 52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 53 u32 addr, u32 size, u32 pitch, u32 flags) 54 { 55 struct nouveau_drm *drm = nouveau_drm(dev); 56 int i = reg - drm->tile.reg; 57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 58 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 59 60 nouveau_fence_unref(®->fence); 61 62 if (tile->pitch) 63 nvkm_fb_tile_fini(fb, i, tile); 64 65 if (pitch) 66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 67 68 nvkm_fb_tile_prog(fb, i, tile); 69 } 70 71 static struct nouveau_drm_tile * 72 nv10_bo_get_tile_region(struct drm_device *dev, int i) 73 { 74 struct nouveau_drm *drm = nouveau_drm(dev); 75 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 76 77 spin_lock(&drm->tile.lock); 78 79 if (!tile->used && 80 (!tile->fence || nouveau_fence_done(tile->fence))) 81 tile->used = true; 82 else 83 tile = NULL; 84 85 spin_unlock(&drm->tile.lock); 86 return tile; 87 } 88 89 static void 90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 91 struct dma_fence *fence) 92 { 93 struct nouveau_drm *drm = nouveau_drm(dev); 94 95 if (tile) { 96 spin_lock(&drm->tile.lock); 97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 98 tile->used = false; 99 spin_unlock(&drm->tile.lock); 100 } 101 } 102 103 static struct nouveau_drm_tile * 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 105 u32 size, u32 pitch, u32 zeta) 106 { 107 struct nouveau_drm *drm = nouveau_drm(dev); 108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 109 struct nouveau_drm_tile *tile, *found = NULL; 110 int i; 111 112 for (i = 0; i < fb->tile.regions; i++) { 113 tile = nv10_bo_get_tile_region(dev, i); 114 115 if (pitch && !found) { 116 found = tile; 117 continue; 118 119 } else if (tile && fb->tile.region[i].pitch) { 120 /* Kill an unused tile region. */ 121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 122 } 123 124 nv10_bo_put_tile_region(dev, tile, NULL); 125 } 126 127 if (found) 128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 129 return found; 130 } 131 132 static void 133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 134 { 135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 136 struct drm_device *dev = drm->dev; 137 struct nouveau_bo *nvbo = nouveau_bo(bo); 138 139 if (unlikely(nvbo->gem.filp)) 140 DRM_ERROR("bo %p still attached to GEM object\n", bo); 141 WARN_ON(nvbo->pin_refcnt > 0); 142 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 143 kfree(nvbo); 144 } 145 146 static inline u64 147 roundup_64(u64 x, u32 y) 148 { 149 x += y - 1; 150 do_div(x, y); 151 return x * y; 152 } 153 154 static void 155 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, 156 int *align, u64 *size) 157 { 158 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 159 struct nvif_device *device = &drm->client.device; 160 161 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 162 if (nvbo->mode) { 163 if (device->info.chipset >= 0x40) { 164 *align = 65536; 165 *size = roundup_64(*size, 64 * nvbo->mode); 166 167 } else if (device->info.chipset >= 0x30) { 168 *align = 32768; 169 *size = roundup_64(*size, 64 * nvbo->mode); 170 171 } else if (device->info.chipset >= 0x20) { 172 *align = 16384; 173 *size = roundup_64(*size, 64 * nvbo->mode); 174 175 } else if (device->info.chipset >= 0x10) { 176 *align = 16384; 177 *size = roundup_64(*size, 32 * nvbo->mode); 178 } 179 } 180 } else { 181 *size = roundup_64(*size, (1 << nvbo->page)); 182 *align = max((1 << nvbo->page), *align); 183 } 184 185 *size = roundup_64(*size, PAGE_SIZE); 186 } 187 188 int 189 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 190 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, 191 struct sg_table *sg, struct reservation_object *robj, 192 struct nouveau_bo **pnvbo) 193 { 194 struct nouveau_drm *drm = cli->drm; 195 struct nouveau_bo *nvbo; 196 struct nvif_mmu *mmu = &cli->mmu; 197 struct nvif_vmm *vmm = &cli->vmm.vmm; 198 size_t acc_size; 199 int type = ttm_bo_type_device; 200 int ret, i, pi = -1; 201 202 if (!size) { 203 NV_WARN(drm, "skipped size %016llx\n", size); 204 return -EINVAL; 205 } 206 207 if (sg) 208 type = ttm_bo_type_sg; 209 210 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 211 if (!nvbo) 212 return -ENOMEM; 213 INIT_LIST_HEAD(&nvbo->head); 214 INIT_LIST_HEAD(&nvbo->entry); 215 INIT_LIST_HEAD(&nvbo->vma_list); 216 nvbo->bo.bdev = &drm->ttm.bdev; 217 218 /* This is confusing, and doesn't actually mean we want an uncached 219 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 220 * into in nouveau_gem_new(). 221 */ 222 if (flags & TTM_PL_FLAG_UNCACHED) { 223 /* Determine if we can get a cache-coherent map, forcing 224 * uncached mapping if we can't. 225 */ 226 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 227 nvbo->force_coherent = true; 228 } 229 230 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 231 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 232 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 233 kfree(nvbo); 234 return -EINVAL; 235 } 236 237 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 238 } else 239 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 240 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 241 nvbo->comp = (tile_flags & 0x00030000) >> 16; 242 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 243 kfree(nvbo); 244 return -EINVAL; 245 } 246 } else { 247 nvbo->zeta = (tile_flags & 0x00000007); 248 } 249 nvbo->mode = tile_mode; 250 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 251 252 /* Determine the desirable target GPU page size for the buffer. */ 253 for (i = 0; i < vmm->page_nr; i++) { 254 /* Because we cannot currently allow VMM maps to fail 255 * during buffer migration, we need to determine page 256 * size for the buffer up-front, and pre-allocate its 257 * page tables. 258 * 259 * Skip page sizes that can't support needed domains. 260 */ 261 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 262 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram) 263 continue; 264 if ((flags & TTM_PL_FLAG_TT) && 265 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 266 continue; 267 268 /* Select this page size if it's the first that supports 269 * the potential memory domains, or when it's compatible 270 * with the requested compression settings. 271 */ 272 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 273 pi = i; 274 275 /* Stop once the buffer is larger than the current page size. */ 276 if (size >= 1ULL << vmm->page[i].shift) 277 break; 278 } 279 280 if (WARN_ON(pi < 0)) 281 return -EINVAL; 282 283 /* Disable compression if suitable settings couldn't be found. */ 284 if (nvbo->comp && !vmm->page[pi].comp) { 285 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 286 nvbo->kind = mmu->kind[nvbo->kind]; 287 nvbo->comp = 0; 288 } 289 nvbo->page = vmm->page[pi].shift; 290 291 nouveau_bo_fixup_align(nvbo, flags, &align, &size); 292 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; 293 nouveau_bo_placement_set(nvbo, flags, 0); 294 295 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, 296 sizeof(struct nouveau_bo)); 297 298 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, 299 type, &nvbo->placement, 300 align >> PAGE_SHIFT, false, acc_size, sg, 301 robj, nouveau_bo_del_ttm); 302 if (ret) { 303 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 304 return ret; 305 } 306 307 *pnvbo = nvbo; 308 return 0; 309 } 310 311 static void 312 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) 313 { 314 *n = 0; 315 316 if (type & TTM_PL_FLAG_VRAM) 317 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; 318 if (type & TTM_PL_FLAG_TT) 319 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; 320 if (type & TTM_PL_FLAG_SYSTEM) 321 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; 322 } 323 324 static void 325 set_placement_range(struct nouveau_bo *nvbo, uint32_t type) 326 { 327 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 328 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; 329 unsigned i, fpfn, lpfn; 330 331 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 332 nvbo->mode && (type & TTM_PL_FLAG_VRAM) && 333 nvbo->bo.mem.num_pages < vram_pages / 4) { 334 /* 335 * Make sure that the color and depth buffers are handled 336 * by independent memory controller units. Up to a 9x 337 * speed up when alpha-blending and depth-test are enabled 338 * at the same time. 339 */ 340 if (nvbo->zeta) { 341 fpfn = vram_pages / 2; 342 lpfn = ~0; 343 } else { 344 fpfn = 0; 345 lpfn = vram_pages / 2; 346 } 347 for (i = 0; i < nvbo->placement.num_placement; ++i) { 348 nvbo->placements[i].fpfn = fpfn; 349 nvbo->placements[i].lpfn = lpfn; 350 } 351 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 352 nvbo->busy_placements[i].fpfn = fpfn; 353 nvbo->busy_placements[i].lpfn = lpfn; 354 } 355 } 356 } 357 358 void 359 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) 360 { 361 struct ttm_placement *pl = &nvbo->placement; 362 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : 363 TTM_PL_MASK_CACHING) | 364 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); 365 366 pl->placement = nvbo->placements; 367 set_placement_list(nvbo->placements, &pl->num_placement, 368 type, flags); 369 370 pl->busy_placement = nvbo->busy_placements; 371 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 372 type | busy, flags); 373 374 set_placement_range(nvbo, type); 375 } 376 377 int 378 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) 379 { 380 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 381 struct ttm_buffer_object *bo = &nvbo->bo; 382 bool force = false, evict = false; 383 int ret; 384 385 ret = ttm_bo_reserve(bo, false, false, NULL); 386 if (ret) 387 return ret; 388 389 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 390 memtype == TTM_PL_FLAG_VRAM && contig) { 391 if (!nvbo->contig) { 392 nvbo->contig = true; 393 force = true; 394 evict = true; 395 } 396 } 397 398 if (nvbo->pin_refcnt) { 399 if (!(memtype & (1 << bo->mem.mem_type)) || evict) { 400 NV_ERROR(drm, "bo %p pinned elsewhere: " 401 "0x%08x vs 0x%08x\n", bo, 402 1 << bo->mem.mem_type, memtype); 403 ret = -EBUSY; 404 } 405 nvbo->pin_refcnt++; 406 goto out; 407 } 408 409 if (evict) { 410 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); 411 ret = nouveau_bo_validate(nvbo, false, false); 412 if (ret) 413 goto out; 414 } 415 416 nvbo->pin_refcnt++; 417 nouveau_bo_placement_set(nvbo, memtype, 0); 418 419 /* drop pin_refcnt temporarily, so we don't trip the assertion 420 * in nouveau_bo_move() that makes sure we're not trying to 421 * move a pinned buffer 422 */ 423 nvbo->pin_refcnt--; 424 ret = nouveau_bo_validate(nvbo, false, false); 425 if (ret) 426 goto out; 427 nvbo->pin_refcnt++; 428 429 switch (bo->mem.mem_type) { 430 case TTM_PL_VRAM: 431 drm->gem.vram_available -= bo->mem.size; 432 break; 433 case TTM_PL_TT: 434 drm->gem.gart_available -= bo->mem.size; 435 break; 436 default: 437 break; 438 } 439 440 out: 441 if (force && ret) 442 nvbo->contig = false; 443 ttm_bo_unreserve(bo); 444 return ret; 445 } 446 447 int 448 nouveau_bo_unpin(struct nouveau_bo *nvbo) 449 { 450 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 451 struct ttm_buffer_object *bo = &nvbo->bo; 452 int ret, ref; 453 454 ret = ttm_bo_reserve(bo, false, false, NULL); 455 if (ret) 456 return ret; 457 458 ref = --nvbo->pin_refcnt; 459 WARN_ON_ONCE(ref < 0); 460 if (ref) 461 goto out; 462 463 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); 464 465 ret = nouveau_bo_validate(nvbo, false, false); 466 if (ret == 0) { 467 switch (bo->mem.mem_type) { 468 case TTM_PL_VRAM: 469 drm->gem.vram_available += bo->mem.size; 470 break; 471 case TTM_PL_TT: 472 drm->gem.gart_available += bo->mem.size; 473 break; 474 default: 475 break; 476 } 477 } 478 479 out: 480 ttm_bo_unreserve(bo); 481 return ret; 482 } 483 484 int 485 nouveau_bo_map(struct nouveau_bo *nvbo) 486 { 487 int ret; 488 489 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 490 if (ret) 491 return ret; 492 493 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 494 495 ttm_bo_unreserve(&nvbo->bo); 496 return ret; 497 } 498 499 void 500 nouveau_bo_unmap(struct nouveau_bo *nvbo) 501 { 502 if (!nvbo) 503 return; 504 505 ttm_bo_kunmap(&nvbo->kmap); 506 } 507 508 void 509 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 510 { 511 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 512 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 513 int i; 514 515 if (!ttm_dma) 516 return; 517 518 /* Don't waste time looping if the object is coherent */ 519 if (nvbo->force_coherent) 520 return; 521 522 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 523 dma_sync_single_for_device(drm->dev->dev, 524 ttm_dma->dma_address[i], 525 PAGE_SIZE, DMA_TO_DEVICE); 526 } 527 528 void 529 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 530 { 531 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 532 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 533 int i; 534 535 if (!ttm_dma) 536 return; 537 538 /* Don't waste time looping if the object is coherent */ 539 if (nvbo->force_coherent) 540 return; 541 542 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 543 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 544 PAGE_SIZE, DMA_FROM_DEVICE); 545 } 546 547 int 548 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 549 bool no_wait_gpu) 550 { 551 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 552 int ret; 553 554 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 555 if (ret) 556 return ret; 557 558 nouveau_bo_sync_for_device(nvbo); 559 560 return 0; 561 } 562 563 void 564 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 565 { 566 bool is_iomem; 567 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 568 569 mem += index; 570 571 if (is_iomem) 572 iowrite16_native(val, (void __force __iomem *)mem); 573 else 574 *mem = val; 575 } 576 577 u32 578 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 579 { 580 bool is_iomem; 581 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 582 583 mem += index; 584 585 if (is_iomem) 586 return ioread32_native((void __force __iomem *)mem); 587 else 588 return *mem; 589 } 590 591 void 592 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 593 { 594 bool is_iomem; 595 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 596 597 mem += index; 598 599 if (is_iomem) 600 iowrite32_native(val, (void __force __iomem *)mem); 601 else 602 *mem = val; 603 } 604 605 static struct ttm_tt * 606 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 607 { 608 #if IS_ENABLED(CONFIG_AGP) 609 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 610 611 if (drm->agp.bridge) { 612 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 613 } 614 #endif 615 616 return nouveau_sgdma_create_ttm(bo, page_flags); 617 } 618 619 static int 620 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 621 { 622 /* We'll do this from user space. */ 623 return 0; 624 } 625 626 static int 627 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 628 struct ttm_mem_type_manager *man) 629 { 630 struct nouveau_drm *drm = nouveau_bdev(bdev); 631 struct nvif_mmu *mmu = &drm->client.mmu; 632 633 switch (type) { 634 case TTM_PL_SYSTEM: 635 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 636 man->available_caching = TTM_PL_MASK_CACHING; 637 man->default_caching = TTM_PL_FLAG_CACHED; 638 break; 639 case TTM_PL_VRAM: 640 man->flags = TTM_MEMTYPE_FLAG_FIXED | 641 TTM_MEMTYPE_FLAG_MAPPABLE; 642 man->available_caching = TTM_PL_FLAG_UNCACHED | 643 TTM_PL_FLAG_WC; 644 man->default_caching = TTM_PL_FLAG_WC; 645 646 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 647 /* Some BARs do not support being ioremapped WC */ 648 const u8 type = mmu->type[drm->ttm.type_vram].type; 649 if (type & NVIF_MEM_UNCACHED) { 650 man->available_caching = TTM_PL_FLAG_UNCACHED; 651 man->default_caching = TTM_PL_FLAG_UNCACHED; 652 } 653 654 man->func = &nouveau_vram_manager; 655 man->io_reserve_fastpath = false; 656 man->use_io_reserve_lru = true; 657 } else { 658 man->func = &ttm_bo_manager_func; 659 } 660 break; 661 case TTM_PL_TT: 662 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) 663 man->func = &nouveau_gart_manager; 664 else 665 if (!drm->agp.bridge) 666 man->func = &nv04_gart_manager; 667 else 668 man->func = &ttm_bo_manager_func; 669 670 if (drm->agp.bridge) { 671 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 672 man->available_caching = TTM_PL_FLAG_UNCACHED | 673 TTM_PL_FLAG_WC; 674 man->default_caching = TTM_PL_FLAG_WC; 675 } else { 676 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | 677 TTM_MEMTYPE_FLAG_CMA; 678 man->available_caching = TTM_PL_MASK_CACHING; 679 man->default_caching = TTM_PL_FLAG_CACHED; 680 } 681 682 break; 683 default: 684 return -EINVAL; 685 } 686 return 0; 687 } 688 689 static void 690 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 691 { 692 struct nouveau_bo *nvbo = nouveau_bo(bo); 693 694 switch (bo->mem.mem_type) { 695 case TTM_PL_VRAM: 696 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 697 TTM_PL_FLAG_SYSTEM); 698 break; 699 default: 700 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); 701 break; 702 } 703 704 *pl = nvbo->placement; 705 } 706 707 708 static int 709 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) 710 { 711 int ret = RING_SPACE(chan, 2); 712 if (ret == 0) { 713 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 714 OUT_RING (chan, handle & 0x0000ffff); 715 FIRE_RING (chan); 716 } 717 return ret; 718 } 719 720 static int 721 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 722 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 723 { 724 struct nouveau_mem *mem = nouveau_mem(old_reg); 725 int ret = RING_SPACE(chan, 10); 726 if (ret == 0) { 727 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); 728 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 729 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 730 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 731 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 732 OUT_RING (chan, PAGE_SIZE); 733 OUT_RING (chan, PAGE_SIZE); 734 OUT_RING (chan, PAGE_SIZE); 735 OUT_RING (chan, new_reg->num_pages); 736 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); 737 } 738 return ret; 739 } 740 741 static int 742 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) 743 { 744 int ret = RING_SPACE(chan, 2); 745 if (ret == 0) { 746 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 747 OUT_RING (chan, handle); 748 } 749 return ret; 750 } 751 752 static int 753 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 754 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 755 { 756 struct nouveau_mem *mem = nouveau_mem(old_reg); 757 u64 src_offset = mem->vma[0].addr; 758 u64 dst_offset = mem->vma[1].addr; 759 u32 page_count = new_reg->num_pages; 760 int ret; 761 762 page_count = new_reg->num_pages; 763 while (page_count) { 764 int line_count = (page_count > 8191) ? 8191 : page_count; 765 766 ret = RING_SPACE(chan, 11); 767 if (ret) 768 return ret; 769 770 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); 771 OUT_RING (chan, upper_32_bits(src_offset)); 772 OUT_RING (chan, lower_32_bits(src_offset)); 773 OUT_RING (chan, upper_32_bits(dst_offset)); 774 OUT_RING (chan, lower_32_bits(dst_offset)); 775 OUT_RING (chan, PAGE_SIZE); 776 OUT_RING (chan, PAGE_SIZE); 777 OUT_RING (chan, PAGE_SIZE); 778 OUT_RING (chan, line_count); 779 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 780 OUT_RING (chan, 0x00000110); 781 782 page_count -= line_count; 783 src_offset += (PAGE_SIZE * line_count); 784 dst_offset += (PAGE_SIZE * line_count); 785 } 786 787 return 0; 788 } 789 790 static int 791 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 792 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 793 { 794 struct nouveau_mem *mem = nouveau_mem(old_reg); 795 u64 src_offset = mem->vma[0].addr; 796 u64 dst_offset = mem->vma[1].addr; 797 u32 page_count = new_reg->num_pages; 798 int ret; 799 800 page_count = new_reg->num_pages; 801 while (page_count) { 802 int line_count = (page_count > 2047) ? 2047 : page_count; 803 804 ret = RING_SPACE(chan, 12); 805 if (ret) 806 return ret; 807 808 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); 809 OUT_RING (chan, upper_32_bits(dst_offset)); 810 OUT_RING (chan, lower_32_bits(dst_offset)); 811 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); 812 OUT_RING (chan, upper_32_bits(src_offset)); 813 OUT_RING (chan, lower_32_bits(src_offset)); 814 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 815 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 816 OUT_RING (chan, PAGE_SIZE); /* line_length */ 817 OUT_RING (chan, line_count); 818 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 819 OUT_RING (chan, 0x00100110); 820 821 page_count -= line_count; 822 src_offset += (PAGE_SIZE * line_count); 823 dst_offset += (PAGE_SIZE * line_count); 824 } 825 826 return 0; 827 } 828 829 static int 830 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 831 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 832 { 833 struct nouveau_mem *mem = nouveau_mem(old_reg); 834 u64 src_offset = mem->vma[0].addr; 835 u64 dst_offset = mem->vma[1].addr; 836 u32 page_count = new_reg->num_pages; 837 int ret; 838 839 page_count = new_reg->num_pages; 840 while (page_count) { 841 int line_count = (page_count > 8191) ? 8191 : page_count; 842 843 ret = RING_SPACE(chan, 11); 844 if (ret) 845 return ret; 846 847 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 848 OUT_RING (chan, upper_32_bits(src_offset)); 849 OUT_RING (chan, lower_32_bits(src_offset)); 850 OUT_RING (chan, upper_32_bits(dst_offset)); 851 OUT_RING (chan, lower_32_bits(dst_offset)); 852 OUT_RING (chan, PAGE_SIZE); 853 OUT_RING (chan, PAGE_SIZE); 854 OUT_RING (chan, PAGE_SIZE); 855 OUT_RING (chan, line_count); 856 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); 857 OUT_RING (chan, 0x00000110); 858 859 page_count -= line_count; 860 src_offset += (PAGE_SIZE * line_count); 861 dst_offset += (PAGE_SIZE * line_count); 862 } 863 864 return 0; 865 } 866 867 static int 868 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 869 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 870 { 871 struct nouveau_mem *mem = nouveau_mem(old_reg); 872 int ret = RING_SPACE(chan, 7); 873 if (ret == 0) { 874 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); 875 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 876 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 877 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 878 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 879 OUT_RING (chan, 0x00000000 /* COPY */); 880 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 881 } 882 return ret; 883 } 884 885 static int 886 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 887 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 888 { 889 struct nouveau_mem *mem = nouveau_mem(old_reg); 890 int ret = RING_SPACE(chan, 7); 891 if (ret == 0) { 892 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); 893 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 894 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 895 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 896 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 897 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 898 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); 899 } 900 return ret; 901 } 902 903 static int 904 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) 905 { 906 int ret = RING_SPACE(chan, 6); 907 if (ret == 0) { 908 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 909 OUT_RING (chan, handle); 910 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); 911 OUT_RING (chan, chan->drm->ntfy.handle); 912 OUT_RING (chan, chan->vram.handle); 913 OUT_RING (chan, chan->vram.handle); 914 } 915 916 return ret; 917 } 918 919 static int 920 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 921 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 922 { 923 struct nouveau_mem *mem = nouveau_mem(old_reg); 924 u64 length = (new_reg->num_pages << PAGE_SHIFT); 925 u64 src_offset = mem->vma[0].addr; 926 u64 dst_offset = mem->vma[1].addr; 927 int src_tiled = !!mem->kind; 928 int dst_tiled = !!nouveau_mem(new_reg)->kind; 929 int ret; 930 931 while (length) { 932 u32 amount, stride, height; 933 934 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); 935 if (ret) 936 return ret; 937 938 amount = min(length, (u64)(4 * 1024 * 1024)); 939 stride = 16 * 4; 940 height = amount / stride; 941 942 if (src_tiled) { 943 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); 944 OUT_RING (chan, 0); 945 OUT_RING (chan, 0); 946 OUT_RING (chan, stride); 947 OUT_RING (chan, height); 948 OUT_RING (chan, 1); 949 OUT_RING (chan, 0); 950 OUT_RING (chan, 0); 951 } else { 952 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); 953 OUT_RING (chan, 1); 954 } 955 if (dst_tiled) { 956 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); 957 OUT_RING (chan, 0); 958 OUT_RING (chan, 0); 959 OUT_RING (chan, stride); 960 OUT_RING (chan, height); 961 OUT_RING (chan, 1); 962 OUT_RING (chan, 0); 963 OUT_RING (chan, 0); 964 } else { 965 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); 966 OUT_RING (chan, 1); 967 } 968 969 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); 970 OUT_RING (chan, upper_32_bits(src_offset)); 971 OUT_RING (chan, upper_32_bits(dst_offset)); 972 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 973 OUT_RING (chan, lower_32_bits(src_offset)); 974 OUT_RING (chan, lower_32_bits(dst_offset)); 975 OUT_RING (chan, stride); 976 OUT_RING (chan, stride); 977 OUT_RING (chan, stride); 978 OUT_RING (chan, height); 979 OUT_RING (chan, 0x00000101); 980 OUT_RING (chan, 0x00000000); 981 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 982 OUT_RING (chan, 0); 983 984 length -= amount; 985 src_offset += amount; 986 dst_offset += amount; 987 } 988 989 return 0; 990 } 991 992 static int 993 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) 994 { 995 int ret = RING_SPACE(chan, 4); 996 if (ret == 0) { 997 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 998 OUT_RING (chan, handle); 999 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); 1000 OUT_RING (chan, chan->drm->ntfy.handle); 1001 } 1002 1003 return ret; 1004 } 1005 1006 static inline uint32_t 1007 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, 1008 struct nouveau_channel *chan, struct ttm_mem_reg *reg) 1009 { 1010 if (reg->mem_type == TTM_PL_TT) 1011 return NvDmaTT; 1012 return chan->vram.handle; 1013 } 1014 1015 static int 1016 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 1017 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 1018 { 1019 u32 src_offset = old_reg->start << PAGE_SHIFT; 1020 u32 dst_offset = new_reg->start << PAGE_SHIFT; 1021 u32 page_count = new_reg->num_pages; 1022 int ret; 1023 1024 ret = RING_SPACE(chan, 3); 1025 if (ret) 1026 return ret; 1027 1028 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); 1029 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); 1030 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); 1031 1032 page_count = new_reg->num_pages; 1033 while (page_count) { 1034 int line_count = (page_count > 2047) ? 2047 : page_count; 1035 1036 ret = RING_SPACE(chan, 11); 1037 if (ret) 1038 return ret; 1039 1040 BEGIN_NV04(chan, NvSubCopy, 1041 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 1042 OUT_RING (chan, src_offset); 1043 OUT_RING (chan, dst_offset); 1044 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 1045 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 1046 OUT_RING (chan, PAGE_SIZE); /* line_length */ 1047 OUT_RING (chan, line_count); 1048 OUT_RING (chan, 0x00000101); 1049 OUT_RING (chan, 0x00000000); 1050 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 1051 OUT_RING (chan, 0); 1052 1053 page_count -= line_count; 1054 src_offset += (PAGE_SIZE * line_count); 1055 dst_offset += (PAGE_SIZE * line_count); 1056 } 1057 1058 return 0; 1059 } 1060 1061 static int 1062 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 1063 struct ttm_mem_reg *reg) 1064 { 1065 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 1066 struct nouveau_mem *new_mem = nouveau_mem(reg); 1067 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 1068 int ret; 1069 1070 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 1071 old_mem->mem.size, &old_mem->vma[0]); 1072 if (ret) 1073 return ret; 1074 1075 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 1076 new_mem->mem.size, &old_mem->vma[1]); 1077 if (ret) 1078 goto done; 1079 1080 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 1081 if (ret) 1082 goto done; 1083 1084 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 1085 done: 1086 if (ret) { 1087 nvif_vmm_put(vmm, &old_mem->vma[1]); 1088 nvif_vmm_put(vmm, &old_mem->vma[0]); 1089 } 1090 return 0; 1091 } 1092 1093 static int 1094 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, 1095 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1096 { 1097 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1098 struct nouveau_channel *chan = drm->ttm.chan; 1099 struct nouveau_cli *cli = (void *)chan->user.client; 1100 struct nouveau_fence *fence; 1101 int ret; 1102 1103 /* create temporary vmas for the transfer and attach them to the 1104 * old nvkm_mem node, these will get cleaned up after ttm has 1105 * destroyed the ttm_mem_reg 1106 */ 1107 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 1108 ret = nouveau_bo_move_prep(drm, bo, new_reg); 1109 if (ret) 1110 return ret; 1111 } 1112 1113 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 1114 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); 1115 if (ret == 0) { 1116 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 1117 if (ret == 0) { 1118 ret = nouveau_fence_new(chan, false, &fence); 1119 if (ret == 0) { 1120 ret = ttm_bo_move_accel_cleanup(bo, 1121 &fence->base, 1122 evict, 1123 new_reg); 1124 nouveau_fence_unref(&fence); 1125 } 1126 } 1127 } 1128 mutex_unlock(&cli->mutex); 1129 return ret; 1130 } 1131 1132 void 1133 nouveau_bo_move_init(struct nouveau_drm *drm) 1134 { 1135 static const struct { 1136 const char *name; 1137 int engine; 1138 s32 oclass; 1139 int (*exec)(struct nouveau_channel *, 1140 struct ttm_buffer_object *, 1141 struct ttm_mem_reg *, struct ttm_mem_reg *); 1142 int (*init)(struct nouveau_channel *, u32 handle); 1143 } _methods[] = { 1144 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 1145 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1146 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 1147 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1148 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1149 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1150 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1151 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1152 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1153 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1154 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 1155 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 1156 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 1157 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 1158 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 1159 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 1160 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 1161 {}, 1162 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, 1163 }, *mthd = _methods; 1164 const char *name = "CPU"; 1165 int ret; 1166 1167 do { 1168 struct nouveau_channel *chan; 1169 1170 if (mthd->engine) 1171 chan = drm->cechan; 1172 else 1173 chan = drm->channel; 1174 if (chan == NULL) 1175 continue; 1176 1177 ret = nvif_object_init(&chan->user, 1178 mthd->oclass | (mthd->engine << 16), 1179 mthd->oclass, NULL, 0, 1180 &drm->ttm.copy); 1181 if (ret == 0) { 1182 ret = mthd->init(chan, drm->ttm.copy.handle); 1183 if (ret) { 1184 nvif_object_fini(&drm->ttm.copy); 1185 continue; 1186 } 1187 1188 drm->ttm.move = mthd->exec; 1189 drm->ttm.chan = chan; 1190 name = mthd->name; 1191 break; 1192 } 1193 } while ((++mthd)->exec); 1194 1195 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 1196 } 1197 1198 static int 1199 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 1200 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1201 { 1202 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1203 struct ttm_place placement_memtype = { 1204 .fpfn = 0, 1205 .lpfn = 0, 1206 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1207 }; 1208 struct ttm_placement placement; 1209 struct ttm_mem_reg tmp_reg; 1210 int ret; 1211 1212 placement.num_placement = placement.num_busy_placement = 1; 1213 placement.placement = placement.busy_placement = &placement_memtype; 1214 1215 tmp_reg = *new_reg; 1216 tmp_reg.mm_node = NULL; 1217 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1218 if (ret) 1219 return ret; 1220 1221 ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx); 1222 if (ret) 1223 goto out; 1224 1225 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); 1226 if (ret) 1227 goto out; 1228 1229 ret = ttm_bo_move_ttm(bo, &ctx, new_reg); 1230 out: 1231 ttm_bo_mem_put(bo, &tmp_reg); 1232 return ret; 1233 } 1234 1235 static int 1236 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 1237 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1238 { 1239 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1240 struct ttm_place placement_memtype = { 1241 .fpfn = 0, 1242 .lpfn = 0, 1243 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1244 }; 1245 struct ttm_placement placement; 1246 struct ttm_mem_reg tmp_reg; 1247 int ret; 1248 1249 placement.num_placement = placement.num_busy_placement = 1; 1250 placement.placement = placement.busy_placement = &placement_memtype; 1251 1252 tmp_reg = *new_reg; 1253 tmp_reg.mm_node = NULL; 1254 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1255 if (ret) 1256 return ret; 1257 1258 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg); 1259 if (ret) 1260 goto out; 1261 1262 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); 1263 if (ret) 1264 goto out; 1265 1266 out: 1267 ttm_bo_mem_put(bo, &tmp_reg); 1268 return ret; 1269 } 1270 1271 static void 1272 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, 1273 struct ttm_mem_reg *new_reg) 1274 { 1275 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 1276 struct nouveau_bo *nvbo = nouveau_bo(bo); 1277 struct nouveau_vma *vma; 1278 1279 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 1280 if (bo->destroy != nouveau_bo_del_ttm) 1281 return; 1282 1283 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 1284 mem->mem.page == nvbo->page) { 1285 list_for_each_entry(vma, &nvbo->vma_list, head) { 1286 nouveau_vma_map(vma, mem); 1287 } 1288 } else { 1289 list_for_each_entry(vma, &nvbo->vma_list, head) { 1290 WARN_ON(ttm_bo_wait(bo, false, false)); 1291 nouveau_vma_unmap(vma); 1292 } 1293 } 1294 } 1295 1296 static int 1297 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg, 1298 struct nouveau_drm_tile **new_tile) 1299 { 1300 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1301 struct drm_device *dev = drm->dev; 1302 struct nouveau_bo *nvbo = nouveau_bo(bo); 1303 u64 offset = new_reg->start << PAGE_SHIFT; 1304 1305 *new_tile = NULL; 1306 if (new_reg->mem_type != TTM_PL_VRAM) 1307 return 0; 1308 1309 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 1310 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, 1311 nvbo->mode, nvbo->zeta); 1312 } 1313 1314 return 0; 1315 } 1316 1317 static void 1318 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 1319 struct nouveau_drm_tile *new_tile, 1320 struct nouveau_drm_tile **old_tile) 1321 { 1322 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1323 struct drm_device *dev = drm->dev; 1324 struct dma_fence *fence = reservation_object_get_excl(bo->resv); 1325 1326 nv10_bo_put_tile_region(dev, *old_tile, fence); 1327 *old_tile = new_tile; 1328 } 1329 1330 static int 1331 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 1332 struct ttm_operation_ctx *ctx, 1333 struct ttm_mem_reg *new_reg) 1334 { 1335 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1336 struct nouveau_bo *nvbo = nouveau_bo(bo); 1337 struct ttm_mem_reg *old_reg = &bo->mem; 1338 struct nouveau_drm_tile *new_tile = NULL; 1339 int ret = 0; 1340 1341 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1342 if (ret) 1343 return ret; 1344 1345 if (nvbo->pin_refcnt) 1346 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 1347 1348 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1349 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 1350 if (ret) 1351 return ret; 1352 } 1353 1354 /* Fake bo copy. */ 1355 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 1356 BUG_ON(bo->mem.mm_node != NULL); 1357 bo->mem = *new_reg; 1358 new_reg->mm_node = NULL; 1359 goto out; 1360 } 1361 1362 /* Hardware assisted copy. */ 1363 if (drm->ttm.move) { 1364 if (new_reg->mem_type == TTM_PL_SYSTEM) 1365 ret = nouveau_bo_move_flipd(bo, evict, 1366 ctx->interruptible, 1367 ctx->no_wait_gpu, new_reg); 1368 else if (old_reg->mem_type == TTM_PL_SYSTEM) 1369 ret = nouveau_bo_move_flips(bo, evict, 1370 ctx->interruptible, 1371 ctx->no_wait_gpu, new_reg); 1372 else 1373 ret = nouveau_bo_move_m2mf(bo, evict, 1374 ctx->interruptible, 1375 ctx->no_wait_gpu, new_reg); 1376 if (!ret) 1377 goto out; 1378 } 1379 1380 /* Fallback to software copy. */ 1381 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1382 if (ret == 0) 1383 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1384 1385 out: 1386 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1387 if (ret) 1388 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1389 else 1390 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1391 } 1392 1393 return ret; 1394 } 1395 1396 static int 1397 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 1398 { 1399 struct nouveau_bo *nvbo = nouveau_bo(bo); 1400 1401 return drm_vma_node_verify_access(&nvbo->gem.vma_node, 1402 filp->private_data); 1403 } 1404 1405 static int 1406 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1407 { 1408 struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type]; 1409 struct nouveau_drm *drm = nouveau_bdev(bdev); 1410 struct nvkm_device *device = nvxx_device(&drm->client.device); 1411 struct nouveau_mem *mem = nouveau_mem(reg); 1412 1413 reg->bus.addr = NULL; 1414 reg->bus.offset = 0; 1415 reg->bus.size = reg->num_pages << PAGE_SHIFT; 1416 reg->bus.base = 0; 1417 reg->bus.is_iomem = false; 1418 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 1419 return -EINVAL; 1420 switch (reg->mem_type) { 1421 case TTM_PL_SYSTEM: 1422 /* System memory */ 1423 return 0; 1424 case TTM_PL_TT: 1425 #if IS_ENABLED(CONFIG_AGP) 1426 if (drm->agp.bridge) { 1427 reg->bus.offset = reg->start << PAGE_SHIFT; 1428 reg->bus.base = drm->agp.base; 1429 reg->bus.is_iomem = !drm->agp.cma; 1430 } 1431 #endif 1432 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) 1433 /* untiled */ 1434 break; 1435 /* fallthrough, tiled memory */ 1436 case TTM_PL_VRAM: 1437 reg->bus.offset = reg->start << PAGE_SHIFT; 1438 reg->bus.base = device->func->resource_addr(device, 1); 1439 reg->bus.is_iomem = true; 1440 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1441 union { 1442 struct nv50_mem_map_v0 nv50; 1443 struct gf100_mem_map_v0 gf100; 1444 } args; 1445 u64 handle, length; 1446 u32 argc = 0; 1447 int ret; 1448 1449 switch (mem->mem.object.oclass) { 1450 case NVIF_CLASS_MEM_NV50: 1451 args.nv50.version = 0; 1452 args.nv50.ro = 0; 1453 args.nv50.kind = mem->kind; 1454 args.nv50.comp = mem->comp; 1455 argc = sizeof(args.nv50); 1456 break; 1457 case NVIF_CLASS_MEM_GF100: 1458 args.gf100.version = 0; 1459 args.gf100.ro = 0; 1460 args.gf100.kind = mem->kind; 1461 argc = sizeof(args.gf100); 1462 break; 1463 default: 1464 WARN_ON(1); 1465 break; 1466 } 1467 1468 ret = nvif_object_map_handle(&mem->mem.object, 1469 &args, argc, 1470 &handle, &length); 1471 if (ret != 1) 1472 return ret ? ret : -EINVAL; 1473 1474 reg->bus.base = 0; 1475 reg->bus.offset = handle; 1476 } 1477 break; 1478 default: 1479 return -EINVAL; 1480 } 1481 return 0; 1482 } 1483 1484 static void 1485 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1486 { 1487 struct nouveau_drm *drm = nouveau_bdev(bdev); 1488 struct nouveau_mem *mem = nouveau_mem(reg); 1489 1490 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1491 switch (reg->mem_type) { 1492 case TTM_PL_TT: 1493 if (mem->kind) 1494 nvif_object_unmap_handle(&mem->mem.object); 1495 break; 1496 case TTM_PL_VRAM: 1497 nvif_object_unmap_handle(&mem->mem.object); 1498 break; 1499 default: 1500 break; 1501 } 1502 } 1503 } 1504 1505 static int 1506 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1507 { 1508 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1509 struct nouveau_bo *nvbo = nouveau_bo(bo); 1510 struct nvkm_device *device = nvxx_device(&drm->client.device); 1511 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1512 int i, ret; 1513 1514 /* as long as the bo isn't in vram, and isn't tiled, we've got 1515 * nothing to do here. 1516 */ 1517 if (bo->mem.mem_type != TTM_PL_VRAM) { 1518 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1519 !nvbo->kind) 1520 return 0; 1521 1522 if (bo->mem.mem_type == TTM_PL_SYSTEM) { 1523 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); 1524 1525 ret = nouveau_bo_validate(nvbo, false, false); 1526 if (ret) 1527 return ret; 1528 } 1529 return 0; 1530 } 1531 1532 /* make sure bo is in mappable vram */ 1533 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1534 bo->mem.start + bo->mem.num_pages < mappable) 1535 return 0; 1536 1537 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1538 nvbo->placements[i].fpfn = 0; 1539 nvbo->placements[i].lpfn = mappable; 1540 } 1541 1542 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1543 nvbo->busy_placements[i].fpfn = 0; 1544 nvbo->busy_placements[i].lpfn = mappable; 1545 } 1546 1547 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); 1548 return nouveau_bo_validate(nvbo, false, false); 1549 } 1550 1551 static int 1552 nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1553 { 1554 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1555 struct nouveau_drm *drm; 1556 struct device *dev; 1557 unsigned i; 1558 int r; 1559 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1560 1561 if (ttm->state != tt_unpopulated) 1562 return 0; 1563 1564 if (slave && ttm->sg) { 1565 /* make userspace faulting work */ 1566 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1567 ttm_dma->dma_address, ttm->num_pages); 1568 ttm->state = tt_unbound; 1569 return 0; 1570 } 1571 1572 drm = nouveau_bdev(ttm->bdev); 1573 dev = drm->dev->dev; 1574 1575 #if IS_ENABLED(CONFIG_AGP) 1576 if (drm->agp.bridge) { 1577 return ttm_agp_tt_populate(ttm, ctx); 1578 } 1579 #endif 1580 1581 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1582 if (swiotlb_nr_tbl()) { 1583 return ttm_dma_populate((void *)ttm, dev, ctx); 1584 } 1585 #endif 1586 1587 r = ttm_pool_populate(ttm, ctx); 1588 if (r) { 1589 return r; 1590 } 1591 1592 for (i = 0; i < ttm->num_pages; i++) { 1593 dma_addr_t addr; 1594 1595 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE, 1596 DMA_BIDIRECTIONAL); 1597 1598 if (dma_mapping_error(dev, addr)) { 1599 while (i--) { 1600 dma_unmap_page(dev, ttm_dma->dma_address[i], 1601 PAGE_SIZE, DMA_BIDIRECTIONAL); 1602 ttm_dma->dma_address[i] = 0; 1603 } 1604 ttm_pool_unpopulate(ttm); 1605 return -EFAULT; 1606 } 1607 1608 ttm_dma->dma_address[i] = addr; 1609 } 1610 return 0; 1611 } 1612 1613 static void 1614 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) 1615 { 1616 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1617 struct nouveau_drm *drm; 1618 struct device *dev; 1619 unsigned i; 1620 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1621 1622 if (slave) 1623 return; 1624 1625 drm = nouveau_bdev(ttm->bdev); 1626 dev = drm->dev->dev; 1627 1628 #if IS_ENABLED(CONFIG_AGP) 1629 if (drm->agp.bridge) { 1630 ttm_agp_tt_unpopulate(ttm); 1631 return; 1632 } 1633 #endif 1634 1635 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1636 if (swiotlb_nr_tbl()) { 1637 ttm_dma_unpopulate((void *)ttm, dev); 1638 return; 1639 } 1640 #endif 1641 1642 for (i = 0; i < ttm->num_pages; i++) { 1643 if (ttm_dma->dma_address[i]) { 1644 dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE, 1645 DMA_BIDIRECTIONAL); 1646 } 1647 } 1648 1649 ttm_pool_unpopulate(ttm); 1650 } 1651 1652 void 1653 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1654 { 1655 struct reservation_object *resv = nvbo->bo.resv; 1656 1657 if (exclusive) 1658 reservation_object_add_excl_fence(resv, &fence->base); 1659 else if (fence) 1660 reservation_object_add_shared_fence(resv, &fence->base); 1661 } 1662 1663 struct ttm_bo_driver nouveau_bo_driver = { 1664 .ttm_tt_create = &nouveau_ttm_tt_create, 1665 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1666 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1667 .invalidate_caches = nouveau_bo_invalidate_caches, 1668 .init_mem_type = nouveau_bo_init_mem_type, 1669 .eviction_valuable = ttm_bo_eviction_valuable, 1670 .evict_flags = nouveau_bo_evict_flags, 1671 .move_notify = nouveau_bo_move_ntfy, 1672 .move = nouveau_bo_move, 1673 .verify_access = nouveau_bo_verify_access, 1674 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, 1675 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1676 .io_mem_free = &nouveau_ttm_io_mem_free, 1677 }; 1678