1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 #include <linux/swiotlb.h> 32 33 #include "nouveau_drv.h" 34 #include "nouveau_dma.h" 35 #include "nouveau_fence.h" 36 37 #include "nouveau_bo.h" 38 #include "nouveau_ttm.h" 39 #include "nouveau_gem.h" 40 #include "nouveau_mem.h" 41 #include "nouveau_vmm.h" 42 43 #include <nvif/class.h> 44 #include <nvif/if500b.h> 45 #include <nvif/if900b.h> 46 47 /* 48 * NV10-NV40 tiling helpers 49 */ 50 51 static void 52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 53 u32 addr, u32 size, u32 pitch, u32 flags) 54 { 55 struct nouveau_drm *drm = nouveau_drm(dev); 56 int i = reg - drm->tile.reg; 57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 58 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 59 60 nouveau_fence_unref(®->fence); 61 62 if (tile->pitch) 63 nvkm_fb_tile_fini(fb, i, tile); 64 65 if (pitch) 66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 67 68 nvkm_fb_tile_prog(fb, i, tile); 69 } 70 71 static struct nouveau_drm_tile * 72 nv10_bo_get_tile_region(struct drm_device *dev, int i) 73 { 74 struct nouveau_drm *drm = nouveau_drm(dev); 75 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 76 77 spin_lock(&drm->tile.lock); 78 79 if (!tile->used && 80 (!tile->fence || nouveau_fence_done(tile->fence))) 81 tile->used = true; 82 else 83 tile = NULL; 84 85 spin_unlock(&drm->tile.lock); 86 return tile; 87 } 88 89 static void 90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 91 struct dma_fence *fence) 92 { 93 struct nouveau_drm *drm = nouveau_drm(dev); 94 95 if (tile) { 96 spin_lock(&drm->tile.lock); 97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 98 tile->used = false; 99 spin_unlock(&drm->tile.lock); 100 } 101 } 102 103 static struct nouveau_drm_tile * 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 105 u32 size, u32 pitch, u32 zeta) 106 { 107 struct nouveau_drm *drm = nouveau_drm(dev); 108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 109 struct nouveau_drm_tile *tile, *found = NULL; 110 int i; 111 112 for (i = 0; i < fb->tile.regions; i++) { 113 tile = nv10_bo_get_tile_region(dev, i); 114 115 if (pitch && !found) { 116 found = tile; 117 continue; 118 119 } else if (tile && fb->tile.region[i].pitch) { 120 /* Kill an unused tile region. */ 121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 122 } 123 124 nv10_bo_put_tile_region(dev, tile, NULL); 125 } 126 127 if (found) 128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 129 return found; 130 } 131 132 static void 133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 134 { 135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 136 struct drm_device *dev = drm->dev; 137 struct nouveau_bo *nvbo = nouveau_bo(bo); 138 139 if (unlikely(nvbo->bo.base.filp)) 140 DRM_ERROR("bo %p still attached to GEM object\n", bo); 141 WARN_ON(nvbo->pin_refcnt > 0); 142 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 143 kfree(nvbo); 144 } 145 146 static inline u64 147 roundup_64(u64 x, u32 y) 148 { 149 x += y - 1; 150 do_div(x, y); 151 return x * y; 152 } 153 154 static void 155 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, 156 int *align, u64 *size) 157 { 158 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 159 struct nvif_device *device = &drm->client.device; 160 161 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 162 if (nvbo->mode) { 163 if (device->info.chipset >= 0x40) { 164 *align = 65536; 165 *size = roundup_64(*size, 64 * nvbo->mode); 166 167 } else if (device->info.chipset >= 0x30) { 168 *align = 32768; 169 *size = roundup_64(*size, 64 * nvbo->mode); 170 171 } else if (device->info.chipset >= 0x20) { 172 *align = 16384; 173 *size = roundup_64(*size, 64 * nvbo->mode); 174 175 } else if (device->info.chipset >= 0x10) { 176 *align = 16384; 177 *size = roundup_64(*size, 32 * nvbo->mode); 178 } 179 } 180 } else { 181 *size = roundup_64(*size, (1 << nvbo->page)); 182 *align = max((1 << nvbo->page), *align); 183 } 184 185 *size = roundup_64(*size, PAGE_SIZE); 186 } 187 188 struct nouveau_bo * 189 nouveau_bo_alloc(struct nouveau_cli *cli, u64 size, u32 flags, u32 tile_mode, 190 u32 tile_flags) 191 { 192 struct nouveau_drm *drm = cli->drm; 193 struct nouveau_bo *nvbo; 194 struct nvif_mmu *mmu = &cli->mmu; 195 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm; 196 int i, pi = -1; 197 198 if (!size) { 199 NV_WARN(drm, "skipped size %016llx\n", size); 200 return ERR_PTR(-EINVAL); 201 } 202 203 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 204 if (!nvbo) 205 return ERR_PTR(-ENOMEM); 206 INIT_LIST_HEAD(&nvbo->head); 207 INIT_LIST_HEAD(&nvbo->entry); 208 INIT_LIST_HEAD(&nvbo->vma_list); 209 nvbo->bo.bdev = &drm->ttm.bdev; 210 211 /* This is confusing, and doesn't actually mean we want an uncached 212 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 213 * into in nouveau_gem_new(). 214 */ 215 if (flags & TTM_PL_FLAG_UNCACHED) { 216 /* Determine if we can get a cache-coherent map, forcing 217 * uncached mapping if we can't. 218 */ 219 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 220 nvbo->force_coherent = true; 221 } 222 223 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 224 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 225 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 226 kfree(nvbo); 227 return ERR_PTR(-EINVAL); 228 } 229 230 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 231 } else 232 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 233 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 234 nvbo->comp = (tile_flags & 0x00030000) >> 16; 235 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 236 kfree(nvbo); 237 return ERR_PTR(-EINVAL); 238 } 239 } else { 240 nvbo->zeta = (tile_flags & 0x00000007); 241 } 242 nvbo->mode = tile_mode; 243 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 244 245 /* Determine the desirable target GPU page size for the buffer. */ 246 for (i = 0; i < vmm->page_nr; i++) { 247 /* Because we cannot currently allow VMM maps to fail 248 * during buffer migration, we need to determine page 249 * size for the buffer up-front, and pre-allocate its 250 * page tables. 251 * 252 * Skip page sizes that can't support needed domains. 253 */ 254 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 255 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram) 256 continue; 257 if ((flags & TTM_PL_FLAG_TT) && 258 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 259 continue; 260 261 /* Select this page size if it's the first that supports 262 * the potential memory domains, or when it's compatible 263 * with the requested compression settings. 264 */ 265 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 266 pi = i; 267 268 /* Stop once the buffer is larger than the current page size. */ 269 if (size >= 1ULL << vmm->page[i].shift) 270 break; 271 } 272 273 if (WARN_ON(pi < 0)) 274 return ERR_PTR(-EINVAL); 275 276 /* Disable compression if suitable settings couldn't be found. */ 277 if (nvbo->comp && !vmm->page[pi].comp) { 278 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 279 nvbo->kind = mmu->kind[nvbo->kind]; 280 nvbo->comp = 0; 281 } 282 nvbo->page = vmm->page[pi].shift; 283 284 return nvbo; 285 } 286 287 int 288 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 flags, 289 struct sg_table *sg, struct dma_resv *robj) 290 { 291 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device; 292 size_t acc_size; 293 int ret; 294 295 acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo)); 296 297 nouveau_bo_fixup_align(nvbo, flags, &align, &size); 298 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; 299 nouveau_bo_placement_set(nvbo, flags, 0); 300 301 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type, 302 &nvbo->placement, align >> PAGE_SHIFT, false, 303 acc_size, sg, robj, nouveau_bo_del_ttm); 304 if (ret) { 305 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 306 return ret; 307 } 308 309 return 0; 310 } 311 312 int 313 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 314 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, 315 struct sg_table *sg, struct dma_resv *robj, 316 struct nouveau_bo **pnvbo) 317 { 318 struct nouveau_bo *nvbo; 319 int ret; 320 321 nvbo = nouveau_bo_alloc(cli, size, flags, tile_mode, tile_flags); 322 if (IS_ERR(nvbo)) 323 return PTR_ERR(nvbo); 324 325 ret = nouveau_bo_init(nvbo, size, align, flags, sg, robj); 326 if (ret) 327 return ret; 328 329 *pnvbo = nvbo; 330 return 0; 331 } 332 333 static void 334 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) 335 { 336 *n = 0; 337 338 if (type & TTM_PL_FLAG_VRAM) 339 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; 340 if (type & TTM_PL_FLAG_TT) 341 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; 342 if (type & TTM_PL_FLAG_SYSTEM) 343 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; 344 } 345 346 static void 347 set_placement_range(struct nouveau_bo *nvbo, uint32_t type) 348 { 349 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 350 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; 351 unsigned i, fpfn, lpfn; 352 353 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 354 nvbo->mode && (type & TTM_PL_FLAG_VRAM) && 355 nvbo->bo.mem.num_pages < vram_pages / 4) { 356 /* 357 * Make sure that the color and depth buffers are handled 358 * by independent memory controller units. Up to a 9x 359 * speed up when alpha-blending and depth-test are enabled 360 * at the same time. 361 */ 362 if (nvbo->zeta) { 363 fpfn = vram_pages / 2; 364 lpfn = ~0; 365 } else { 366 fpfn = 0; 367 lpfn = vram_pages / 2; 368 } 369 for (i = 0; i < nvbo->placement.num_placement; ++i) { 370 nvbo->placements[i].fpfn = fpfn; 371 nvbo->placements[i].lpfn = lpfn; 372 } 373 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 374 nvbo->busy_placements[i].fpfn = fpfn; 375 nvbo->busy_placements[i].lpfn = lpfn; 376 } 377 } 378 } 379 380 void 381 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) 382 { 383 struct ttm_placement *pl = &nvbo->placement; 384 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : 385 TTM_PL_MASK_CACHING) | 386 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); 387 388 pl->placement = nvbo->placements; 389 set_placement_list(nvbo->placements, &pl->num_placement, 390 type, flags); 391 392 pl->busy_placement = nvbo->busy_placements; 393 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 394 type | busy, flags); 395 396 set_placement_range(nvbo, type); 397 } 398 399 int 400 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) 401 { 402 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 403 struct ttm_buffer_object *bo = &nvbo->bo; 404 bool force = false, evict = false; 405 int ret; 406 407 ret = ttm_bo_reserve(bo, false, false, NULL); 408 if (ret) 409 return ret; 410 411 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 412 memtype == TTM_PL_FLAG_VRAM && contig) { 413 if (!nvbo->contig) { 414 nvbo->contig = true; 415 force = true; 416 evict = true; 417 } 418 } 419 420 if (nvbo->pin_refcnt) { 421 if (!(memtype & (1 << bo->mem.mem_type)) || evict) { 422 NV_ERROR(drm, "bo %p pinned elsewhere: " 423 "0x%08x vs 0x%08x\n", bo, 424 1 << bo->mem.mem_type, memtype); 425 ret = -EBUSY; 426 } 427 nvbo->pin_refcnt++; 428 goto out; 429 } 430 431 if (evict) { 432 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); 433 ret = nouveau_bo_validate(nvbo, false, false); 434 if (ret) 435 goto out; 436 } 437 438 nvbo->pin_refcnt++; 439 nouveau_bo_placement_set(nvbo, memtype, 0); 440 441 /* drop pin_refcnt temporarily, so we don't trip the assertion 442 * in nouveau_bo_move() that makes sure we're not trying to 443 * move a pinned buffer 444 */ 445 nvbo->pin_refcnt--; 446 ret = nouveau_bo_validate(nvbo, false, false); 447 if (ret) 448 goto out; 449 nvbo->pin_refcnt++; 450 451 switch (bo->mem.mem_type) { 452 case TTM_PL_VRAM: 453 drm->gem.vram_available -= bo->mem.size; 454 break; 455 case TTM_PL_TT: 456 drm->gem.gart_available -= bo->mem.size; 457 break; 458 default: 459 break; 460 } 461 462 out: 463 if (force && ret) 464 nvbo->contig = false; 465 ttm_bo_unreserve(bo); 466 return ret; 467 } 468 469 int 470 nouveau_bo_unpin(struct nouveau_bo *nvbo) 471 { 472 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 473 struct ttm_buffer_object *bo = &nvbo->bo; 474 int ret, ref; 475 476 ret = ttm_bo_reserve(bo, false, false, NULL); 477 if (ret) 478 return ret; 479 480 ref = --nvbo->pin_refcnt; 481 WARN_ON_ONCE(ref < 0); 482 if (ref) 483 goto out; 484 485 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); 486 487 ret = nouveau_bo_validate(nvbo, false, false); 488 if (ret == 0) { 489 switch (bo->mem.mem_type) { 490 case TTM_PL_VRAM: 491 drm->gem.vram_available += bo->mem.size; 492 break; 493 case TTM_PL_TT: 494 drm->gem.gart_available += bo->mem.size; 495 break; 496 default: 497 break; 498 } 499 } 500 501 out: 502 ttm_bo_unreserve(bo); 503 return ret; 504 } 505 506 int 507 nouveau_bo_map(struct nouveau_bo *nvbo) 508 { 509 int ret; 510 511 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 512 if (ret) 513 return ret; 514 515 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 516 517 ttm_bo_unreserve(&nvbo->bo); 518 return ret; 519 } 520 521 void 522 nouveau_bo_unmap(struct nouveau_bo *nvbo) 523 { 524 if (!nvbo) 525 return; 526 527 ttm_bo_kunmap(&nvbo->kmap); 528 } 529 530 void 531 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 532 { 533 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 534 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 535 int i; 536 537 if (!ttm_dma) 538 return; 539 540 /* Don't waste time looping if the object is coherent */ 541 if (nvbo->force_coherent) 542 return; 543 544 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 545 dma_sync_single_for_device(drm->dev->dev, 546 ttm_dma->dma_address[i], 547 PAGE_SIZE, DMA_TO_DEVICE); 548 } 549 550 void 551 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 552 { 553 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 554 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 555 int i; 556 557 if (!ttm_dma) 558 return; 559 560 /* Don't waste time looping if the object is coherent */ 561 if (nvbo->force_coherent) 562 return; 563 564 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 565 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 566 PAGE_SIZE, DMA_FROM_DEVICE); 567 } 568 569 int 570 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 571 bool no_wait_gpu) 572 { 573 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 574 int ret; 575 576 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 577 if (ret) 578 return ret; 579 580 nouveau_bo_sync_for_device(nvbo); 581 582 return 0; 583 } 584 585 void 586 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 587 { 588 bool is_iomem; 589 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 590 591 mem += index; 592 593 if (is_iomem) 594 iowrite16_native(val, (void __force __iomem *)mem); 595 else 596 *mem = val; 597 } 598 599 u32 600 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 601 { 602 bool is_iomem; 603 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 604 605 mem += index; 606 607 if (is_iomem) 608 return ioread32_native((void __force __iomem *)mem); 609 else 610 return *mem; 611 } 612 613 void 614 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 615 { 616 bool is_iomem; 617 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 618 619 mem += index; 620 621 if (is_iomem) 622 iowrite32_native(val, (void __force __iomem *)mem); 623 else 624 *mem = val; 625 } 626 627 static struct ttm_tt * 628 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 629 { 630 #if IS_ENABLED(CONFIG_AGP) 631 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 632 633 if (drm->agp.bridge) { 634 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 635 } 636 #endif 637 638 return nouveau_sgdma_create_ttm(bo, page_flags); 639 } 640 641 static int 642 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 643 { 644 /* We'll do this from user space. */ 645 return 0; 646 } 647 648 static int 649 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 650 struct ttm_mem_type_manager *man) 651 { 652 struct nouveau_drm *drm = nouveau_bdev(bdev); 653 struct nvif_mmu *mmu = &drm->client.mmu; 654 655 switch (type) { 656 case TTM_PL_SYSTEM: 657 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 658 man->available_caching = TTM_PL_MASK_CACHING; 659 man->default_caching = TTM_PL_FLAG_CACHED; 660 break; 661 case TTM_PL_VRAM: 662 man->flags = TTM_MEMTYPE_FLAG_FIXED | 663 TTM_MEMTYPE_FLAG_MAPPABLE; 664 man->available_caching = TTM_PL_FLAG_UNCACHED | 665 TTM_PL_FLAG_WC; 666 man->default_caching = TTM_PL_FLAG_WC; 667 668 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 669 /* Some BARs do not support being ioremapped WC */ 670 const u8 type = mmu->type[drm->ttm.type_vram].type; 671 if (type & NVIF_MEM_UNCACHED) { 672 man->available_caching = TTM_PL_FLAG_UNCACHED; 673 man->default_caching = TTM_PL_FLAG_UNCACHED; 674 } 675 676 man->func = &nouveau_vram_manager; 677 man->io_reserve_fastpath = false; 678 man->use_io_reserve_lru = true; 679 } else { 680 man->func = &ttm_bo_manager_func; 681 } 682 break; 683 case TTM_PL_TT: 684 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) 685 man->func = &nouveau_gart_manager; 686 else 687 if (!drm->agp.bridge) 688 man->func = &nv04_gart_manager; 689 else 690 man->func = &ttm_bo_manager_func; 691 692 if (drm->agp.bridge) { 693 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 694 man->available_caching = TTM_PL_FLAG_UNCACHED | 695 TTM_PL_FLAG_WC; 696 man->default_caching = TTM_PL_FLAG_WC; 697 } else { 698 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | 699 TTM_MEMTYPE_FLAG_CMA; 700 man->available_caching = TTM_PL_MASK_CACHING; 701 man->default_caching = TTM_PL_FLAG_CACHED; 702 } 703 704 break; 705 default: 706 return -EINVAL; 707 } 708 return 0; 709 } 710 711 static void 712 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 713 { 714 struct nouveau_bo *nvbo = nouveau_bo(bo); 715 716 switch (bo->mem.mem_type) { 717 case TTM_PL_VRAM: 718 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 719 TTM_PL_FLAG_SYSTEM); 720 break; 721 default: 722 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); 723 break; 724 } 725 726 *pl = nvbo->placement; 727 } 728 729 730 static int 731 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) 732 { 733 int ret = RING_SPACE(chan, 2); 734 if (ret == 0) { 735 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 736 OUT_RING (chan, handle & 0x0000ffff); 737 FIRE_RING (chan); 738 } 739 return ret; 740 } 741 742 static int 743 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 744 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 745 { 746 struct nouveau_mem *mem = nouveau_mem(old_reg); 747 int ret = RING_SPACE(chan, 10); 748 if (ret == 0) { 749 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); 750 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 751 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 752 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 753 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 754 OUT_RING (chan, PAGE_SIZE); 755 OUT_RING (chan, PAGE_SIZE); 756 OUT_RING (chan, PAGE_SIZE); 757 OUT_RING (chan, new_reg->num_pages); 758 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); 759 } 760 return ret; 761 } 762 763 static int 764 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) 765 { 766 int ret = RING_SPACE(chan, 2); 767 if (ret == 0) { 768 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 769 OUT_RING (chan, handle); 770 } 771 return ret; 772 } 773 774 static int 775 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 776 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 777 { 778 struct nouveau_mem *mem = nouveau_mem(old_reg); 779 u64 src_offset = mem->vma[0].addr; 780 u64 dst_offset = mem->vma[1].addr; 781 u32 page_count = new_reg->num_pages; 782 int ret; 783 784 page_count = new_reg->num_pages; 785 while (page_count) { 786 int line_count = (page_count > 8191) ? 8191 : page_count; 787 788 ret = RING_SPACE(chan, 11); 789 if (ret) 790 return ret; 791 792 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); 793 OUT_RING (chan, upper_32_bits(src_offset)); 794 OUT_RING (chan, lower_32_bits(src_offset)); 795 OUT_RING (chan, upper_32_bits(dst_offset)); 796 OUT_RING (chan, lower_32_bits(dst_offset)); 797 OUT_RING (chan, PAGE_SIZE); 798 OUT_RING (chan, PAGE_SIZE); 799 OUT_RING (chan, PAGE_SIZE); 800 OUT_RING (chan, line_count); 801 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 802 OUT_RING (chan, 0x00000110); 803 804 page_count -= line_count; 805 src_offset += (PAGE_SIZE * line_count); 806 dst_offset += (PAGE_SIZE * line_count); 807 } 808 809 return 0; 810 } 811 812 static int 813 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 814 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 815 { 816 struct nouveau_mem *mem = nouveau_mem(old_reg); 817 u64 src_offset = mem->vma[0].addr; 818 u64 dst_offset = mem->vma[1].addr; 819 u32 page_count = new_reg->num_pages; 820 int ret; 821 822 page_count = new_reg->num_pages; 823 while (page_count) { 824 int line_count = (page_count > 2047) ? 2047 : page_count; 825 826 ret = RING_SPACE(chan, 12); 827 if (ret) 828 return ret; 829 830 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); 831 OUT_RING (chan, upper_32_bits(dst_offset)); 832 OUT_RING (chan, lower_32_bits(dst_offset)); 833 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); 834 OUT_RING (chan, upper_32_bits(src_offset)); 835 OUT_RING (chan, lower_32_bits(src_offset)); 836 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 837 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 838 OUT_RING (chan, PAGE_SIZE); /* line_length */ 839 OUT_RING (chan, line_count); 840 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 841 OUT_RING (chan, 0x00100110); 842 843 page_count -= line_count; 844 src_offset += (PAGE_SIZE * line_count); 845 dst_offset += (PAGE_SIZE * line_count); 846 } 847 848 return 0; 849 } 850 851 static int 852 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 853 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 854 { 855 struct nouveau_mem *mem = nouveau_mem(old_reg); 856 u64 src_offset = mem->vma[0].addr; 857 u64 dst_offset = mem->vma[1].addr; 858 u32 page_count = new_reg->num_pages; 859 int ret; 860 861 page_count = new_reg->num_pages; 862 while (page_count) { 863 int line_count = (page_count > 8191) ? 8191 : page_count; 864 865 ret = RING_SPACE(chan, 11); 866 if (ret) 867 return ret; 868 869 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 870 OUT_RING (chan, upper_32_bits(src_offset)); 871 OUT_RING (chan, lower_32_bits(src_offset)); 872 OUT_RING (chan, upper_32_bits(dst_offset)); 873 OUT_RING (chan, lower_32_bits(dst_offset)); 874 OUT_RING (chan, PAGE_SIZE); 875 OUT_RING (chan, PAGE_SIZE); 876 OUT_RING (chan, PAGE_SIZE); 877 OUT_RING (chan, line_count); 878 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); 879 OUT_RING (chan, 0x00000110); 880 881 page_count -= line_count; 882 src_offset += (PAGE_SIZE * line_count); 883 dst_offset += (PAGE_SIZE * line_count); 884 } 885 886 return 0; 887 } 888 889 static int 890 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 891 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 892 { 893 struct nouveau_mem *mem = nouveau_mem(old_reg); 894 int ret = RING_SPACE(chan, 7); 895 if (ret == 0) { 896 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); 897 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 898 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 899 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 900 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 901 OUT_RING (chan, 0x00000000 /* COPY */); 902 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 903 } 904 return ret; 905 } 906 907 static int 908 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 909 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 910 { 911 struct nouveau_mem *mem = nouveau_mem(old_reg); 912 int ret = RING_SPACE(chan, 7); 913 if (ret == 0) { 914 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); 915 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 916 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 917 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 918 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 919 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 920 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); 921 } 922 return ret; 923 } 924 925 static int 926 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) 927 { 928 int ret = RING_SPACE(chan, 6); 929 if (ret == 0) { 930 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 931 OUT_RING (chan, handle); 932 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); 933 OUT_RING (chan, chan->drm->ntfy.handle); 934 OUT_RING (chan, chan->vram.handle); 935 OUT_RING (chan, chan->vram.handle); 936 } 937 938 return ret; 939 } 940 941 static int 942 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 943 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 944 { 945 struct nouveau_mem *mem = nouveau_mem(old_reg); 946 u64 length = (new_reg->num_pages << PAGE_SHIFT); 947 u64 src_offset = mem->vma[0].addr; 948 u64 dst_offset = mem->vma[1].addr; 949 int src_tiled = !!mem->kind; 950 int dst_tiled = !!nouveau_mem(new_reg)->kind; 951 int ret; 952 953 while (length) { 954 u32 amount, stride, height; 955 956 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); 957 if (ret) 958 return ret; 959 960 amount = min(length, (u64)(4 * 1024 * 1024)); 961 stride = 16 * 4; 962 height = amount / stride; 963 964 if (src_tiled) { 965 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); 966 OUT_RING (chan, 0); 967 OUT_RING (chan, 0); 968 OUT_RING (chan, stride); 969 OUT_RING (chan, height); 970 OUT_RING (chan, 1); 971 OUT_RING (chan, 0); 972 OUT_RING (chan, 0); 973 } else { 974 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); 975 OUT_RING (chan, 1); 976 } 977 if (dst_tiled) { 978 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); 979 OUT_RING (chan, 0); 980 OUT_RING (chan, 0); 981 OUT_RING (chan, stride); 982 OUT_RING (chan, height); 983 OUT_RING (chan, 1); 984 OUT_RING (chan, 0); 985 OUT_RING (chan, 0); 986 } else { 987 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); 988 OUT_RING (chan, 1); 989 } 990 991 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); 992 OUT_RING (chan, upper_32_bits(src_offset)); 993 OUT_RING (chan, upper_32_bits(dst_offset)); 994 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 995 OUT_RING (chan, lower_32_bits(src_offset)); 996 OUT_RING (chan, lower_32_bits(dst_offset)); 997 OUT_RING (chan, stride); 998 OUT_RING (chan, stride); 999 OUT_RING (chan, stride); 1000 OUT_RING (chan, height); 1001 OUT_RING (chan, 0x00000101); 1002 OUT_RING (chan, 0x00000000); 1003 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 1004 OUT_RING (chan, 0); 1005 1006 length -= amount; 1007 src_offset += amount; 1008 dst_offset += amount; 1009 } 1010 1011 return 0; 1012 } 1013 1014 static int 1015 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) 1016 { 1017 int ret = RING_SPACE(chan, 4); 1018 if (ret == 0) { 1019 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 1020 OUT_RING (chan, handle); 1021 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); 1022 OUT_RING (chan, chan->drm->ntfy.handle); 1023 } 1024 1025 return ret; 1026 } 1027 1028 static inline uint32_t 1029 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, 1030 struct nouveau_channel *chan, struct ttm_mem_reg *reg) 1031 { 1032 if (reg->mem_type == TTM_PL_TT) 1033 return NvDmaTT; 1034 return chan->vram.handle; 1035 } 1036 1037 static int 1038 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 1039 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 1040 { 1041 u32 src_offset = old_reg->start << PAGE_SHIFT; 1042 u32 dst_offset = new_reg->start << PAGE_SHIFT; 1043 u32 page_count = new_reg->num_pages; 1044 int ret; 1045 1046 ret = RING_SPACE(chan, 3); 1047 if (ret) 1048 return ret; 1049 1050 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); 1051 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); 1052 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); 1053 1054 page_count = new_reg->num_pages; 1055 while (page_count) { 1056 int line_count = (page_count > 2047) ? 2047 : page_count; 1057 1058 ret = RING_SPACE(chan, 11); 1059 if (ret) 1060 return ret; 1061 1062 BEGIN_NV04(chan, NvSubCopy, 1063 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 1064 OUT_RING (chan, src_offset); 1065 OUT_RING (chan, dst_offset); 1066 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 1067 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 1068 OUT_RING (chan, PAGE_SIZE); /* line_length */ 1069 OUT_RING (chan, line_count); 1070 OUT_RING (chan, 0x00000101); 1071 OUT_RING (chan, 0x00000000); 1072 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 1073 OUT_RING (chan, 0); 1074 1075 page_count -= line_count; 1076 src_offset += (PAGE_SIZE * line_count); 1077 dst_offset += (PAGE_SIZE * line_count); 1078 } 1079 1080 return 0; 1081 } 1082 1083 static int 1084 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 1085 struct ttm_mem_reg *reg) 1086 { 1087 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 1088 struct nouveau_mem *new_mem = nouveau_mem(reg); 1089 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 1090 int ret; 1091 1092 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 1093 old_mem->mem.size, &old_mem->vma[0]); 1094 if (ret) 1095 return ret; 1096 1097 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 1098 new_mem->mem.size, &old_mem->vma[1]); 1099 if (ret) 1100 goto done; 1101 1102 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 1103 if (ret) 1104 goto done; 1105 1106 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 1107 done: 1108 if (ret) { 1109 nvif_vmm_put(vmm, &old_mem->vma[1]); 1110 nvif_vmm_put(vmm, &old_mem->vma[0]); 1111 } 1112 return 0; 1113 } 1114 1115 static int 1116 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, 1117 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1118 { 1119 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1120 struct nouveau_channel *chan = drm->ttm.chan; 1121 struct nouveau_cli *cli = (void *)chan->user.client; 1122 struct nouveau_fence *fence; 1123 int ret; 1124 1125 /* create temporary vmas for the transfer and attach them to the 1126 * old nvkm_mem node, these will get cleaned up after ttm has 1127 * destroyed the ttm_mem_reg 1128 */ 1129 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 1130 ret = nouveau_bo_move_prep(drm, bo, new_reg); 1131 if (ret) 1132 return ret; 1133 } 1134 1135 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 1136 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); 1137 if (ret == 0) { 1138 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 1139 if (ret == 0) { 1140 ret = nouveau_fence_new(chan, false, &fence); 1141 if (ret == 0) { 1142 ret = ttm_bo_move_accel_cleanup(bo, 1143 &fence->base, 1144 evict, 1145 new_reg); 1146 nouveau_fence_unref(&fence); 1147 } 1148 } 1149 } 1150 mutex_unlock(&cli->mutex); 1151 return ret; 1152 } 1153 1154 void 1155 nouveau_bo_move_init(struct nouveau_drm *drm) 1156 { 1157 static const struct { 1158 const char *name; 1159 int engine; 1160 s32 oclass; 1161 int (*exec)(struct nouveau_channel *, 1162 struct ttm_buffer_object *, 1163 struct ttm_mem_reg *, struct ttm_mem_reg *); 1164 int (*init)(struct nouveau_channel *, u32 handle); 1165 } _methods[] = { 1166 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, 1167 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1168 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 1169 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1170 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 1171 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1172 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1173 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1174 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1175 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1176 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1177 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1178 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 1179 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 1180 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 1181 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 1182 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 1183 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 1184 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 1185 {}, 1186 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, 1187 }, *mthd = _methods; 1188 const char *name = "CPU"; 1189 int ret; 1190 1191 do { 1192 struct nouveau_channel *chan; 1193 1194 if (mthd->engine) 1195 chan = drm->cechan; 1196 else 1197 chan = drm->channel; 1198 if (chan == NULL) 1199 continue; 1200 1201 ret = nvif_object_init(&chan->user, 1202 mthd->oclass | (mthd->engine << 16), 1203 mthd->oclass, NULL, 0, 1204 &drm->ttm.copy); 1205 if (ret == 0) { 1206 ret = mthd->init(chan, drm->ttm.copy.handle); 1207 if (ret) { 1208 nvif_object_fini(&drm->ttm.copy); 1209 continue; 1210 } 1211 1212 drm->ttm.move = mthd->exec; 1213 drm->ttm.chan = chan; 1214 name = mthd->name; 1215 break; 1216 } 1217 } while ((++mthd)->exec); 1218 1219 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 1220 } 1221 1222 static int 1223 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 1224 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1225 { 1226 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1227 struct ttm_place placement_memtype = { 1228 .fpfn = 0, 1229 .lpfn = 0, 1230 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1231 }; 1232 struct ttm_placement placement; 1233 struct ttm_mem_reg tmp_reg; 1234 int ret; 1235 1236 placement.num_placement = placement.num_busy_placement = 1; 1237 placement.placement = placement.busy_placement = &placement_memtype; 1238 1239 tmp_reg = *new_reg; 1240 tmp_reg.mm_node = NULL; 1241 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1242 if (ret) 1243 return ret; 1244 1245 ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx); 1246 if (ret) 1247 goto out; 1248 1249 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); 1250 if (ret) 1251 goto out; 1252 1253 ret = ttm_bo_move_ttm(bo, &ctx, new_reg); 1254 out: 1255 ttm_bo_mem_put(bo, &tmp_reg); 1256 return ret; 1257 } 1258 1259 static int 1260 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 1261 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1262 { 1263 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1264 struct ttm_place placement_memtype = { 1265 .fpfn = 0, 1266 .lpfn = 0, 1267 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1268 }; 1269 struct ttm_placement placement; 1270 struct ttm_mem_reg tmp_reg; 1271 int ret; 1272 1273 placement.num_placement = placement.num_busy_placement = 1; 1274 placement.placement = placement.busy_placement = &placement_memtype; 1275 1276 tmp_reg = *new_reg; 1277 tmp_reg.mm_node = NULL; 1278 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1279 if (ret) 1280 return ret; 1281 1282 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg); 1283 if (ret) 1284 goto out; 1285 1286 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); 1287 if (ret) 1288 goto out; 1289 1290 out: 1291 ttm_bo_mem_put(bo, &tmp_reg); 1292 return ret; 1293 } 1294 1295 static void 1296 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, 1297 struct ttm_mem_reg *new_reg) 1298 { 1299 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 1300 struct nouveau_bo *nvbo = nouveau_bo(bo); 1301 struct nouveau_vma *vma; 1302 1303 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 1304 if (bo->destroy != nouveau_bo_del_ttm) 1305 return; 1306 1307 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 1308 mem->mem.page == nvbo->page) { 1309 list_for_each_entry(vma, &nvbo->vma_list, head) { 1310 nouveau_vma_map(vma, mem); 1311 } 1312 } else { 1313 list_for_each_entry(vma, &nvbo->vma_list, head) { 1314 WARN_ON(ttm_bo_wait(bo, false, false)); 1315 nouveau_vma_unmap(vma); 1316 } 1317 } 1318 } 1319 1320 static int 1321 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg, 1322 struct nouveau_drm_tile **new_tile) 1323 { 1324 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1325 struct drm_device *dev = drm->dev; 1326 struct nouveau_bo *nvbo = nouveau_bo(bo); 1327 u64 offset = new_reg->start << PAGE_SHIFT; 1328 1329 *new_tile = NULL; 1330 if (new_reg->mem_type != TTM_PL_VRAM) 1331 return 0; 1332 1333 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 1334 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, 1335 nvbo->mode, nvbo->zeta); 1336 } 1337 1338 return 0; 1339 } 1340 1341 static void 1342 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 1343 struct nouveau_drm_tile *new_tile, 1344 struct nouveau_drm_tile **old_tile) 1345 { 1346 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1347 struct drm_device *dev = drm->dev; 1348 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv); 1349 1350 nv10_bo_put_tile_region(dev, *old_tile, fence); 1351 *old_tile = new_tile; 1352 } 1353 1354 static int 1355 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 1356 struct ttm_operation_ctx *ctx, 1357 struct ttm_mem_reg *new_reg) 1358 { 1359 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1360 struct nouveau_bo *nvbo = nouveau_bo(bo); 1361 struct ttm_mem_reg *old_reg = &bo->mem; 1362 struct nouveau_drm_tile *new_tile = NULL; 1363 int ret = 0; 1364 1365 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1366 if (ret) 1367 return ret; 1368 1369 if (nvbo->pin_refcnt) 1370 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 1371 1372 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1373 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 1374 if (ret) 1375 return ret; 1376 } 1377 1378 /* Fake bo copy. */ 1379 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 1380 BUG_ON(bo->mem.mm_node != NULL); 1381 bo->mem = *new_reg; 1382 new_reg->mm_node = NULL; 1383 goto out; 1384 } 1385 1386 /* Hardware assisted copy. */ 1387 if (drm->ttm.move) { 1388 if (new_reg->mem_type == TTM_PL_SYSTEM) 1389 ret = nouveau_bo_move_flipd(bo, evict, 1390 ctx->interruptible, 1391 ctx->no_wait_gpu, new_reg); 1392 else if (old_reg->mem_type == TTM_PL_SYSTEM) 1393 ret = nouveau_bo_move_flips(bo, evict, 1394 ctx->interruptible, 1395 ctx->no_wait_gpu, new_reg); 1396 else 1397 ret = nouveau_bo_move_m2mf(bo, evict, 1398 ctx->interruptible, 1399 ctx->no_wait_gpu, new_reg); 1400 if (!ret) 1401 goto out; 1402 } 1403 1404 /* Fallback to software copy. */ 1405 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1406 if (ret == 0) 1407 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1408 1409 out: 1410 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1411 if (ret) 1412 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1413 else 1414 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1415 } 1416 1417 return ret; 1418 } 1419 1420 static int 1421 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 1422 { 1423 struct nouveau_bo *nvbo = nouveau_bo(bo); 1424 1425 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node, 1426 filp->private_data); 1427 } 1428 1429 static int 1430 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1431 { 1432 struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type]; 1433 struct nouveau_drm *drm = nouveau_bdev(bdev); 1434 struct nvkm_device *device = nvxx_device(&drm->client.device); 1435 struct nouveau_mem *mem = nouveau_mem(reg); 1436 1437 reg->bus.addr = NULL; 1438 reg->bus.offset = 0; 1439 reg->bus.size = reg->num_pages << PAGE_SHIFT; 1440 reg->bus.base = 0; 1441 reg->bus.is_iomem = false; 1442 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 1443 return -EINVAL; 1444 switch (reg->mem_type) { 1445 case TTM_PL_SYSTEM: 1446 /* System memory */ 1447 return 0; 1448 case TTM_PL_TT: 1449 #if IS_ENABLED(CONFIG_AGP) 1450 if (drm->agp.bridge) { 1451 reg->bus.offset = reg->start << PAGE_SHIFT; 1452 reg->bus.base = drm->agp.base; 1453 reg->bus.is_iomem = !drm->agp.cma; 1454 } 1455 #endif 1456 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) 1457 /* untiled */ 1458 break; 1459 /* fall through - tiled memory */ 1460 case TTM_PL_VRAM: 1461 reg->bus.offset = reg->start << PAGE_SHIFT; 1462 reg->bus.base = device->func->resource_addr(device, 1); 1463 reg->bus.is_iomem = true; 1464 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1465 union { 1466 struct nv50_mem_map_v0 nv50; 1467 struct gf100_mem_map_v0 gf100; 1468 } args; 1469 u64 handle, length; 1470 u32 argc = 0; 1471 int ret; 1472 1473 switch (mem->mem.object.oclass) { 1474 case NVIF_CLASS_MEM_NV50: 1475 args.nv50.version = 0; 1476 args.nv50.ro = 0; 1477 args.nv50.kind = mem->kind; 1478 args.nv50.comp = mem->comp; 1479 argc = sizeof(args.nv50); 1480 break; 1481 case NVIF_CLASS_MEM_GF100: 1482 args.gf100.version = 0; 1483 args.gf100.ro = 0; 1484 args.gf100.kind = mem->kind; 1485 argc = sizeof(args.gf100); 1486 break; 1487 default: 1488 WARN_ON(1); 1489 break; 1490 } 1491 1492 ret = nvif_object_map_handle(&mem->mem.object, 1493 &args, argc, 1494 &handle, &length); 1495 if (ret != 1) 1496 return ret ? ret : -EINVAL; 1497 1498 reg->bus.base = 0; 1499 reg->bus.offset = handle; 1500 } 1501 break; 1502 default: 1503 return -EINVAL; 1504 } 1505 return 0; 1506 } 1507 1508 static void 1509 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1510 { 1511 struct nouveau_drm *drm = nouveau_bdev(bdev); 1512 struct nouveau_mem *mem = nouveau_mem(reg); 1513 1514 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1515 switch (reg->mem_type) { 1516 case TTM_PL_TT: 1517 if (mem->kind) 1518 nvif_object_unmap_handle(&mem->mem.object); 1519 break; 1520 case TTM_PL_VRAM: 1521 nvif_object_unmap_handle(&mem->mem.object); 1522 break; 1523 default: 1524 break; 1525 } 1526 } 1527 } 1528 1529 static int 1530 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1531 { 1532 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1533 struct nouveau_bo *nvbo = nouveau_bo(bo); 1534 struct nvkm_device *device = nvxx_device(&drm->client.device); 1535 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1536 int i, ret; 1537 1538 /* as long as the bo isn't in vram, and isn't tiled, we've got 1539 * nothing to do here. 1540 */ 1541 if (bo->mem.mem_type != TTM_PL_VRAM) { 1542 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1543 !nvbo->kind) 1544 return 0; 1545 1546 if (bo->mem.mem_type == TTM_PL_SYSTEM) { 1547 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); 1548 1549 ret = nouveau_bo_validate(nvbo, false, false); 1550 if (ret) 1551 return ret; 1552 } 1553 return 0; 1554 } 1555 1556 /* make sure bo is in mappable vram */ 1557 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1558 bo->mem.start + bo->mem.num_pages < mappable) 1559 return 0; 1560 1561 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1562 nvbo->placements[i].fpfn = 0; 1563 nvbo->placements[i].lpfn = mappable; 1564 } 1565 1566 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1567 nvbo->busy_placements[i].fpfn = 0; 1568 nvbo->busy_placements[i].lpfn = mappable; 1569 } 1570 1571 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); 1572 return nouveau_bo_validate(nvbo, false, false); 1573 } 1574 1575 static int 1576 nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1577 { 1578 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1579 struct nouveau_drm *drm; 1580 struct device *dev; 1581 unsigned i; 1582 int r; 1583 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1584 1585 if (ttm->state != tt_unpopulated) 1586 return 0; 1587 1588 if (slave && ttm->sg) { 1589 /* make userspace faulting work */ 1590 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1591 ttm_dma->dma_address, ttm->num_pages); 1592 ttm->state = tt_unbound; 1593 return 0; 1594 } 1595 1596 drm = nouveau_bdev(ttm->bdev); 1597 dev = drm->dev->dev; 1598 1599 #if IS_ENABLED(CONFIG_AGP) 1600 if (drm->agp.bridge) { 1601 return ttm_agp_tt_populate(ttm, ctx); 1602 } 1603 #endif 1604 1605 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1606 if (swiotlb_nr_tbl()) { 1607 return ttm_dma_populate((void *)ttm, dev, ctx); 1608 } 1609 #endif 1610 1611 r = ttm_pool_populate(ttm, ctx); 1612 if (r) { 1613 return r; 1614 } 1615 1616 for (i = 0; i < ttm->num_pages; i++) { 1617 dma_addr_t addr; 1618 1619 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE, 1620 DMA_BIDIRECTIONAL); 1621 1622 if (dma_mapping_error(dev, addr)) { 1623 while (i--) { 1624 dma_unmap_page(dev, ttm_dma->dma_address[i], 1625 PAGE_SIZE, DMA_BIDIRECTIONAL); 1626 ttm_dma->dma_address[i] = 0; 1627 } 1628 ttm_pool_unpopulate(ttm); 1629 return -EFAULT; 1630 } 1631 1632 ttm_dma->dma_address[i] = addr; 1633 } 1634 return 0; 1635 } 1636 1637 static void 1638 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) 1639 { 1640 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1641 struct nouveau_drm *drm; 1642 struct device *dev; 1643 unsigned i; 1644 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1645 1646 if (slave) 1647 return; 1648 1649 drm = nouveau_bdev(ttm->bdev); 1650 dev = drm->dev->dev; 1651 1652 #if IS_ENABLED(CONFIG_AGP) 1653 if (drm->agp.bridge) { 1654 ttm_agp_tt_unpopulate(ttm); 1655 return; 1656 } 1657 #endif 1658 1659 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1660 if (swiotlb_nr_tbl()) { 1661 ttm_dma_unpopulate((void *)ttm, dev); 1662 return; 1663 } 1664 #endif 1665 1666 for (i = 0; i < ttm->num_pages; i++) { 1667 if (ttm_dma->dma_address[i]) { 1668 dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE, 1669 DMA_BIDIRECTIONAL); 1670 } 1671 } 1672 1673 ttm_pool_unpopulate(ttm); 1674 } 1675 1676 void 1677 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1678 { 1679 struct dma_resv *resv = nvbo->bo.base.resv; 1680 1681 if (exclusive) 1682 dma_resv_add_excl_fence(resv, &fence->base); 1683 else if (fence) 1684 dma_resv_add_shared_fence(resv, &fence->base); 1685 } 1686 1687 struct ttm_bo_driver nouveau_bo_driver = { 1688 .ttm_tt_create = &nouveau_ttm_tt_create, 1689 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1690 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1691 .invalidate_caches = nouveau_bo_invalidate_caches, 1692 .init_mem_type = nouveau_bo_init_mem_type, 1693 .eviction_valuable = ttm_bo_eviction_valuable, 1694 .evict_flags = nouveau_bo_evict_flags, 1695 .move_notify = nouveau_bo_move_ntfy, 1696 .move = nouveau_bo_move, 1697 .verify_access = nouveau_bo_verify_access, 1698 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, 1699 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1700 .io_mem_free = &nouveau_ttm_io_mem_free, 1701 }; 1702