1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 32 #include "nouveau_drv.h" 33 #include "nouveau_chan.h" 34 #include "nouveau_fence.h" 35 36 #include "nouveau_bo.h" 37 #include "nouveau_ttm.h" 38 #include "nouveau_gem.h" 39 #include "nouveau_mem.h" 40 #include "nouveau_vmm.h" 41 42 #include <nvif/class.h> 43 #include <nvif/if500b.h> 44 #include <nvif/if900b.h> 45 46 static int nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm, 47 struct ttm_resource *reg); 48 static void nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm); 49 50 /* 51 * NV10-NV40 tiling helpers 52 */ 53 54 static void 55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 56 u32 addr, u32 size, u32 pitch, u32 flags) 57 { 58 struct nouveau_drm *drm = nouveau_drm(dev); 59 int i = reg - drm->tile.reg; 60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 61 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 62 63 nouveau_fence_unref(®->fence); 64 65 if (tile->pitch) 66 nvkm_fb_tile_fini(fb, i, tile); 67 68 if (pitch) 69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 70 71 nvkm_fb_tile_prog(fb, i, tile); 72 } 73 74 static struct nouveau_drm_tile * 75 nv10_bo_get_tile_region(struct drm_device *dev, int i) 76 { 77 struct nouveau_drm *drm = nouveau_drm(dev); 78 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 79 80 spin_lock(&drm->tile.lock); 81 82 if (!tile->used && 83 (!tile->fence || nouveau_fence_done(tile->fence))) 84 tile->used = true; 85 else 86 tile = NULL; 87 88 spin_unlock(&drm->tile.lock); 89 return tile; 90 } 91 92 static void 93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 94 struct dma_fence *fence) 95 { 96 struct nouveau_drm *drm = nouveau_drm(dev); 97 98 if (tile) { 99 spin_lock(&drm->tile.lock); 100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 101 tile->used = false; 102 spin_unlock(&drm->tile.lock); 103 } 104 } 105 106 static struct nouveau_drm_tile * 107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 108 u32 size, u32 pitch, u32 zeta) 109 { 110 struct nouveau_drm *drm = nouveau_drm(dev); 111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 112 struct nouveau_drm_tile *tile, *found = NULL; 113 int i; 114 115 for (i = 0; i < fb->tile.regions; i++) { 116 tile = nv10_bo_get_tile_region(dev, i); 117 118 if (pitch && !found) { 119 found = tile; 120 continue; 121 122 } else if (tile && fb->tile.region[i].pitch) { 123 /* Kill an unused tile region. */ 124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 125 } 126 127 nv10_bo_put_tile_region(dev, tile, NULL); 128 } 129 130 if (found) 131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 132 return found; 133 } 134 135 static void 136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 137 { 138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 139 struct drm_device *dev = drm->dev; 140 struct nouveau_bo *nvbo = nouveau_bo(bo); 141 142 WARN_ON(nvbo->bo.pin_count > 0); 143 nouveau_bo_del_io_reserve_lru(bo); 144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 145 146 /* 147 * If nouveau_bo_new() allocated this buffer, the GEM object was never 148 * initialized, so don't attempt to release it. 149 */ 150 if (bo->base.dev) 151 drm_gem_object_release(&bo->base); 152 153 kfree(nvbo); 154 } 155 156 static inline u64 157 roundup_64(u64 x, u32 y) 158 { 159 x += y - 1; 160 do_div(x, y); 161 return x * y; 162 } 163 164 static void 165 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size) 166 { 167 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 168 struct nvif_device *device = &drm->client.device; 169 170 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 171 if (nvbo->mode) { 172 if (device->info.chipset >= 0x40) { 173 *align = 65536; 174 *size = roundup_64(*size, 64 * nvbo->mode); 175 176 } else if (device->info.chipset >= 0x30) { 177 *align = 32768; 178 *size = roundup_64(*size, 64 * nvbo->mode); 179 180 } else if (device->info.chipset >= 0x20) { 181 *align = 16384; 182 *size = roundup_64(*size, 64 * nvbo->mode); 183 184 } else if (device->info.chipset >= 0x10) { 185 *align = 16384; 186 *size = roundup_64(*size, 32 * nvbo->mode); 187 } 188 } 189 } else { 190 *size = roundup_64(*size, (1 << nvbo->page)); 191 *align = max((1 << nvbo->page), *align); 192 } 193 194 *size = roundup_64(*size, PAGE_SIZE); 195 } 196 197 struct nouveau_bo * 198 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain, 199 u32 tile_mode, u32 tile_flags) 200 { 201 struct nouveau_drm *drm = cli->drm; 202 struct nouveau_bo *nvbo; 203 struct nvif_mmu *mmu = &cli->mmu; 204 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm; 205 int i, pi = -1; 206 207 if (!*size) { 208 NV_WARN(drm, "skipped size %016llx\n", *size); 209 return ERR_PTR(-EINVAL); 210 } 211 212 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 213 if (!nvbo) 214 return ERR_PTR(-ENOMEM); 215 INIT_LIST_HEAD(&nvbo->head); 216 INIT_LIST_HEAD(&nvbo->entry); 217 INIT_LIST_HEAD(&nvbo->vma_list); 218 nvbo->bo.bdev = &drm->ttm.bdev; 219 220 /* This is confusing, and doesn't actually mean we want an uncached 221 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 222 * into in nouveau_gem_new(). 223 */ 224 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) { 225 /* Determine if we can get a cache-coherent map, forcing 226 * uncached mapping if we can't. 227 */ 228 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 229 nvbo->force_coherent = true; 230 } 231 232 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 233 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 234 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 235 kfree(nvbo); 236 return ERR_PTR(-EINVAL); 237 } 238 239 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 240 } else 241 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 242 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 243 nvbo->comp = (tile_flags & 0x00030000) >> 16; 244 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 245 kfree(nvbo); 246 return ERR_PTR(-EINVAL); 247 } 248 } else { 249 nvbo->zeta = (tile_flags & 0x00000007); 250 } 251 nvbo->mode = tile_mode; 252 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 253 254 /* Determine the desirable target GPU page size for the buffer. */ 255 for (i = 0; i < vmm->page_nr; i++) { 256 /* Because we cannot currently allow VMM maps to fail 257 * during buffer migration, we need to determine page 258 * size for the buffer up-front, and pre-allocate its 259 * page tables. 260 * 261 * Skip page sizes that can't support needed domains. 262 */ 263 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 264 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram) 265 continue; 266 if ((domain & NOUVEAU_GEM_DOMAIN_GART) && 267 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 268 continue; 269 270 /* Select this page size if it's the first that supports 271 * the potential memory domains, or when it's compatible 272 * with the requested compression settings. 273 */ 274 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 275 pi = i; 276 277 /* Stop once the buffer is larger than the current page size. */ 278 if (*size >= 1ULL << vmm->page[i].shift) 279 break; 280 } 281 282 if (WARN_ON(pi < 0)) 283 return ERR_PTR(-EINVAL); 284 285 /* Disable compression if suitable settings couldn't be found. */ 286 if (nvbo->comp && !vmm->page[pi].comp) { 287 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 288 nvbo->kind = mmu->kind[nvbo->kind]; 289 nvbo->comp = 0; 290 } 291 nvbo->page = vmm->page[pi].shift; 292 293 nouveau_bo_fixup_align(nvbo, align, size); 294 295 return nvbo; 296 } 297 298 int 299 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain, 300 struct sg_table *sg, struct dma_resv *robj) 301 { 302 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device; 303 int ret; 304 305 nouveau_bo_placement_set(nvbo, domain, 0); 306 INIT_LIST_HEAD(&nvbo->io_reserve_lru); 307 308 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type, 309 &nvbo->placement, align >> PAGE_SHIFT, false, sg, 310 robj, nouveau_bo_del_ttm); 311 if (ret) { 312 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 313 return ret; 314 } 315 316 return 0; 317 } 318 319 int 320 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 321 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags, 322 struct sg_table *sg, struct dma_resv *robj, 323 struct nouveau_bo **pnvbo) 324 { 325 struct nouveau_bo *nvbo; 326 int ret; 327 328 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode, 329 tile_flags); 330 if (IS_ERR(nvbo)) 331 return PTR_ERR(nvbo); 332 333 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj); 334 if (ret) 335 return ret; 336 337 *pnvbo = nvbo; 338 return 0; 339 } 340 341 static void 342 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain) 343 { 344 *n = 0; 345 346 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) { 347 pl[*n].mem_type = TTM_PL_VRAM; 348 pl[*n].flags = 0; 349 (*n)++; 350 } 351 if (domain & NOUVEAU_GEM_DOMAIN_GART) { 352 pl[*n].mem_type = TTM_PL_TT; 353 pl[*n].flags = 0; 354 (*n)++; 355 } 356 if (domain & NOUVEAU_GEM_DOMAIN_CPU) { 357 pl[*n].mem_type = TTM_PL_SYSTEM; 358 pl[(*n)++].flags = 0; 359 } 360 } 361 362 static void 363 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain) 364 { 365 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 366 u64 vram_size = drm->client.device.info.ram_size; 367 unsigned i, fpfn, lpfn; 368 369 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 370 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) && 371 nvbo->bo.base.size < vram_size / 4) { 372 /* 373 * Make sure that the color and depth buffers are handled 374 * by independent memory controller units. Up to a 9x 375 * speed up when alpha-blending and depth-test are enabled 376 * at the same time. 377 */ 378 if (nvbo->zeta) { 379 fpfn = (vram_size / 2) >> PAGE_SHIFT; 380 lpfn = ~0; 381 } else { 382 fpfn = 0; 383 lpfn = (vram_size / 2) >> PAGE_SHIFT; 384 } 385 for (i = 0; i < nvbo->placement.num_placement; ++i) { 386 nvbo->placements[i].fpfn = fpfn; 387 nvbo->placements[i].lpfn = lpfn; 388 } 389 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 390 nvbo->busy_placements[i].fpfn = fpfn; 391 nvbo->busy_placements[i].lpfn = lpfn; 392 } 393 } 394 } 395 396 void 397 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain, 398 uint32_t busy) 399 { 400 struct ttm_placement *pl = &nvbo->placement; 401 402 pl->placement = nvbo->placements; 403 set_placement_list(nvbo->placements, &pl->num_placement, domain); 404 405 pl->busy_placement = nvbo->busy_placements; 406 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 407 domain | busy); 408 409 set_placement_range(nvbo, domain); 410 } 411 412 int 413 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig) 414 { 415 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 416 struct ttm_buffer_object *bo = &nvbo->bo; 417 bool force = false, evict = false; 418 int ret; 419 420 ret = ttm_bo_reserve(bo, false, false, NULL); 421 if (ret) 422 return ret; 423 424 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 425 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) { 426 if (!nvbo->contig) { 427 nvbo->contig = true; 428 force = true; 429 evict = true; 430 } 431 } 432 433 if (nvbo->bo.pin_count) { 434 bool error = evict; 435 436 switch (bo->mem.mem_type) { 437 case TTM_PL_VRAM: 438 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM); 439 break; 440 case TTM_PL_TT: 441 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART); 442 default: 443 break; 444 } 445 446 if (error) { 447 NV_ERROR(drm, "bo %p pinned elsewhere: " 448 "0x%08x vs 0x%08x\n", bo, 449 bo->mem.mem_type, domain); 450 ret = -EBUSY; 451 } 452 ttm_bo_pin(&nvbo->bo); 453 goto out; 454 } 455 456 if (evict) { 457 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0); 458 ret = nouveau_bo_validate(nvbo, false, false); 459 if (ret) 460 goto out; 461 } 462 463 nouveau_bo_placement_set(nvbo, domain, 0); 464 ret = nouveau_bo_validate(nvbo, false, false); 465 if (ret) 466 goto out; 467 468 ttm_bo_pin(&nvbo->bo); 469 470 switch (bo->mem.mem_type) { 471 case TTM_PL_VRAM: 472 drm->gem.vram_available -= bo->base.size; 473 break; 474 case TTM_PL_TT: 475 drm->gem.gart_available -= bo->base.size; 476 break; 477 default: 478 break; 479 } 480 481 out: 482 if (force && ret) 483 nvbo->contig = false; 484 ttm_bo_unreserve(bo); 485 return ret; 486 } 487 488 int 489 nouveau_bo_unpin(struct nouveau_bo *nvbo) 490 { 491 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 492 struct ttm_buffer_object *bo = &nvbo->bo; 493 int ret; 494 495 ret = ttm_bo_reserve(bo, false, false, NULL); 496 if (ret) 497 return ret; 498 499 ttm_bo_unpin(&nvbo->bo); 500 if (!nvbo->bo.pin_count) { 501 switch (bo->mem.mem_type) { 502 case TTM_PL_VRAM: 503 drm->gem.vram_available += bo->base.size; 504 break; 505 case TTM_PL_TT: 506 drm->gem.gart_available += bo->base.size; 507 break; 508 default: 509 break; 510 } 511 } 512 513 ttm_bo_unreserve(bo); 514 return 0; 515 } 516 517 int 518 nouveau_bo_map(struct nouveau_bo *nvbo) 519 { 520 int ret; 521 522 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 523 if (ret) 524 return ret; 525 526 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 527 528 ttm_bo_unreserve(&nvbo->bo); 529 return ret; 530 } 531 532 void 533 nouveau_bo_unmap(struct nouveau_bo *nvbo) 534 { 535 if (!nvbo) 536 return; 537 538 ttm_bo_kunmap(&nvbo->kmap); 539 } 540 541 void 542 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 543 { 544 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 545 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 546 int i, j; 547 548 if (!ttm_dma) 549 return; 550 if (!ttm_dma->pages) { 551 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma); 552 return; 553 } 554 555 /* Don't waste time looping if the object is coherent */ 556 if (nvbo->force_coherent) 557 return; 558 559 i = 0; 560 while (i < ttm_dma->num_pages) { 561 struct page *p = ttm_dma->pages[i]; 562 size_t num_pages = 1; 563 564 for (j = i + 1; j < ttm_dma->num_pages; ++j) { 565 if (++p != ttm_dma->pages[j]) 566 break; 567 568 ++num_pages; 569 } 570 dma_sync_single_for_device(drm->dev->dev, 571 ttm_dma->dma_address[i], 572 num_pages * PAGE_SIZE, DMA_TO_DEVICE); 573 i += num_pages; 574 } 575 } 576 577 void 578 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 579 { 580 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 581 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 582 int i, j; 583 584 if (!ttm_dma) 585 return; 586 if (!ttm_dma->pages) { 587 NV_DEBUG(drm, "ttm_dma 0x%p: pages NULL\n", ttm_dma); 588 return; 589 } 590 591 /* Don't waste time looping if the object is coherent */ 592 if (nvbo->force_coherent) 593 return; 594 595 i = 0; 596 while (i < ttm_dma->num_pages) { 597 struct page *p = ttm_dma->pages[i]; 598 size_t num_pages = 1; 599 600 for (j = i + 1; j < ttm_dma->num_pages; ++j) { 601 if (++p != ttm_dma->pages[j]) 602 break; 603 604 ++num_pages; 605 } 606 607 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 608 num_pages * PAGE_SIZE, DMA_FROM_DEVICE); 609 i += num_pages; 610 } 611 } 612 613 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo) 614 { 615 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 616 struct nouveau_bo *nvbo = nouveau_bo(bo); 617 618 mutex_lock(&drm->ttm.io_reserve_mutex); 619 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru); 620 mutex_unlock(&drm->ttm.io_reserve_mutex); 621 } 622 623 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo) 624 { 625 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 626 struct nouveau_bo *nvbo = nouveau_bo(bo); 627 628 mutex_lock(&drm->ttm.io_reserve_mutex); 629 list_del_init(&nvbo->io_reserve_lru); 630 mutex_unlock(&drm->ttm.io_reserve_mutex); 631 } 632 633 int 634 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 635 bool no_wait_gpu) 636 { 637 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 638 int ret; 639 640 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 641 if (ret) 642 return ret; 643 644 nouveau_bo_sync_for_device(nvbo); 645 646 return 0; 647 } 648 649 void 650 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 651 { 652 bool is_iomem; 653 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 654 655 mem += index; 656 657 if (is_iomem) 658 iowrite16_native(val, (void __force __iomem *)mem); 659 else 660 *mem = val; 661 } 662 663 u32 664 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 665 { 666 bool is_iomem; 667 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 668 669 mem += index; 670 671 if (is_iomem) 672 return ioread32_native((void __force __iomem *)mem); 673 else 674 return *mem; 675 } 676 677 void 678 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 679 { 680 bool is_iomem; 681 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 682 683 mem += index; 684 685 if (is_iomem) 686 iowrite32_native(val, (void __force __iomem *)mem); 687 else 688 *mem = val; 689 } 690 691 static struct ttm_tt * 692 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 693 { 694 #if IS_ENABLED(CONFIG_AGP) 695 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 696 697 if (drm->agp.bridge) { 698 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 699 } 700 #endif 701 702 return nouveau_sgdma_create_ttm(bo, page_flags); 703 } 704 705 static int 706 nouveau_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm, 707 struct ttm_resource *reg) 708 { 709 #if IS_ENABLED(CONFIG_AGP) 710 struct nouveau_drm *drm = nouveau_bdev(bdev); 711 #endif 712 if (!reg) 713 return -EINVAL; 714 #if IS_ENABLED(CONFIG_AGP) 715 if (drm->agp.bridge) 716 return ttm_agp_bind(ttm, reg); 717 #endif 718 return nouveau_sgdma_bind(bdev, ttm, reg); 719 } 720 721 static void 722 nouveau_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm) 723 { 724 #if IS_ENABLED(CONFIG_AGP) 725 struct nouveau_drm *drm = nouveau_bdev(bdev); 726 727 if (drm->agp.bridge) { 728 ttm_agp_unbind(ttm); 729 return; 730 } 731 #endif 732 nouveau_sgdma_unbind(bdev, ttm); 733 } 734 735 static void 736 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 737 { 738 struct nouveau_bo *nvbo = nouveau_bo(bo); 739 740 switch (bo->mem.mem_type) { 741 case TTM_PL_VRAM: 742 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 743 NOUVEAU_GEM_DOMAIN_CPU); 744 break; 745 default: 746 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0); 747 break; 748 } 749 750 *pl = nvbo->placement; 751 } 752 753 static int 754 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 755 struct ttm_resource *reg) 756 { 757 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 758 struct nouveau_mem *new_mem = nouveau_mem(reg); 759 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 760 int ret; 761 762 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 763 old_mem->mem.size, &old_mem->vma[0]); 764 if (ret) 765 return ret; 766 767 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 768 new_mem->mem.size, &old_mem->vma[1]); 769 if (ret) 770 goto done; 771 772 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 773 if (ret) 774 goto done; 775 776 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 777 done: 778 if (ret) { 779 nvif_vmm_put(vmm, &old_mem->vma[1]); 780 nvif_vmm_put(vmm, &old_mem->vma[0]); 781 } 782 return 0; 783 } 784 785 static int 786 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, 787 struct ttm_operation_ctx *ctx, 788 struct ttm_resource *new_reg) 789 { 790 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 791 struct nouveau_channel *chan = drm->ttm.chan; 792 struct nouveau_cli *cli = (void *)chan->user.client; 793 struct nouveau_fence *fence; 794 int ret; 795 796 /* create temporary vmas for the transfer and attach them to the 797 * old nvkm_mem node, these will get cleaned up after ttm has 798 * destroyed the ttm_resource 799 */ 800 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 801 ret = nouveau_bo_move_prep(drm, bo, new_reg); 802 if (ret) 803 return ret; 804 } 805 806 if (drm_drv_uses_atomic_modeset(drm->dev)) 807 mutex_lock(&cli->mutex); 808 else 809 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 810 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible); 811 if (ret == 0) { 812 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 813 if (ret == 0) { 814 ret = nouveau_fence_new(chan, false, &fence); 815 if (ret == 0) { 816 ret = ttm_bo_move_accel_cleanup(bo, 817 &fence->base, 818 evict, false, 819 new_reg); 820 nouveau_fence_unref(&fence); 821 } 822 } 823 } 824 mutex_unlock(&cli->mutex); 825 return ret; 826 } 827 828 void 829 nouveau_bo_move_init(struct nouveau_drm *drm) 830 { 831 static const struct _method_table { 832 const char *name; 833 int engine; 834 s32 oclass; 835 int (*exec)(struct nouveau_channel *, 836 struct ttm_buffer_object *, 837 struct ttm_resource *, struct ttm_resource *); 838 int (*init)(struct nouveau_channel *, u32 handle); 839 } _methods[] = { 840 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, 841 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, 842 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 843 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 844 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 845 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 846 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 847 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 848 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 849 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 850 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 851 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 852 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 853 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 854 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 855 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 856 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 857 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 858 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 859 {}, 860 }; 861 const struct _method_table *mthd = _methods; 862 const char *name = "CPU"; 863 int ret; 864 865 do { 866 struct nouveau_channel *chan; 867 868 if (mthd->engine) 869 chan = drm->cechan; 870 else 871 chan = drm->channel; 872 if (chan == NULL) 873 continue; 874 875 ret = nvif_object_ctor(&chan->user, "ttmBoMove", 876 mthd->oclass | (mthd->engine << 16), 877 mthd->oclass, NULL, 0, 878 &drm->ttm.copy); 879 if (ret == 0) { 880 ret = mthd->init(chan, drm->ttm.copy.handle); 881 if (ret) { 882 nvif_object_dtor(&drm->ttm.copy); 883 continue; 884 } 885 886 drm->ttm.move = mthd->exec; 887 drm->ttm.chan = chan; 888 name = mthd->name; 889 break; 890 } 891 } while ((++mthd)->exec); 892 893 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 894 } 895 896 static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, 897 struct ttm_resource *new_reg) 898 { 899 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 900 struct nouveau_bo *nvbo = nouveau_bo(bo); 901 struct nouveau_vma *vma; 902 903 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 904 if (bo->destroy != nouveau_bo_del_ttm) 905 return; 906 907 nouveau_bo_del_io_reserve_lru(bo); 908 909 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 910 mem->mem.page == nvbo->page) { 911 list_for_each_entry(vma, &nvbo->vma_list, head) { 912 nouveau_vma_map(vma, mem); 913 } 914 } else { 915 list_for_each_entry(vma, &nvbo->vma_list, head) { 916 WARN_ON(ttm_bo_wait(bo, false, false)); 917 nouveau_vma_unmap(vma); 918 } 919 } 920 921 if (new_reg) { 922 if (new_reg->mm_node) 923 nvbo->offset = (new_reg->start << PAGE_SHIFT); 924 else 925 nvbo->offset = 0; 926 } 927 928 } 929 930 static int 931 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg, 932 struct nouveau_drm_tile **new_tile) 933 { 934 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 935 struct drm_device *dev = drm->dev; 936 struct nouveau_bo *nvbo = nouveau_bo(bo); 937 u64 offset = new_reg->start << PAGE_SHIFT; 938 939 *new_tile = NULL; 940 if (new_reg->mem_type != TTM_PL_VRAM) 941 return 0; 942 943 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 944 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size, 945 nvbo->mode, nvbo->zeta); 946 } 947 948 return 0; 949 } 950 951 static void 952 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 953 struct nouveau_drm_tile *new_tile, 954 struct nouveau_drm_tile **old_tile) 955 { 956 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 957 struct drm_device *dev = drm->dev; 958 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv); 959 960 nv10_bo_put_tile_region(dev, *old_tile, fence); 961 *old_tile = new_tile; 962 } 963 964 static int 965 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 966 struct ttm_operation_ctx *ctx, 967 struct ttm_resource *new_reg, 968 struct ttm_place *hop) 969 { 970 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 971 struct nouveau_bo *nvbo = nouveau_bo(bo); 972 struct ttm_resource *old_reg = &bo->mem; 973 struct nouveau_drm_tile *new_tile = NULL; 974 int ret = 0; 975 976 977 if (new_reg->mem_type == TTM_PL_TT) { 978 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg); 979 if (ret) 980 return ret; 981 } 982 983 nouveau_bo_move_ntfy(bo, new_reg); 984 ret = ttm_bo_wait_ctx(bo, ctx); 985 if (ret) 986 goto out_ntfy; 987 988 if (nvbo->bo.pin_count) 989 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 990 991 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 992 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 993 if (ret) 994 goto out_ntfy; 995 } 996 997 /* Fake bo copy. */ 998 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 999 ttm_bo_move_null(bo, new_reg); 1000 goto out; 1001 } 1002 1003 if (old_reg->mem_type == TTM_PL_SYSTEM && 1004 new_reg->mem_type == TTM_PL_TT) { 1005 ttm_bo_move_null(bo, new_reg); 1006 goto out; 1007 } 1008 1009 if (old_reg->mem_type == TTM_PL_TT && 1010 new_reg->mem_type == TTM_PL_SYSTEM) { 1011 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm); 1012 ttm_resource_free(bo, &bo->mem); 1013 ttm_bo_assign_mem(bo, new_reg); 1014 goto out; 1015 } 1016 1017 /* Hardware assisted copy. */ 1018 if (drm->ttm.move) { 1019 if ((old_reg->mem_type == TTM_PL_SYSTEM && 1020 new_reg->mem_type == TTM_PL_VRAM) || 1021 (old_reg->mem_type == TTM_PL_VRAM && 1022 new_reg->mem_type == TTM_PL_SYSTEM)) { 1023 hop->fpfn = 0; 1024 hop->lpfn = 0; 1025 hop->mem_type = TTM_PL_TT; 1026 hop->flags = 0; 1027 return -EMULTIHOP; 1028 } 1029 ret = nouveau_bo_move_m2mf(bo, evict, ctx, 1030 new_reg); 1031 } else 1032 ret = -ENODEV; 1033 1034 if (ret) { 1035 /* Fallback to software copy. */ 1036 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1037 } 1038 1039 out: 1040 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1041 if (ret) 1042 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1043 else 1044 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1045 } 1046 out_ntfy: 1047 if (ret) { 1048 nouveau_bo_move_ntfy(bo, &bo->mem); 1049 } 1050 return ret; 1051 } 1052 1053 static void 1054 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm, 1055 struct ttm_resource *reg) 1056 { 1057 struct nouveau_mem *mem = nouveau_mem(reg); 1058 1059 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1060 switch (reg->mem_type) { 1061 case TTM_PL_TT: 1062 if (mem->kind) 1063 nvif_object_unmap_handle(&mem->mem.object); 1064 break; 1065 case TTM_PL_VRAM: 1066 nvif_object_unmap_handle(&mem->mem.object); 1067 break; 1068 default: 1069 break; 1070 } 1071 } 1072 } 1073 1074 static int 1075 nouveau_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *reg) 1076 { 1077 struct nouveau_drm *drm = nouveau_bdev(bdev); 1078 struct nvkm_device *device = nvxx_device(&drm->client.device); 1079 struct nouveau_mem *mem = nouveau_mem(reg); 1080 struct nvif_mmu *mmu = &drm->client.mmu; 1081 int ret; 1082 1083 mutex_lock(&drm->ttm.io_reserve_mutex); 1084 retry: 1085 switch (reg->mem_type) { 1086 case TTM_PL_SYSTEM: 1087 /* System memory */ 1088 ret = 0; 1089 goto out; 1090 case TTM_PL_TT: 1091 #if IS_ENABLED(CONFIG_AGP) 1092 if (drm->agp.bridge) { 1093 reg->bus.offset = (reg->start << PAGE_SHIFT) + 1094 drm->agp.base; 1095 reg->bus.is_iomem = !drm->agp.cma; 1096 reg->bus.caching = ttm_write_combined; 1097 } 1098 #endif 1099 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || 1100 !mem->kind) { 1101 /* untiled */ 1102 ret = 0; 1103 break; 1104 } 1105 fallthrough; /* tiled memory */ 1106 case TTM_PL_VRAM: 1107 reg->bus.offset = (reg->start << PAGE_SHIFT) + 1108 device->func->resource_addr(device, 1); 1109 reg->bus.is_iomem = true; 1110 1111 /* Some BARs do not support being ioremapped WC */ 1112 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 1113 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED) 1114 reg->bus.caching = ttm_uncached; 1115 else 1116 reg->bus.caching = ttm_write_combined; 1117 1118 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1119 union { 1120 struct nv50_mem_map_v0 nv50; 1121 struct gf100_mem_map_v0 gf100; 1122 } args; 1123 u64 handle, length; 1124 u32 argc = 0; 1125 1126 switch (mem->mem.object.oclass) { 1127 case NVIF_CLASS_MEM_NV50: 1128 args.nv50.version = 0; 1129 args.nv50.ro = 0; 1130 args.nv50.kind = mem->kind; 1131 args.nv50.comp = mem->comp; 1132 argc = sizeof(args.nv50); 1133 break; 1134 case NVIF_CLASS_MEM_GF100: 1135 args.gf100.version = 0; 1136 args.gf100.ro = 0; 1137 args.gf100.kind = mem->kind; 1138 argc = sizeof(args.gf100); 1139 break; 1140 default: 1141 WARN_ON(1); 1142 break; 1143 } 1144 1145 ret = nvif_object_map_handle(&mem->mem.object, 1146 &args, argc, 1147 &handle, &length); 1148 if (ret != 1) { 1149 if (WARN_ON(ret == 0)) 1150 ret = -EINVAL; 1151 goto out; 1152 } 1153 1154 reg->bus.offset = handle; 1155 } 1156 ret = 0; 1157 break; 1158 default: 1159 ret = -EINVAL; 1160 } 1161 1162 out: 1163 if (ret == -ENOSPC) { 1164 struct nouveau_bo *nvbo; 1165 1166 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru, 1167 typeof(*nvbo), 1168 io_reserve_lru); 1169 if (nvbo) { 1170 list_del_init(&nvbo->io_reserve_lru); 1171 drm_vma_node_unmap(&nvbo->bo.base.vma_node, 1172 bdev->dev_mapping); 1173 nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem); 1174 goto retry; 1175 } 1176 1177 } 1178 mutex_unlock(&drm->ttm.io_reserve_mutex); 1179 return ret; 1180 } 1181 1182 static void 1183 nouveau_ttm_io_mem_free(struct ttm_device *bdev, struct ttm_resource *reg) 1184 { 1185 struct nouveau_drm *drm = nouveau_bdev(bdev); 1186 1187 mutex_lock(&drm->ttm.io_reserve_mutex); 1188 nouveau_ttm_io_mem_free_locked(drm, reg); 1189 mutex_unlock(&drm->ttm.io_reserve_mutex); 1190 } 1191 1192 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1193 { 1194 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1195 struct nouveau_bo *nvbo = nouveau_bo(bo); 1196 struct nvkm_device *device = nvxx_device(&drm->client.device); 1197 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1198 int i, ret; 1199 1200 /* as long as the bo isn't in vram, and isn't tiled, we've got 1201 * nothing to do here. 1202 */ 1203 if (bo->mem.mem_type != TTM_PL_VRAM) { 1204 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1205 !nvbo->kind) 1206 return 0; 1207 1208 if (bo->mem.mem_type != TTM_PL_SYSTEM) 1209 return 0; 1210 1211 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0); 1212 1213 } else { 1214 /* make sure bo is in mappable vram */ 1215 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1216 bo->mem.start + bo->mem.num_pages < mappable) 1217 return 0; 1218 1219 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1220 nvbo->placements[i].fpfn = 0; 1221 nvbo->placements[i].lpfn = mappable; 1222 } 1223 1224 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1225 nvbo->busy_placements[i].fpfn = 0; 1226 nvbo->busy_placements[i].lpfn = mappable; 1227 } 1228 1229 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0); 1230 } 1231 1232 ret = nouveau_bo_validate(nvbo, false, false); 1233 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS)) 1234 return VM_FAULT_NOPAGE; 1235 else if (unlikely(ret)) 1236 return VM_FAULT_SIGBUS; 1237 1238 ttm_bo_move_to_lru_tail_unlocked(bo); 1239 return 0; 1240 } 1241 1242 static int 1243 nouveau_ttm_tt_populate(struct ttm_device *bdev, 1244 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1245 { 1246 struct ttm_tt *ttm_dma = (void *)ttm; 1247 struct nouveau_drm *drm; 1248 struct device *dev; 1249 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1250 1251 if (ttm_tt_is_populated(ttm)) 1252 return 0; 1253 1254 if (slave && ttm->sg) { 1255 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address, 1256 ttm->num_pages); 1257 return 0; 1258 } 1259 1260 drm = nouveau_bdev(bdev); 1261 dev = drm->dev->dev; 1262 1263 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx); 1264 } 1265 1266 static void 1267 nouveau_ttm_tt_unpopulate(struct ttm_device *bdev, 1268 struct ttm_tt *ttm) 1269 { 1270 struct nouveau_drm *drm; 1271 struct device *dev; 1272 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1273 1274 if (slave) 1275 return; 1276 1277 drm = nouveau_bdev(bdev); 1278 dev = drm->dev->dev; 1279 1280 return ttm_pool_free(&drm->ttm.bdev.pool, ttm); 1281 } 1282 1283 static void 1284 nouveau_ttm_tt_destroy(struct ttm_device *bdev, 1285 struct ttm_tt *ttm) 1286 { 1287 #if IS_ENABLED(CONFIG_AGP) 1288 struct nouveau_drm *drm = nouveau_bdev(bdev); 1289 if (drm->agp.bridge) { 1290 ttm_agp_unbind(ttm); 1291 ttm_tt_destroy_common(bdev, ttm); 1292 ttm_agp_destroy(ttm); 1293 return; 1294 } 1295 #endif 1296 nouveau_sgdma_destroy(bdev, ttm); 1297 } 1298 1299 void 1300 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1301 { 1302 struct dma_resv *resv = nvbo->bo.base.resv; 1303 1304 if (exclusive) 1305 dma_resv_add_excl_fence(resv, &fence->base); 1306 else if (fence) 1307 dma_resv_add_shared_fence(resv, &fence->base); 1308 } 1309 1310 static void 1311 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1312 { 1313 nouveau_bo_move_ntfy(bo, NULL); 1314 } 1315 1316 struct ttm_device_funcs nouveau_bo_driver = { 1317 .ttm_tt_create = &nouveau_ttm_tt_create, 1318 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1319 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1320 .ttm_tt_destroy = &nouveau_ttm_tt_destroy, 1321 .eviction_valuable = ttm_bo_eviction_valuable, 1322 .evict_flags = nouveau_bo_evict_flags, 1323 .delete_mem_notify = nouveau_bo_delete_mem_notify, 1324 .move = nouveau_bo_move, 1325 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1326 .io_mem_free = &nouveau_ttm_io_mem_free, 1327 }; 1328