1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 #include <linux/swiotlb.h> 32 33 #include "nouveau_drv.h" 34 #include "nouveau_dma.h" 35 #include "nouveau_fence.h" 36 37 #include "nouveau_bo.h" 38 #include "nouveau_ttm.h" 39 #include "nouveau_gem.h" 40 #include "nouveau_mem.h" 41 #include "nouveau_vmm.h" 42 43 #include <nvif/class.h> 44 #include <nvif/if500b.h> 45 #include <nvif/if900b.h> 46 47 /* 48 * NV10-NV40 tiling helpers 49 */ 50 51 static void 52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 53 u32 addr, u32 size, u32 pitch, u32 flags) 54 { 55 struct nouveau_drm *drm = nouveau_drm(dev); 56 int i = reg - drm->tile.reg; 57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 58 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 59 60 nouveau_fence_unref(®->fence); 61 62 if (tile->pitch) 63 nvkm_fb_tile_fini(fb, i, tile); 64 65 if (pitch) 66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 67 68 nvkm_fb_tile_prog(fb, i, tile); 69 } 70 71 static struct nouveau_drm_tile * 72 nv10_bo_get_tile_region(struct drm_device *dev, int i) 73 { 74 struct nouveau_drm *drm = nouveau_drm(dev); 75 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 76 77 spin_lock(&drm->tile.lock); 78 79 if (!tile->used && 80 (!tile->fence || nouveau_fence_done(tile->fence))) 81 tile->used = true; 82 else 83 tile = NULL; 84 85 spin_unlock(&drm->tile.lock); 86 return tile; 87 } 88 89 static void 90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 91 struct dma_fence *fence) 92 { 93 struct nouveau_drm *drm = nouveau_drm(dev); 94 95 if (tile) { 96 spin_lock(&drm->tile.lock); 97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 98 tile->used = false; 99 spin_unlock(&drm->tile.lock); 100 } 101 } 102 103 static struct nouveau_drm_tile * 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 105 u32 size, u32 pitch, u32 zeta) 106 { 107 struct nouveau_drm *drm = nouveau_drm(dev); 108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 109 struct nouveau_drm_tile *tile, *found = NULL; 110 int i; 111 112 for (i = 0; i < fb->tile.regions; i++) { 113 tile = nv10_bo_get_tile_region(dev, i); 114 115 if (pitch && !found) { 116 found = tile; 117 continue; 118 119 } else if (tile && fb->tile.region[i].pitch) { 120 /* Kill an unused tile region. */ 121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 122 } 123 124 nv10_bo_put_tile_region(dev, tile, NULL); 125 } 126 127 if (found) 128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 129 return found; 130 } 131 132 static void 133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 134 { 135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 136 struct drm_device *dev = drm->dev; 137 struct nouveau_bo *nvbo = nouveau_bo(bo); 138 139 if (unlikely(nvbo->bo.base.filp)) 140 DRM_ERROR("bo %p still attached to GEM object\n", bo); 141 WARN_ON(nvbo->pin_refcnt > 0); 142 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 143 kfree(nvbo); 144 } 145 146 static inline u64 147 roundup_64(u64 x, u32 y) 148 { 149 x += y - 1; 150 do_div(x, y); 151 return x * y; 152 } 153 154 static void 155 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, 156 int *align, u64 *size) 157 { 158 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 159 struct nvif_device *device = &drm->client.device; 160 161 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 162 if (nvbo->mode) { 163 if (device->info.chipset >= 0x40) { 164 *align = 65536; 165 *size = roundup_64(*size, 64 * nvbo->mode); 166 167 } else if (device->info.chipset >= 0x30) { 168 *align = 32768; 169 *size = roundup_64(*size, 64 * nvbo->mode); 170 171 } else if (device->info.chipset >= 0x20) { 172 *align = 16384; 173 *size = roundup_64(*size, 64 * nvbo->mode); 174 175 } else if (device->info.chipset >= 0x10) { 176 *align = 16384; 177 *size = roundup_64(*size, 32 * nvbo->mode); 178 } 179 } 180 } else { 181 *size = roundup_64(*size, (1 << nvbo->page)); 182 *align = max((1 << nvbo->page), *align); 183 } 184 185 *size = roundup_64(*size, PAGE_SIZE); 186 } 187 188 int 189 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 190 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, 191 struct sg_table *sg, struct reservation_object *robj, 192 struct nouveau_bo **pnvbo) 193 { 194 struct nouveau_drm *drm = cli->drm; 195 struct nouveau_bo *nvbo; 196 struct nvif_mmu *mmu = &cli->mmu; 197 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm; 198 size_t acc_size; 199 int type = ttm_bo_type_device; 200 int ret, i, pi = -1; 201 202 if (!size) { 203 NV_WARN(drm, "skipped size %016llx\n", size); 204 return -EINVAL; 205 } 206 207 if (sg) 208 type = ttm_bo_type_sg; 209 210 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 211 if (!nvbo) 212 return -ENOMEM; 213 INIT_LIST_HEAD(&nvbo->head); 214 INIT_LIST_HEAD(&nvbo->entry); 215 INIT_LIST_HEAD(&nvbo->vma_list); 216 nvbo->bo.bdev = &drm->ttm.bdev; 217 218 /* This is confusing, and doesn't actually mean we want an uncached 219 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 220 * into in nouveau_gem_new(). 221 */ 222 if (flags & TTM_PL_FLAG_UNCACHED) { 223 /* Determine if we can get a cache-coherent map, forcing 224 * uncached mapping if we can't. 225 */ 226 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 227 nvbo->force_coherent = true; 228 } 229 230 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 231 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 232 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 233 kfree(nvbo); 234 return -EINVAL; 235 } 236 237 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 238 } else 239 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 240 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 241 nvbo->comp = (tile_flags & 0x00030000) >> 16; 242 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 243 kfree(nvbo); 244 return -EINVAL; 245 } 246 } else { 247 nvbo->zeta = (tile_flags & 0x00000007); 248 } 249 nvbo->mode = tile_mode; 250 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 251 252 /* Determine the desirable target GPU page size for the buffer. */ 253 for (i = 0; i < vmm->page_nr; i++) { 254 /* Because we cannot currently allow VMM maps to fail 255 * during buffer migration, we need to determine page 256 * size for the buffer up-front, and pre-allocate its 257 * page tables. 258 * 259 * Skip page sizes that can't support needed domains. 260 */ 261 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 262 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram) 263 continue; 264 if ((flags & TTM_PL_FLAG_TT) && 265 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 266 continue; 267 268 /* Select this page size if it's the first that supports 269 * the potential memory domains, or when it's compatible 270 * with the requested compression settings. 271 */ 272 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 273 pi = i; 274 275 /* Stop once the buffer is larger than the current page size. */ 276 if (size >= 1ULL << vmm->page[i].shift) 277 break; 278 } 279 280 if (WARN_ON(pi < 0)) 281 return -EINVAL; 282 283 /* Disable compression if suitable settings couldn't be found. */ 284 if (nvbo->comp && !vmm->page[pi].comp) { 285 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 286 nvbo->kind = mmu->kind[nvbo->kind]; 287 nvbo->comp = 0; 288 } 289 nvbo->page = vmm->page[pi].shift; 290 291 nouveau_bo_fixup_align(nvbo, flags, &align, &size); 292 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; 293 nouveau_bo_placement_set(nvbo, flags, 0); 294 295 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, 296 sizeof(struct nouveau_bo)); 297 298 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, 299 type, &nvbo->placement, 300 align >> PAGE_SHIFT, false, acc_size, sg, 301 robj, nouveau_bo_del_ttm); 302 303 if (ret) { 304 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 305 return ret; 306 } 307 308 *pnvbo = nvbo; 309 return 0; 310 } 311 312 static void 313 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) 314 { 315 *n = 0; 316 317 if (type & TTM_PL_FLAG_VRAM) 318 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; 319 if (type & TTM_PL_FLAG_TT) 320 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; 321 if (type & TTM_PL_FLAG_SYSTEM) 322 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; 323 } 324 325 static void 326 set_placement_range(struct nouveau_bo *nvbo, uint32_t type) 327 { 328 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 329 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; 330 unsigned i, fpfn, lpfn; 331 332 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 333 nvbo->mode && (type & TTM_PL_FLAG_VRAM) && 334 nvbo->bo.mem.num_pages < vram_pages / 4) { 335 /* 336 * Make sure that the color and depth buffers are handled 337 * by independent memory controller units. Up to a 9x 338 * speed up when alpha-blending and depth-test are enabled 339 * at the same time. 340 */ 341 if (nvbo->zeta) { 342 fpfn = vram_pages / 2; 343 lpfn = ~0; 344 } else { 345 fpfn = 0; 346 lpfn = vram_pages / 2; 347 } 348 for (i = 0; i < nvbo->placement.num_placement; ++i) { 349 nvbo->placements[i].fpfn = fpfn; 350 nvbo->placements[i].lpfn = lpfn; 351 } 352 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 353 nvbo->busy_placements[i].fpfn = fpfn; 354 nvbo->busy_placements[i].lpfn = lpfn; 355 } 356 } 357 } 358 359 void 360 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) 361 { 362 struct ttm_placement *pl = &nvbo->placement; 363 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : 364 TTM_PL_MASK_CACHING) | 365 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); 366 367 pl->placement = nvbo->placements; 368 set_placement_list(nvbo->placements, &pl->num_placement, 369 type, flags); 370 371 pl->busy_placement = nvbo->busy_placements; 372 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 373 type | busy, flags); 374 375 set_placement_range(nvbo, type); 376 } 377 378 int 379 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) 380 { 381 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 382 struct ttm_buffer_object *bo = &nvbo->bo; 383 bool force = false, evict = false; 384 int ret; 385 386 ret = ttm_bo_reserve(bo, false, false, NULL); 387 if (ret) 388 return ret; 389 390 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 391 memtype == TTM_PL_FLAG_VRAM && contig) { 392 if (!nvbo->contig) { 393 nvbo->contig = true; 394 force = true; 395 evict = true; 396 } 397 } 398 399 if (nvbo->pin_refcnt) { 400 if (!(memtype & (1 << bo->mem.mem_type)) || evict) { 401 NV_ERROR(drm, "bo %p pinned elsewhere: " 402 "0x%08x vs 0x%08x\n", bo, 403 1 << bo->mem.mem_type, memtype); 404 ret = -EBUSY; 405 } 406 nvbo->pin_refcnt++; 407 goto out; 408 } 409 410 if (evict) { 411 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); 412 ret = nouveau_bo_validate(nvbo, false, false); 413 if (ret) 414 goto out; 415 } 416 417 nvbo->pin_refcnt++; 418 nouveau_bo_placement_set(nvbo, memtype, 0); 419 420 /* drop pin_refcnt temporarily, so we don't trip the assertion 421 * in nouveau_bo_move() that makes sure we're not trying to 422 * move a pinned buffer 423 */ 424 nvbo->pin_refcnt--; 425 ret = nouveau_bo_validate(nvbo, false, false); 426 if (ret) 427 goto out; 428 nvbo->pin_refcnt++; 429 430 switch (bo->mem.mem_type) { 431 case TTM_PL_VRAM: 432 drm->gem.vram_available -= bo->mem.size; 433 break; 434 case TTM_PL_TT: 435 drm->gem.gart_available -= bo->mem.size; 436 break; 437 default: 438 break; 439 } 440 441 out: 442 if (force && ret) 443 nvbo->contig = false; 444 ttm_bo_unreserve(bo); 445 return ret; 446 } 447 448 int 449 nouveau_bo_unpin(struct nouveau_bo *nvbo) 450 { 451 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 452 struct ttm_buffer_object *bo = &nvbo->bo; 453 int ret, ref; 454 455 ret = ttm_bo_reserve(bo, false, false, NULL); 456 if (ret) 457 return ret; 458 459 ref = --nvbo->pin_refcnt; 460 WARN_ON_ONCE(ref < 0); 461 if (ref) 462 goto out; 463 464 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); 465 466 ret = nouveau_bo_validate(nvbo, false, false); 467 if (ret == 0) { 468 switch (bo->mem.mem_type) { 469 case TTM_PL_VRAM: 470 drm->gem.vram_available += bo->mem.size; 471 break; 472 case TTM_PL_TT: 473 drm->gem.gart_available += bo->mem.size; 474 break; 475 default: 476 break; 477 } 478 } 479 480 out: 481 ttm_bo_unreserve(bo); 482 return ret; 483 } 484 485 int 486 nouveau_bo_map(struct nouveau_bo *nvbo) 487 { 488 int ret; 489 490 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 491 if (ret) 492 return ret; 493 494 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 495 496 ttm_bo_unreserve(&nvbo->bo); 497 return ret; 498 } 499 500 void 501 nouveau_bo_unmap(struct nouveau_bo *nvbo) 502 { 503 if (!nvbo) 504 return; 505 506 ttm_bo_kunmap(&nvbo->kmap); 507 } 508 509 void 510 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 511 { 512 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 513 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 514 int i; 515 516 if (!ttm_dma) 517 return; 518 519 /* Don't waste time looping if the object is coherent */ 520 if (nvbo->force_coherent) 521 return; 522 523 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 524 dma_sync_single_for_device(drm->dev->dev, 525 ttm_dma->dma_address[i], 526 PAGE_SIZE, DMA_TO_DEVICE); 527 } 528 529 void 530 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 531 { 532 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 533 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 534 int i; 535 536 if (!ttm_dma) 537 return; 538 539 /* Don't waste time looping if the object is coherent */ 540 if (nvbo->force_coherent) 541 return; 542 543 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 544 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 545 PAGE_SIZE, DMA_FROM_DEVICE); 546 } 547 548 int 549 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 550 bool no_wait_gpu) 551 { 552 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 553 int ret; 554 555 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 556 if (ret) 557 return ret; 558 559 nouveau_bo_sync_for_device(nvbo); 560 561 return 0; 562 } 563 564 void 565 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 566 { 567 bool is_iomem; 568 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 569 570 mem += index; 571 572 if (is_iomem) 573 iowrite16_native(val, (void __force __iomem *)mem); 574 else 575 *mem = val; 576 } 577 578 u32 579 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 580 { 581 bool is_iomem; 582 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 583 584 mem += index; 585 586 if (is_iomem) 587 return ioread32_native((void __force __iomem *)mem); 588 else 589 return *mem; 590 } 591 592 void 593 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 594 { 595 bool is_iomem; 596 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 597 598 mem += index; 599 600 if (is_iomem) 601 iowrite32_native(val, (void __force __iomem *)mem); 602 else 603 *mem = val; 604 } 605 606 static struct ttm_tt * 607 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 608 { 609 #if IS_ENABLED(CONFIG_AGP) 610 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 611 612 if (drm->agp.bridge) { 613 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 614 } 615 #endif 616 617 return nouveau_sgdma_create_ttm(bo, page_flags); 618 } 619 620 static int 621 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 622 { 623 /* We'll do this from user space. */ 624 return 0; 625 } 626 627 static int 628 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 629 struct ttm_mem_type_manager *man) 630 { 631 struct nouveau_drm *drm = nouveau_bdev(bdev); 632 struct nvif_mmu *mmu = &drm->client.mmu; 633 634 switch (type) { 635 case TTM_PL_SYSTEM: 636 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 637 man->available_caching = TTM_PL_MASK_CACHING; 638 man->default_caching = TTM_PL_FLAG_CACHED; 639 break; 640 case TTM_PL_VRAM: 641 man->flags = TTM_MEMTYPE_FLAG_FIXED | 642 TTM_MEMTYPE_FLAG_MAPPABLE; 643 man->available_caching = TTM_PL_FLAG_UNCACHED | 644 TTM_PL_FLAG_WC; 645 man->default_caching = TTM_PL_FLAG_WC; 646 647 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 648 /* Some BARs do not support being ioremapped WC */ 649 const u8 type = mmu->type[drm->ttm.type_vram].type; 650 if (type & NVIF_MEM_UNCACHED) { 651 man->available_caching = TTM_PL_FLAG_UNCACHED; 652 man->default_caching = TTM_PL_FLAG_UNCACHED; 653 } 654 655 man->func = &nouveau_vram_manager; 656 man->io_reserve_fastpath = false; 657 man->use_io_reserve_lru = true; 658 } else { 659 man->func = &ttm_bo_manager_func; 660 } 661 break; 662 case TTM_PL_TT: 663 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) 664 man->func = &nouveau_gart_manager; 665 else 666 if (!drm->agp.bridge) 667 man->func = &nv04_gart_manager; 668 else 669 man->func = &ttm_bo_manager_func; 670 671 if (drm->agp.bridge) { 672 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 673 man->available_caching = TTM_PL_FLAG_UNCACHED | 674 TTM_PL_FLAG_WC; 675 man->default_caching = TTM_PL_FLAG_WC; 676 } else { 677 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | 678 TTM_MEMTYPE_FLAG_CMA; 679 man->available_caching = TTM_PL_MASK_CACHING; 680 man->default_caching = TTM_PL_FLAG_CACHED; 681 } 682 683 break; 684 default: 685 return -EINVAL; 686 } 687 return 0; 688 } 689 690 static void 691 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 692 { 693 struct nouveau_bo *nvbo = nouveau_bo(bo); 694 695 switch (bo->mem.mem_type) { 696 case TTM_PL_VRAM: 697 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 698 TTM_PL_FLAG_SYSTEM); 699 break; 700 default: 701 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); 702 break; 703 } 704 705 *pl = nvbo->placement; 706 } 707 708 709 static int 710 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) 711 { 712 int ret = RING_SPACE(chan, 2); 713 if (ret == 0) { 714 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 715 OUT_RING (chan, handle & 0x0000ffff); 716 FIRE_RING (chan); 717 } 718 return ret; 719 } 720 721 static int 722 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 723 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 724 { 725 struct nouveau_mem *mem = nouveau_mem(old_reg); 726 int ret = RING_SPACE(chan, 10); 727 if (ret == 0) { 728 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); 729 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 730 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 731 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 732 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 733 OUT_RING (chan, PAGE_SIZE); 734 OUT_RING (chan, PAGE_SIZE); 735 OUT_RING (chan, PAGE_SIZE); 736 OUT_RING (chan, new_reg->num_pages); 737 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); 738 } 739 return ret; 740 } 741 742 static int 743 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) 744 { 745 int ret = RING_SPACE(chan, 2); 746 if (ret == 0) { 747 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 748 OUT_RING (chan, handle); 749 } 750 return ret; 751 } 752 753 static int 754 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 755 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 756 { 757 struct nouveau_mem *mem = nouveau_mem(old_reg); 758 u64 src_offset = mem->vma[0].addr; 759 u64 dst_offset = mem->vma[1].addr; 760 u32 page_count = new_reg->num_pages; 761 int ret; 762 763 page_count = new_reg->num_pages; 764 while (page_count) { 765 int line_count = (page_count > 8191) ? 8191 : page_count; 766 767 ret = RING_SPACE(chan, 11); 768 if (ret) 769 return ret; 770 771 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); 772 OUT_RING (chan, upper_32_bits(src_offset)); 773 OUT_RING (chan, lower_32_bits(src_offset)); 774 OUT_RING (chan, upper_32_bits(dst_offset)); 775 OUT_RING (chan, lower_32_bits(dst_offset)); 776 OUT_RING (chan, PAGE_SIZE); 777 OUT_RING (chan, PAGE_SIZE); 778 OUT_RING (chan, PAGE_SIZE); 779 OUT_RING (chan, line_count); 780 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 781 OUT_RING (chan, 0x00000110); 782 783 page_count -= line_count; 784 src_offset += (PAGE_SIZE * line_count); 785 dst_offset += (PAGE_SIZE * line_count); 786 } 787 788 return 0; 789 } 790 791 static int 792 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 793 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 794 { 795 struct nouveau_mem *mem = nouveau_mem(old_reg); 796 u64 src_offset = mem->vma[0].addr; 797 u64 dst_offset = mem->vma[1].addr; 798 u32 page_count = new_reg->num_pages; 799 int ret; 800 801 page_count = new_reg->num_pages; 802 while (page_count) { 803 int line_count = (page_count > 2047) ? 2047 : page_count; 804 805 ret = RING_SPACE(chan, 12); 806 if (ret) 807 return ret; 808 809 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); 810 OUT_RING (chan, upper_32_bits(dst_offset)); 811 OUT_RING (chan, lower_32_bits(dst_offset)); 812 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); 813 OUT_RING (chan, upper_32_bits(src_offset)); 814 OUT_RING (chan, lower_32_bits(src_offset)); 815 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 816 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 817 OUT_RING (chan, PAGE_SIZE); /* line_length */ 818 OUT_RING (chan, line_count); 819 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 820 OUT_RING (chan, 0x00100110); 821 822 page_count -= line_count; 823 src_offset += (PAGE_SIZE * line_count); 824 dst_offset += (PAGE_SIZE * line_count); 825 } 826 827 return 0; 828 } 829 830 static int 831 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 832 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 833 { 834 struct nouveau_mem *mem = nouveau_mem(old_reg); 835 u64 src_offset = mem->vma[0].addr; 836 u64 dst_offset = mem->vma[1].addr; 837 u32 page_count = new_reg->num_pages; 838 int ret; 839 840 page_count = new_reg->num_pages; 841 while (page_count) { 842 int line_count = (page_count > 8191) ? 8191 : page_count; 843 844 ret = RING_SPACE(chan, 11); 845 if (ret) 846 return ret; 847 848 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 849 OUT_RING (chan, upper_32_bits(src_offset)); 850 OUT_RING (chan, lower_32_bits(src_offset)); 851 OUT_RING (chan, upper_32_bits(dst_offset)); 852 OUT_RING (chan, lower_32_bits(dst_offset)); 853 OUT_RING (chan, PAGE_SIZE); 854 OUT_RING (chan, PAGE_SIZE); 855 OUT_RING (chan, PAGE_SIZE); 856 OUT_RING (chan, line_count); 857 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); 858 OUT_RING (chan, 0x00000110); 859 860 page_count -= line_count; 861 src_offset += (PAGE_SIZE * line_count); 862 dst_offset += (PAGE_SIZE * line_count); 863 } 864 865 return 0; 866 } 867 868 static int 869 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 870 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 871 { 872 struct nouveau_mem *mem = nouveau_mem(old_reg); 873 int ret = RING_SPACE(chan, 7); 874 if (ret == 0) { 875 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); 876 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 877 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 878 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 879 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 880 OUT_RING (chan, 0x00000000 /* COPY */); 881 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 882 } 883 return ret; 884 } 885 886 static int 887 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 888 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 889 { 890 struct nouveau_mem *mem = nouveau_mem(old_reg); 891 int ret = RING_SPACE(chan, 7); 892 if (ret == 0) { 893 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); 894 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 895 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 896 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 897 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 898 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 899 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); 900 } 901 return ret; 902 } 903 904 static int 905 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) 906 { 907 int ret = RING_SPACE(chan, 6); 908 if (ret == 0) { 909 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 910 OUT_RING (chan, handle); 911 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); 912 OUT_RING (chan, chan->drm->ntfy.handle); 913 OUT_RING (chan, chan->vram.handle); 914 OUT_RING (chan, chan->vram.handle); 915 } 916 917 return ret; 918 } 919 920 static int 921 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 922 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 923 { 924 struct nouveau_mem *mem = nouveau_mem(old_reg); 925 u64 length = (new_reg->num_pages << PAGE_SHIFT); 926 u64 src_offset = mem->vma[0].addr; 927 u64 dst_offset = mem->vma[1].addr; 928 int src_tiled = !!mem->kind; 929 int dst_tiled = !!nouveau_mem(new_reg)->kind; 930 int ret; 931 932 while (length) { 933 u32 amount, stride, height; 934 935 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); 936 if (ret) 937 return ret; 938 939 amount = min(length, (u64)(4 * 1024 * 1024)); 940 stride = 16 * 4; 941 height = amount / stride; 942 943 if (src_tiled) { 944 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); 945 OUT_RING (chan, 0); 946 OUT_RING (chan, 0); 947 OUT_RING (chan, stride); 948 OUT_RING (chan, height); 949 OUT_RING (chan, 1); 950 OUT_RING (chan, 0); 951 OUT_RING (chan, 0); 952 } else { 953 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); 954 OUT_RING (chan, 1); 955 } 956 if (dst_tiled) { 957 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); 958 OUT_RING (chan, 0); 959 OUT_RING (chan, 0); 960 OUT_RING (chan, stride); 961 OUT_RING (chan, height); 962 OUT_RING (chan, 1); 963 OUT_RING (chan, 0); 964 OUT_RING (chan, 0); 965 } else { 966 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); 967 OUT_RING (chan, 1); 968 } 969 970 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); 971 OUT_RING (chan, upper_32_bits(src_offset)); 972 OUT_RING (chan, upper_32_bits(dst_offset)); 973 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 974 OUT_RING (chan, lower_32_bits(src_offset)); 975 OUT_RING (chan, lower_32_bits(dst_offset)); 976 OUT_RING (chan, stride); 977 OUT_RING (chan, stride); 978 OUT_RING (chan, stride); 979 OUT_RING (chan, height); 980 OUT_RING (chan, 0x00000101); 981 OUT_RING (chan, 0x00000000); 982 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 983 OUT_RING (chan, 0); 984 985 length -= amount; 986 src_offset += amount; 987 dst_offset += amount; 988 } 989 990 return 0; 991 } 992 993 static int 994 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) 995 { 996 int ret = RING_SPACE(chan, 4); 997 if (ret == 0) { 998 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 999 OUT_RING (chan, handle); 1000 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); 1001 OUT_RING (chan, chan->drm->ntfy.handle); 1002 } 1003 1004 return ret; 1005 } 1006 1007 static inline uint32_t 1008 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, 1009 struct nouveau_channel *chan, struct ttm_mem_reg *reg) 1010 { 1011 if (reg->mem_type == TTM_PL_TT) 1012 return NvDmaTT; 1013 return chan->vram.handle; 1014 } 1015 1016 static int 1017 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 1018 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 1019 { 1020 u32 src_offset = old_reg->start << PAGE_SHIFT; 1021 u32 dst_offset = new_reg->start << PAGE_SHIFT; 1022 u32 page_count = new_reg->num_pages; 1023 int ret; 1024 1025 ret = RING_SPACE(chan, 3); 1026 if (ret) 1027 return ret; 1028 1029 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); 1030 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); 1031 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); 1032 1033 page_count = new_reg->num_pages; 1034 while (page_count) { 1035 int line_count = (page_count > 2047) ? 2047 : page_count; 1036 1037 ret = RING_SPACE(chan, 11); 1038 if (ret) 1039 return ret; 1040 1041 BEGIN_NV04(chan, NvSubCopy, 1042 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 1043 OUT_RING (chan, src_offset); 1044 OUT_RING (chan, dst_offset); 1045 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 1046 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 1047 OUT_RING (chan, PAGE_SIZE); /* line_length */ 1048 OUT_RING (chan, line_count); 1049 OUT_RING (chan, 0x00000101); 1050 OUT_RING (chan, 0x00000000); 1051 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 1052 OUT_RING (chan, 0); 1053 1054 page_count -= line_count; 1055 src_offset += (PAGE_SIZE * line_count); 1056 dst_offset += (PAGE_SIZE * line_count); 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int 1063 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 1064 struct ttm_mem_reg *reg) 1065 { 1066 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 1067 struct nouveau_mem *new_mem = nouveau_mem(reg); 1068 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 1069 int ret; 1070 1071 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 1072 old_mem->mem.size, &old_mem->vma[0]); 1073 if (ret) 1074 return ret; 1075 1076 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 1077 new_mem->mem.size, &old_mem->vma[1]); 1078 if (ret) 1079 goto done; 1080 1081 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 1082 if (ret) 1083 goto done; 1084 1085 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 1086 done: 1087 if (ret) { 1088 nvif_vmm_put(vmm, &old_mem->vma[1]); 1089 nvif_vmm_put(vmm, &old_mem->vma[0]); 1090 } 1091 return 0; 1092 } 1093 1094 static int 1095 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, 1096 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1097 { 1098 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1099 struct nouveau_channel *chan = drm->ttm.chan; 1100 struct nouveau_cli *cli = (void *)chan->user.client; 1101 struct nouveau_fence *fence; 1102 int ret; 1103 1104 /* create temporary vmas for the transfer and attach them to the 1105 * old nvkm_mem node, these will get cleaned up after ttm has 1106 * destroyed the ttm_mem_reg 1107 */ 1108 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 1109 ret = nouveau_bo_move_prep(drm, bo, new_reg); 1110 if (ret) 1111 return ret; 1112 } 1113 1114 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 1115 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); 1116 if (ret == 0) { 1117 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 1118 if (ret == 0) { 1119 ret = nouveau_fence_new(chan, false, &fence); 1120 if (ret == 0) { 1121 ret = ttm_bo_move_accel_cleanup(bo, 1122 &fence->base, 1123 evict, 1124 new_reg); 1125 nouveau_fence_unref(&fence); 1126 } 1127 } 1128 } 1129 mutex_unlock(&cli->mutex); 1130 return ret; 1131 } 1132 1133 void 1134 nouveau_bo_move_init(struct nouveau_drm *drm) 1135 { 1136 static const struct { 1137 const char *name; 1138 int engine; 1139 s32 oclass; 1140 int (*exec)(struct nouveau_channel *, 1141 struct ttm_buffer_object *, 1142 struct ttm_mem_reg *, struct ttm_mem_reg *); 1143 int (*init)(struct nouveau_channel *, u32 handle); 1144 } _methods[] = { 1145 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, 1146 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1147 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 1148 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1149 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 1150 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1151 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1152 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1153 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1154 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1155 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1156 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1157 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 1158 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 1159 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 1160 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 1161 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 1162 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 1163 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 1164 {}, 1165 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, 1166 }, *mthd = _methods; 1167 const char *name = "CPU"; 1168 int ret; 1169 1170 do { 1171 struct nouveau_channel *chan; 1172 1173 if (mthd->engine) 1174 chan = drm->cechan; 1175 else 1176 chan = drm->channel; 1177 if (chan == NULL) 1178 continue; 1179 1180 ret = nvif_object_init(&chan->user, 1181 mthd->oclass | (mthd->engine << 16), 1182 mthd->oclass, NULL, 0, 1183 &drm->ttm.copy); 1184 if (ret == 0) { 1185 ret = mthd->init(chan, drm->ttm.copy.handle); 1186 if (ret) { 1187 nvif_object_fini(&drm->ttm.copy); 1188 continue; 1189 } 1190 1191 drm->ttm.move = mthd->exec; 1192 drm->ttm.chan = chan; 1193 name = mthd->name; 1194 break; 1195 } 1196 } while ((++mthd)->exec); 1197 1198 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 1199 } 1200 1201 static int 1202 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 1203 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1204 { 1205 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1206 struct ttm_place placement_memtype = { 1207 .fpfn = 0, 1208 .lpfn = 0, 1209 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1210 }; 1211 struct ttm_placement placement; 1212 struct ttm_mem_reg tmp_reg; 1213 int ret; 1214 1215 placement.num_placement = placement.num_busy_placement = 1; 1216 placement.placement = placement.busy_placement = &placement_memtype; 1217 1218 tmp_reg = *new_reg; 1219 tmp_reg.mm_node = NULL; 1220 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1221 if (ret) 1222 return ret; 1223 1224 ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx); 1225 if (ret) 1226 goto out; 1227 1228 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); 1229 if (ret) 1230 goto out; 1231 1232 ret = ttm_bo_move_ttm(bo, &ctx, new_reg); 1233 out: 1234 ttm_bo_mem_put(bo, &tmp_reg); 1235 return ret; 1236 } 1237 1238 static int 1239 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 1240 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1241 { 1242 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1243 struct ttm_place placement_memtype = { 1244 .fpfn = 0, 1245 .lpfn = 0, 1246 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1247 }; 1248 struct ttm_placement placement; 1249 struct ttm_mem_reg tmp_reg; 1250 int ret; 1251 1252 placement.num_placement = placement.num_busy_placement = 1; 1253 placement.placement = placement.busy_placement = &placement_memtype; 1254 1255 tmp_reg = *new_reg; 1256 tmp_reg.mm_node = NULL; 1257 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1258 if (ret) 1259 return ret; 1260 1261 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg); 1262 if (ret) 1263 goto out; 1264 1265 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); 1266 if (ret) 1267 goto out; 1268 1269 out: 1270 ttm_bo_mem_put(bo, &tmp_reg); 1271 return ret; 1272 } 1273 1274 static void 1275 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, 1276 struct ttm_mem_reg *new_reg) 1277 { 1278 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 1279 struct nouveau_bo *nvbo = nouveau_bo(bo); 1280 struct nouveau_vma *vma; 1281 1282 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 1283 if (bo->destroy != nouveau_bo_del_ttm) 1284 return; 1285 1286 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 1287 mem->mem.page == nvbo->page) { 1288 list_for_each_entry(vma, &nvbo->vma_list, head) { 1289 nouveau_vma_map(vma, mem); 1290 } 1291 } else { 1292 list_for_each_entry(vma, &nvbo->vma_list, head) { 1293 WARN_ON(ttm_bo_wait(bo, false, false)); 1294 nouveau_vma_unmap(vma); 1295 } 1296 } 1297 } 1298 1299 static int 1300 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg, 1301 struct nouveau_drm_tile **new_tile) 1302 { 1303 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1304 struct drm_device *dev = drm->dev; 1305 struct nouveau_bo *nvbo = nouveau_bo(bo); 1306 u64 offset = new_reg->start << PAGE_SHIFT; 1307 1308 *new_tile = NULL; 1309 if (new_reg->mem_type != TTM_PL_VRAM) 1310 return 0; 1311 1312 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 1313 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, 1314 nvbo->mode, nvbo->zeta); 1315 } 1316 1317 return 0; 1318 } 1319 1320 static void 1321 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 1322 struct nouveau_drm_tile *new_tile, 1323 struct nouveau_drm_tile **old_tile) 1324 { 1325 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1326 struct drm_device *dev = drm->dev; 1327 struct dma_fence *fence = reservation_object_get_excl(bo->base.resv); 1328 1329 nv10_bo_put_tile_region(dev, *old_tile, fence); 1330 *old_tile = new_tile; 1331 } 1332 1333 static int 1334 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 1335 struct ttm_operation_ctx *ctx, 1336 struct ttm_mem_reg *new_reg) 1337 { 1338 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1339 struct nouveau_bo *nvbo = nouveau_bo(bo); 1340 struct ttm_mem_reg *old_reg = &bo->mem; 1341 struct nouveau_drm_tile *new_tile = NULL; 1342 int ret = 0; 1343 1344 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1345 if (ret) 1346 return ret; 1347 1348 if (nvbo->pin_refcnt) 1349 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 1350 1351 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1352 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 1353 if (ret) 1354 return ret; 1355 } 1356 1357 /* Fake bo copy. */ 1358 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 1359 BUG_ON(bo->mem.mm_node != NULL); 1360 bo->mem = *new_reg; 1361 new_reg->mm_node = NULL; 1362 goto out; 1363 } 1364 1365 /* Hardware assisted copy. */ 1366 if (drm->ttm.move) { 1367 if (new_reg->mem_type == TTM_PL_SYSTEM) 1368 ret = nouveau_bo_move_flipd(bo, evict, 1369 ctx->interruptible, 1370 ctx->no_wait_gpu, new_reg); 1371 else if (old_reg->mem_type == TTM_PL_SYSTEM) 1372 ret = nouveau_bo_move_flips(bo, evict, 1373 ctx->interruptible, 1374 ctx->no_wait_gpu, new_reg); 1375 else 1376 ret = nouveau_bo_move_m2mf(bo, evict, 1377 ctx->interruptible, 1378 ctx->no_wait_gpu, new_reg); 1379 if (!ret) 1380 goto out; 1381 } 1382 1383 /* Fallback to software copy. */ 1384 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1385 if (ret == 0) 1386 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1387 1388 out: 1389 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1390 if (ret) 1391 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1392 else 1393 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1394 } 1395 1396 return ret; 1397 } 1398 1399 static int 1400 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 1401 { 1402 struct nouveau_bo *nvbo = nouveau_bo(bo); 1403 1404 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node, 1405 filp->private_data); 1406 } 1407 1408 static int 1409 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1410 { 1411 struct ttm_mem_type_manager *man = &bdev->man[reg->mem_type]; 1412 struct nouveau_drm *drm = nouveau_bdev(bdev); 1413 struct nvkm_device *device = nvxx_device(&drm->client.device); 1414 struct nouveau_mem *mem = nouveau_mem(reg); 1415 1416 reg->bus.addr = NULL; 1417 reg->bus.offset = 0; 1418 reg->bus.size = reg->num_pages << PAGE_SHIFT; 1419 reg->bus.base = 0; 1420 reg->bus.is_iomem = false; 1421 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 1422 return -EINVAL; 1423 switch (reg->mem_type) { 1424 case TTM_PL_SYSTEM: 1425 /* System memory */ 1426 return 0; 1427 case TTM_PL_TT: 1428 #if IS_ENABLED(CONFIG_AGP) 1429 if (drm->agp.bridge) { 1430 reg->bus.offset = reg->start << PAGE_SHIFT; 1431 reg->bus.base = drm->agp.base; 1432 reg->bus.is_iomem = !drm->agp.cma; 1433 } 1434 #endif 1435 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) 1436 /* untiled */ 1437 break; 1438 /* fall through - tiled memory */ 1439 case TTM_PL_VRAM: 1440 reg->bus.offset = reg->start << PAGE_SHIFT; 1441 reg->bus.base = device->func->resource_addr(device, 1); 1442 reg->bus.is_iomem = true; 1443 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1444 union { 1445 struct nv50_mem_map_v0 nv50; 1446 struct gf100_mem_map_v0 gf100; 1447 } args; 1448 u64 handle, length; 1449 u32 argc = 0; 1450 int ret; 1451 1452 switch (mem->mem.object.oclass) { 1453 case NVIF_CLASS_MEM_NV50: 1454 args.nv50.version = 0; 1455 args.nv50.ro = 0; 1456 args.nv50.kind = mem->kind; 1457 args.nv50.comp = mem->comp; 1458 argc = sizeof(args.nv50); 1459 break; 1460 case NVIF_CLASS_MEM_GF100: 1461 args.gf100.version = 0; 1462 args.gf100.ro = 0; 1463 args.gf100.kind = mem->kind; 1464 argc = sizeof(args.gf100); 1465 break; 1466 default: 1467 WARN_ON(1); 1468 break; 1469 } 1470 1471 ret = nvif_object_map_handle(&mem->mem.object, 1472 &args, argc, 1473 &handle, &length); 1474 if (ret != 1) 1475 return ret ? ret : -EINVAL; 1476 1477 reg->bus.base = 0; 1478 reg->bus.offset = handle; 1479 } 1480 break; 1481 default: 1482 return -EINVAL; 1483 } 1484 return 0; 1485 } 1486 1487 static void 1488 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1489 { 1490 struct nouveau_drm *drm = nouveau_bdev(bdev); 1491 struct nouveau_mem *mem = nouveau_mem(reg); 1492 1493 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1494 switch (reg->mem_type) { 1495 case TTM_PL_TT: 1496 if (mem->kind) 1497 nvif_object_unmap_handle(&mem->mem.object); 1498 break; 1499 case TTM_PL_VRAM: 1500 nvif_object_unmap_handle(&mem->mem.object); 1501 break; 1502 default: 1503 break; 1504 } 1505 } 1506 } 1507 1508 static int 1509 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1510 { 1511 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1512 struct nouveau_bo *nvbo = nouveau_bo(bo); 1513 struct nvkm_device *device = nvxx_device(&drm->client.device); 1514 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1515 int i, ret; 1516 1517 /* as long as the bo isn't in vram, and isn't tiled, we've got 1518 * nothing to do here. 1519 */ 1520 if (bo->mem.mem_type != TTM_PL_VRAM) { 1521 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1522 !nvbo->kind) 1523 return 0; 1524 1525 if (bo->mem.mem_type == TTM_PL_SYSTEM) { 1526 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); 1527 1528 ret = nouveau_bo_validate(nvbo, false, false); 1529 if (ret) 1530 return ret; 1531 } 1532 return 0; 1533 } 1534 1535 /* make sure bo is in mappable vram */ 1536 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1537 bo->mem.start + bo->mem.num_pages < mappable) 1538 return 0; 1539 1540 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1541 nvbo->placements[i].fpfn = 0; 1542 nvbo->placements[i].lpfn = mappable; 1543 } 1544 1545 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1546 nvbo->busy_placements[i].fpfn = 0; 1547 nvbo->busy_placements[i].lpfn = mappable; 1548 } 1549 1550 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); 1551 return nouveau_bo_validate(nvbo, false, false); 1552 } 1553 1554 static int 1555 nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1556 { 1557 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1558 struct nouveau_drm *drm; 1559 struct device *dev; 1560 unsigned i; 1561 int r; 1562 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1563 1564 if (ttm->state != tt_unpopulated) 1565 return 0; 1566 1567 if (slave && ttm->sg) { 1568 /* make userspace faulting work */ 1569 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1570 ttm_dma->dma_address, ttm->num_pages); 1571 ttm->state = tt_unbound; 1572 return 0; 1573 } 1574 1575 drm = nouveau_bdev(ttm->bdev); 1576 dev = drm->dev->dev; 1577 1578 #if IS_ENABLED(CONFIG_AGP) 1579 if (drm->agp.bridge) { 1580 return ttm_agp_tt_populate(ttm, ctx); 1581 } 1582 #endif 1583 1584 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1585 if (swiotlb_nr_tbl()) { 1586 return ttm_dma_populate((void *)ttm, dev, ctx); 1587 } 1588 #endif 1589 1590 r = ttm_pool_populate(ttm, ctx); 1591 if (r) { 1592 return r; 1593 } 1594 1595 for (i = 0; i < ttm->num_pages; i++) { 1596 dma_addr_t addr; 1597 1598 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE, 1599 DMA_BIDIRECTIONAL); 1600 1601 if (dma_mapping_error(dev, addr)) { 1602 while (i--) { 1603 dma_unmap_page(dev, ttm_dma->dma_address[i], 1604 PAGE_SIZE, DMA_BIDIRECTIONAL); 1605 ttm_dma->dma_address[i] = 0; 1606 } 1607 ttm_pool_unpopulate(ttm); 1608 return -EFAULT; 1609 } 1610 1611 ttm_dma->dma_address[i] = addr; 1612 } 1613 return 0; 1614 } 1615 1616 static void 1617 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) 1618 { 1619 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1620 struct nouveau_drm *drm; 1621 struct device *dev; 1622 unsigned i; 1623 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1624 1625 if (slave) 1626 return; 1627 1628 drm = nouveau_bdev(ttm->bdev); 1629 dev = drm->dev->dev; 1630 1631 #if IS_ENABLED(CONFIG_AGP) 1632 if (drm->agp.bridge) { 1633 ttm_agp_tt_unpopulate(ttm); 1634 return; 1635 } 1636 #endif 1637 1638 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1639 if (swiotlb_nr_tbl()) { 1640 ttm_dma_unpopulate((void *)ttm, dev); 1641 return; 1642 } 1643 #endif 1644 1645 for (i = 0; i < ttm->num_pages; i++) { 1646 if (ttm_dma->dma_address[i]) { 1647 dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE, 1648 DMA_BIDIRECTIONAL); 1649 } 1650 } 1651 1652 ttm_pool_unpopulate(ttm); 1653 } 1654 1655 void 1656 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1657 { 1658 struct reservation_object *resv = nvbo->bo.base.resv; 1659 1660 if (exclusive) 1661 reservation_object_add_excl_fence(resv, &fence->base); 1662 else if (fence) 1663 reservation_object_add_shared_fence(resv, &fence->base); 1664 } 1665 1666 struct ttm_bo_driver nouveau_bo_driver = { 1667 .ttm_tt_create = &nouveau_ttm_tt_create, 1668 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1669 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1670 .invalidate_caches = nouveau_bo_invalidate_caches, 1671 .init_mem_type = nouveau_bo_init_mem_type, 1672 .eviction_valuable = ttm_bo_eviction_valuable, 1673 .evict_flags = nouveau_bo_evict_flags, 1674 .move_notify = nouveau_bo_move_ntfy, 1675 .move = nouveau_bo_move, 1676 .verify_access = nouveau_bo_verify_access, 1677 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, 1678 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1679 .io_mem_free = &nouveau_ttm_io_mem_free, 1680 }; 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