1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 #include <linux/swiotlb.h> 32 33 #include "nouveau_drv.h" 34 #include "nouveau_dma.h" 35 #include "nouveau_fence.h" 36 37 #include "nouveau_bo.h" 38 #include "nouveau_ttm.h" 39 #include "nouveau_gem.h" 40 #include "nouveau_mem.h" 41 #include "nouveau_vmm.h" 42 43 #include <nvif/class.h> 44 #include <nvif/if500b.h> 45 #include <nvif/if900b.h> 46 47 /* 48 * NV10-NV40 tiling helpers 49 */ 50 51 static void 52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 53 u32 addr, u32 size, u32 pitch, u32 flags) 54 { 55 struct nouveau_drm *drm = nouveau_drm(dev); 56 int i = reg - drm->tile.reg; 57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 58 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 59 60 nouveau_fence_unref(®->fence); 61 62 if (tile->pitch) 63 nvkm_fb_tile_fini(fb, i, tile); 64 65 if (pitch) 66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 67 68 nvkm_fb_tile_prog(fb, i, tile); 69 } 70 71 static struct nouveau_drm_tile * 72 nv10_bo_get_tile_region(struct drm_device *dev, int i) 73 { 74 struct nouveau_drm *drm = nouveau_drm(dev); 75 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 76 77 spin_lock(&drm->tile.lock); 78 79 if (!tile->used && 80 (!tile->fence || nouveau_fence_done(tile->fence))) 81 tile->used = true; 82 else 83 tile = NULL; 84 85 spin_unlock(&drm->tile.lock); 86 return tile; 87 } 88 89 static void 90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 91 struct dma_fence *fence) 92 { 93 struct nouveau_drm *drm = nouveau_drm(dev); 94 95 if (tile) { 96 spin_lock(&drm->tile.lock); 97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 98 tile->used = false; 99 spin_unlock(&drm->tile.lock); 100 } 101 } 102 103 static struct nouveau_drm_tile * 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 105 u32 size, u32 pitch, u32 zeta) 106 { 107 struct nouveau_drm *drm = nouveau_drm(dev); 108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 109 struct nouveau_drm_tile *tile, *found = NULL; 110 int i; 111 112 for (i = 0; i < fb->tile.regions; i++) { 113 tile = nv10_bo_get_tile_region(dev, i); 114 115 if (pitch && !found) { 116 found = tile; 117 continue; 118 119 } else if (tile && fb->tile.region[i].pitch) { 120 /* Kill an unused tile region. */ 121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 122 } 123 124 nv10_bo_put_tile_region(dev, tile, NULL); 125 } 126 127 if (found) 128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 129 return found; 130 } 131 132 static void 133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 134 { 135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 136 struct drm_device *dev = drm->dev; 137 struct nouveau_bo *nvbo = nouveau_bo(bo); 138 139 WARN_ON(nvbo->pin_refcnt > 0); 140 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 141 142 /* 143 * If nouveau_bo_new() allocated this buffer, the GEM object was never 144 * initialized, so don't attempt to release it. 145 */ 146 if (bo->base.dev) 147 drm_gem_object_release(&bo->base); 148 149 kfree(nvbo); 150 } 151 152 static inline u64 153 roundup_64(u64 x, u32 y) 154 { 155 x += y - 1; 156 do_div(x, y); 157 return x * y; 158 } 159 160 static void 161 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, 162 int *align, u64 *size) 163 { 164 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 165 struct nvif_device *device = &drm->client.device; 166 167 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 168 if (nvbo->mode) { 169 if (device->info.chipset >= 0x40) { 170 *align = 65536; 171 *size = roundup_64(*size, 64 * nvbo->mode); 172 173 } else if (device->info.chipset >= 0x30) { 174 *align = 32768; 175 *size = roundup_64(*size, 64 * nvbo->mode); 176 177 } else if (device->info.chipset >= 0x20) { 178 *align = 16384; 179 *size = roundup_64(*size, 64 * nvbo->mode); 180 181 } else if (device->info.chipset >= 0x10) { 182 *align = 16384; 183 *size = roundup_64(*size, 32 * nvbo->mode); 184 } 185 } 186 } else { 187 *size = roundup_64(*size, (1 << nvbo->page)); 188 *align = max((1 << nvbo->page), *align); 189 } 190 191 *size = roundup_64(*size, PAGE_SIZE); 192 } 193 194 struct nouveau_bo * 195 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags, 196 u32 tile_mode, u32 tile_flags) 197 { 198 struct nouveau_drm *drm = cli->drm; 199 struct nouveau_bo *nvbo; 200 struct nvif_mmu *mmu = &cli->mmu; 201 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm; 202 int i, pi = -1; 203 204 if (!*size) { 205 NV_WARN(drm, "skipped size %016llx\n", *size); 206 return ERR_PTR(-EINVAL); 207 } 208 209 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 210 if (!nvbo) 211 return ERR_PTR(-ENOMEM); 212 INIT_LIST_HEAD(&nvbo->head); 213 INIT_LIST_HEAD(&nvbo->entry); 214 INIT_LIST_HEAD(&nvbo->vma_list); 215 nvbo->bo.bdev = &drm->ttm.bdev; 216 217 /* This is confusing, and doesn't actually mean we want an uncached 218 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 219 * into in nouveau_gem_new(). 220 */ 221 if (flags & TTM_PL_FLAG_UNCACHED) { 222 /* Determine if we can get a cache-coherent map, forcing 223 * uncached mapping if we can't. 224 */ 225 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 226 nvbo->force_coherent = true; 227 } 228 229 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 230 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 231 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 232 kfree(nvbo); 233 return ERR_PTR(-EINVAL); 234 } 235 236 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 237 } else 238 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 239 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 240 nvbo->comp = (tile_flags & 0x00030000) >> 16; 241 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 242 kfree(nvbo); 243 return ERR_PTR(-EINVAL); 244 } 245 } else { 246 nvbo->zeta = (tile_flags & 0x00000007); 247 } 248 nvbo->mode = tile_mode; 249 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 250 251 /* Determine the desirable target GPU page size for the buffer. */ 252 for (i = 0; i < vmm->page_nr; i++) { 253 /* Because we cannot currently allow VMM maps to fail 254 * during buffer migration, we need to determine page 255 * size for the buffer up-front, and pre-allocate its 256 * page tables. 257 * 258 * Skip page sizes that can't support needed domains. 259 */ 260 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 261 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram) 262 continue; 263 if ((flags & TTM_PL_FLAG_TT) && 264 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 265 continue; 266 267 /* Select this page size if it's the first that supports 268 * the potential memory domains, or when it's compatible 269 * with the requested compression settings. 270 */ 271 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 272 pi = i; 273 274 /* Stop once the buffer is larger than the current page size. */ 275 if (*size >= 1ULL << vmm->page[i].shift) 276 break; 277 } 278 279 if (WARN_ON(pi < 0)) 280 return ERR_PTR(-EINVAL); 281 282 /* Disable compression if suitable settings couldn't be found. */ 283 if (nvbo->comp && !vmm->page[pi].comp) { 284 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 285 nvbo->kind = mmu->kind[nvbo->kind]; 286 nvbo->comp = 0; 287 } 288 nvbo->page = vmm->page[pi].shift; 289 290 nouveau_bo_fixup_align(nvbo, flags, align, size); 291 292 return nvbo; 293 } 294 295 int 296 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 flags, 297 struct sg_table *sg, struct dma_resv *robj) 298 { 299 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device; 300 size_t acc_size; 301 int ret; 302 303 acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo)); 304 305 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; 306 nouveau_bo_placement_set(nvbo, flags, 0); 307 308 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type, 309 &nvbo->placement, align >> PAGE_SHIFT, false, 310 acc_size, sg, robj, nouveau_bo_del_ttm); 311 if (ret) { 312 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 313 return ret; 314 } 315 316 return 0; 317 } 318 319 int 320 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 321 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, 322 struct sg_table *sg, struct dma_resv *robj, 323 struct nouveau_bo **pnvbo) 324 { 325 struct nouveau_bo *nvbo; 326 int ret; 327 328 nvbo = nouveau_bo_alloc(cli, &size, &align, flags, tile_mode, 329 tile_flags); 330 if (IS_ERR(nvbo)) 331 return PTR_ERR(nvbo); 332 333 ret = nouveau_bo_init(nvbo, size, align, flags, sg, robj); 334 if (ret) 335 return ret; 336 337 *pnvbo = nvbo; 338 return 0; 339 } 340 341 static void 342 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) 343 { 344 *n = 0; 345 346 if (type & TTM_PL_FLAG_VRAM) 347 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; 348 if (type & TTM_PL_FLAG_TT) 349 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; 350 if (type & TTM_PL_FLAG_SYSTEM) 351 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; 352 } 353 354 static void 355 set_placement_range(struct nouveau_bo *nvbo, uint32_t type) 356 { 357 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 358 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; 359 unsigned i, fpfn, lpfn; 360 361 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 362 nvbo->mode && (type & TTM_PL_FLAG_VRAM) && 363 nvbo->bo.mem.num_pages < vram_pages / 4) { 364 /* 365 * Make sure that the color and depth buffers are handled 366 * by independent memory controller units. Up to a 9x 367 * speed up when alpha-blending and depth-test are enabled 368 * at the same time. 369 */ 370 if (nvbo->zeta) { 371 fpfn = vram_pages / 2; 372 lpfn = ~0; 373 } else { 374 fpfn = 0; 375 lpfn = vram_pages / 2; 376 } 377 for (i = 0; i < nvbo->placement.num_placement; ++i) { 378 nvbo->placements[i].fpfn = fpfn; 379 nvbo->placements[i].lpfn = lpfn; 380 } 381 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 382 nvbo->busy_placements[i].fpfn = fpfn; 383 nvbo->busy_placements[i].lpfn = lpfn; 384 } 385 } 386 } 387 388 void 389 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) 390 { 391 struct ttm_placement *pl = &nvbo->placement; 392 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : 393 TTM_PL_MASK_CACHING) | 394 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); 395 396 pl->placement = nvbo->placements; 397 set_placement_list(nvbo->placements, &pl->num_placement, 398 type, flags); 399 400 pl->busy_placement = nvbo->busy_placements; 401 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 402 type | busy, flags); 403 404 set_placement_range(nvbo, type); 405 } 406 407 int 408 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) 409 { 410 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 411 struct ttm_buffer_object *bo = &nvbo->bo; 412 bool force = false, evict = false; 413 int ret; 414 415 ret = ttm_bo_reserve(bo, false, false, NULL); 416 if (ret) 417 return ret; 418 419 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 420 memtype == TTM_PL_FLAG_VRAM && contig) { 421 if (!nvbo->contig) { 422 nvbo->contig = true; 423 force = true; 424 evict = true; 425 } 426 } 427 428 if (nvbo->pin_refcnt) { 429 if (!(memtype & (1 << bo->mem.mem_type)) || evict) { 430 NV_ERROR(drm, "bo %p pinned elsewhere: " 431 "0x%08x vs 0x%08x\n", bo, 432 1 << bo->mem.mem_type, memtype); 433 ret = -EBUSY; 434 } 435 nvbo->pin_refcnt++; 436 goto out; 437 } 438 439 if (evict) { 440 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); 441 ret = nouveau_bo_validate(nvbo, false, false); 442 if (ret) 443 goto out; 444 } 445 446 nvbo->pin_refcnt++; 447 nouveau_bo_placement_set(nvbo, memtype, 0); 448 449 /* drop pin_refcnt temporarily, so we don't trip the assertion 450 * in nouveau_bo_move() that makes sure we're not trying to 451 * move a pinned buffer 452 */ 453 nvbo->pin_refcnt--; 454 ret = nouveau_bo_validate(nvbo, false, false); 455 if (ret) 456 goto out; 457 nvbo->pin_refcnt++; 458 459 switch (bo->mem.mem_type) { 460 case TTM_PL_VRAM: 461 drm->gem.vram_available -= bo->mem.size; 462 break; 463 case TTM_PL_TT: 464 drm->gem.gart_available -= bo->mem.size; 465 break; 466 default: 467 break; 468 } 469 470 out: 471 if (force && ret) 472 nvbo->contig = false; 473 ttm_bo_unreserve(bo); 474 return ret; 475 } 476 477 int 478 nouveau_bo_unpin(struct nouveau_bo *nvbo) 479 { 480 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 481 struct ttm_buffer_object *bo = &nvbo->bo; 482 int ret, ref; 483 484 ret = ttm_bo_reserve(bo, false, false, NULL); 485 if (ret) 486 return ret; 487 488 ref = --nvbo->pin_refcnt; 489 WARN_ON_ONCE(ref < 0); 490 if (ref) 491 goto out; 492 493 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); 494 495 ret = nouveau_bo_validate(nvbo, false, false); 496 if (ret == 0) { 497 switch (bo->mem.mem_type) { 498 case TTM_PL_VRAM: 499 drm->gem.vram_available += bo->mem.size; 500 break; 501 case TTM_PL_TT: 502 drm->gem.gart_available += bo->mem.size; 503 break; 504 default: 505 break; 506 } 507 } 508 509 out: 510 ttm_bo_unreserve(bo); 511 return ret; 512 } 513 514 int 515 nouveau_bo_map(struct nouveau_bo *nvbo) 516 { 517 int ret; 518 519 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 520 if (ret) 521 return ret; 522 523 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 524 525 ttm_bo_unreserve(&nvbo->bo); 526 return ret; 527 } 528 529 void 530 nouveau_bo_unmap(struct nouveau_bo *nvbo) 531 { 532 if (!nvbo) 533 return; 534 535 ttm_bo_kunmap(&nvbo->kmap); 536 } 537 538 void 539 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 540 { 541 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 542 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 543 int i; 544 545 if (!ttm_dma) 546 return; 547 548 /* Don't waste time looping if the object is coherent */ 549 if (nvbo->force_coherent) 550 return; 551 552 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 553 dma_sync_single_for_device(drm->dev->dev, 554 ttm_dma->dma_address[i], 555 PAGE_SIZE, DMA_TO_DEVICE); 556 } 557 558 void 559 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 560 { 561 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 562 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 563 int i; 564 565 if (!ttm_dma) 566 return; 567 568 /* Don't waste time looping if the object is coherent */ 569 if (nvbo->force_coherent) 570 return; 571 572 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 573 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 574 PAGE_SIZE, DMA_FROM_DEVICE); 575 } 576 577 int 578 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 579 bool no_wait_gpu) 580 { 581 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 582 int ret; 583 584 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 585 if (ret) 586 return ret; 587 588 nouveau_bo_sync_for_device(nvbo); 589 590 return 0; 591 } 592 593 void 594 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 595 { 596 bool is_iomem; 597 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 598 599 mem += index; 600 601 if (is_iomem) 602 iowrite16_native(val, (void __force __iomem *)mem); 603 else 604 *mem = val; 605 } 606 607 u32 608 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 609 { 610 bool is_iomem; 611 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 612 613 mem += index; 614 615 if (is_iomem) 616 return ioread32_native((void __force __iomem *)mem); 617 else 618 return *mem; 619 } 620 621 void 622 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 623 { 624 bool is_iomem; 625 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 626 627 mem += index; 628 629 if (is_iomem) 630 iowrite32_native(val, (void __force __iomem *)mem); 631 else 632 *mem = val; 633 } 634 635 static struct ttm_tt * 636 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 637 { 638 #if IS_ENABLED(CONFIG_AGP) 639 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 640 641 if (drm->agp.bridge) { 642 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 643 } 644 #endif 645 646 return nouveau_sgdma_create_ttm(bo, page_flags); 647 } 648 649 static void 650 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 651 { 652 struct nouveau_bo *nvbo = nouveau_bo(bo); 653 654 switch (bo->mem.mem_type) { 655 case TTM_PL_VRAM: 656 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 657 TTM_PL_FLAG_SYSTEM); 658 break; 659 default: 660 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); 661 break; 662 } 663 664 *pl = nvbo->placement; 665 } 666 667 668 static int 669 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) 670 { 671 int ret = RING_SPACE(chan, 2); 672 if (ret == 0) { 673 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 674 OUT_RING (chan, handle & 0x0000ffff); 675 FIRE_RING (chan); 676 } 677 return ret; 678 } 679 680 static int 681 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 682 struct ttm_resource *old_reg, struct ttm_resource *new_reg) 683 { 684 struct nouveau_mem *mem = nouveau_mem(old_reg); 685 int ret = RING_SPACE(chan, 10); 686 if (ret == 0) { 687 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); 688 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 689 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 690 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 691 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 692 OUT_RING (chan, PAGE_SIZE); 693 OUT_RING (chan, PAGE_SIZE); 694 OUT_RING (chan, PAGE_SIZE); 695 OUT_RING (chan, new_reg->num_pages); 696 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); 697 } 698 return ret; 699 } 700 701 static int 702 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) 703 { 704 int ret = RING_SPACE(chan, 2); 705 if (ret == 0) { 706 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 707 OUT_RING (chan, handle); 708 } 709 return ret; 710 } 711 712 static int 713 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 714 struct ttm_resource *old_reg, struct ttm_resource *new_reg) 715 { 716 struct nouveau_mem *mem = nouveau_mem(old_reg); 717 u64 src_offset = mem->vma[0].addr; 718 u64 dst_offset = mem->vma[1].addr; 719 u32 page_count = new_reg->num_pages; 720 int ret; 721 722 page_count = new_reg->num_pages; 723 while (page_count) { 724 int line_count = (page_count > 8191) ? 8191 : page_count; 725 726 ret = RING_SPACE(chan, 11); 727 if (ret) 728 return ret; 729 730 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); 731 OUT_RING (chan, upper_32_bits(src_offset)); 732 OUT_RING (chan, lower_32_bits(src_offset)); 733 OUT_RING (chan, upper_32_bits(dst_offset)); 734 OUT_RING (chan, lower_32_bits(dst_offset)); 735 OUT_RING (chan, PAGE_SIZE); 736 OUT_RING (chan, PAGE_SIZE); 737 OUT_RING (chan, PAGE_SIZE); 738 OUT_RING (chan, line_count); 739 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 740 OUT_RING (chan, 0x00000110); 741 742 page_count -= line_count; 743 src_offset += (PAGE_SIZE * line_count); 744 dst_offset += (PAGE_SIZE * line_count); 745 } 746 747 return 0; 748 } 749 750 static int 751 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 752 struct ttm_resource *old_reg, struct ttm_resource *new_reg) 753 { 754 struct nouveau_mem *mem = nouveau_mem(old_reg); 755 u64 src_offset = mem->vma[0].addr; 756 u64 dst_offset = mem->vma[1].addr; 757 u32 page_count = new_reg->num_pages; 758 int ret; 759 760 page_count = new_reg->num_pages; 761 while (page_count) { 762 int line_count = (page_count > 2047) ? 2047 : page_count; 763 764 ret = RING_SPACE(chan, 12); 765 if (ret) 766 return ret; 767 768 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); 769 OUT_RING (chan, upper_32_bits(dst_offset)); 770 OUT_RING (chan, lower_32_bits(dst_offset)); 771 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); 772 OUT_RING (chan, upper_32_bits(src_offset)); 773 OUT_RING (chan, lower_32_bits(src_offset)); 774 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 775 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 776 OUT_RING (chan, PAGE_SIZE); /* line_length */ 777 OUT_RING (chan, line_count); 778 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 779 OUT_RING (chan, 0x00100110); 780 781 page_count -= line_count; 782 src_offset += (PAGE_SIZE * line_count); 783 dst_offset += (PAGE_SIZE * line_count); 784 } 785 786 return 0; 787 } 788 789 static int 790 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 791 struct ttm_resource *old_reg, struct ttm_resource *new_reg) 792 { 793 struct nouveau_mem *mem = nouveau_mem(old_reg); 794 u64 src_offset = mem->vma[0].addr; 795 u64 dst_offset = mem->vma[1].addr; 796 u32 page_count = new_reg->num_pages; 797 int ret; 798 799 page_count = new_reg->num_pages; 800 while (page_count) { 801 int line_count = (page_count > 8191) ? 8191 : page_count; 802 803 ret = RING_SPACE(chan, 11); 804 if (ret) 805 return ret; 806 807 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 808 OUT_RING (chan, upper_32_bits(src_offset)); 809 OUT_RING (chan, lower_32_bits(src_offset)); 810 OUT_RING (chan, upper_32_bits(dst_offset)); 811 OUT_RING (chan, lower_32_bits(dst_offset)); 812 OUT_RING (chan, PAGE_SIZE); 813 OUT_RING (chan, PAGE_SIZE); 814 OUT_RING (chan, PAGE_SIZE); 815 OUT_RING (chan, line_count); 816 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); 817 OUT_RING (chan, 0x00000110); 818 819 page_count -= line_count; 820 src_offset += (PAGE_SIZE * line_count); 821 dst_offset += (PAGE_SIZE * line_count); 822 } 823 824 return 0; 825 } 826 827 static int 828 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 829 struct ttm_resource *old_reg, struct ttm_resource *new_reg) 830 { 831 struct nouveau_mem *mem = nouveau_mem(old_reg); 832 int ret = RING_SPACE(chan, 7); 833 if (ret == 0) { 834 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); 835 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 836 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 837 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 838 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 839 OUT_RING (chan, 0x00000000 /* COPY */); 840 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 841 } 842 return ret; 843 } 844 845 static int 846 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 847 struct ttm_resource *old_reg, struct ttm_resource *new_reg) 848 { 849 struct nouveau_mem *mem = nouveau_mem(old_reg); 850 int ret = RING_SPACE(chan, 7); 851 if (ret == 0) { 852 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); 853 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 854 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 855 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 856 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 857 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 858 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); 859 } 860 return ret; 861 } 862 863 static int 864 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) 865 { 866 int ret = RING_SPACE(chan, 6); 867 if (ret == 0) { 868 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 869 OUT_RING (chan, handle); 870 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); 871 OUT_RING (chan, chan->drm->ntfy.handle); 872 OUT_RING (chan, chan->vram.handle); 873 OUT_RING (chan, chan->vram.handle); 874 } 875 876 return ret; 877 } 878 879 static int 880 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 881 struct ttm_resource *old_reg, struct ttm_resource *new_reg) 882 { 883 struct nouveau_mem *mem = nouveau_mem(old_reg); 884 u64 length = (new_reg->num_pages << PAGE_SHIFT); 885 u64 src_offset = mem->vma[0].addr; 886 u64 dst_offset = mem->vma[1].addr; 887 int src_tiled = !!mem->kind; 888 int dst_tiled = !!nouveau_mem(new_reg)->kind; 889 int ret; 890 891 while (length) { 892 u32 amount, stride, height; 893 894 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); 895 if (ret) 896 return ret; 897 898 amount = min(length, (u64)(4 * 1024 * 1024)); 899 stride = 16 * 4; 900 height = amount / stride; 901 902 if (src_tiled) { 903 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); 904 OUT_RING (chan, 0); 905 OUT_RING (chan, 0); 906 OUT_RING (chan, stride); 907 OUT_RING (chan, height); 908 OUT_RING (chan, 1); 909 OUT_RING (chan, 0); 910 OUT_RING (chan, 0); 911 } else { 912 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); 913 OUT_RING (chan, 1); 914 } 915 if (dst_tiled) { 916 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); 917 OUT_RING (chan, 0); 918 OUT_RING (chan, 0); 919 OUT_RING (chan, stride); 920 OUT_RING (chan, height); 921 OUT_RING (chan, 1); 922 OUT_RING (chan, 0); 923 OUT_RING (chan, 0); 924 } else { 925 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); 926 OUT_RING (chan, 1); 927 } 928 929 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); 930 OUT_RING (chan, upper_32_bits(src_offset)); 931 OUT_RING (chan, upper_32_bits(dst_offset)); 932 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 933 OUT_RING (chan, lower_32_bits(src_offset)); 934 OUT_RING (chan, lower_32_bits(dst_offset)); 935 OUT_RING (chan, stride); 936 OUT_RING (chan, stride); 937 OUT_RING (chan, stride); 938 OUT_RING (chan, height); 939 OUT_RING (chan, 0x00000101); 940 OUT_RING (chan, 0x00000000); 941 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 942 OUT_RING (chan, 0); 943 944 length -= amount; 945 src_offset += amount; 946 dst_offset += amount; 947 } 948 949 return 0; 950 } 951 952 static int 953 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) 954 { 955 int ret = RING_SPACE(chan, 4); 956 if (ret == 0) { 957 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 958 OUT_RING (chan, handle); 959 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); 960 OUT_RING (chan, chan->drm->ntfy.handle); 961 } 962 963 return ret; 964 } 965 966 static inline uint32_t 967 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, 968 struct nouveau_channel *chan, struct ttm_resource *reg) 969 { 970 if (reg->mem_type == TTM_PL_TT) 971 return NvDmaTT; 972 return chan->vram.handle; 973 } 974 975 static int 976 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 977 struct ttm_resource *old_reg, struct ttm_resource *new_reg) 978 { 979 u32 src_offset = old_reg->start << PAGE_SHIFT; 980 u32 dst_offset = new_reg->start << PAGE_SHIFT; 981 u32 page_count = new_reg->num_pages; 982 int ret; 983 984 ret = RING_SPACE(chan, 3); 985 if (ret) 986 return ret; 987 988 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); 989 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); 990 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); 991 992 page_count = new_reg->num_pages; 993 while (page_count) { 994 int line_count = (page_count > 2047) ? 2047 : page_count; 995 996 ret = RING_SPACE(chan, 11); 997 if (ret) 998 return ret; 999 1000 BEGIN_NV04(chan, NvSubCopy, 1001 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 1002 OUT_RING (chan, src_offset); 1003 OUT_RING (chan, dst_offset); 1004 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 1005 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 1006 OUT_RING (chan, PAGE_SIZE); /* line_length */ 1007 OUT_RING (chan, line_count); 1008 OUT_RING (chan, 0x00000101); 1009 OUT_RING (chan, 0x00000000); 1010 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 1011 OUT_RING (chan, 0); 1012 1013 page_count -= line_count; 1014 src_offset += (PAGE_SIZE * line_count); 1015 dst_offset += (PAGE_SIZE * line_count); 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int 1022 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 1023 struct ttm_resource *reg) 1024 { 1025 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 1026 struct nouveau_mem *new_mem = nouveau_mem(reg); 1027 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 1028 int ret; 1029 1030 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 1031 old_mem->mem.size, &old_mem->vma[0]); 1032 if (ret) 1033 return ret; 1034 1035 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 1036 new_mem->mem.size, &old_mem->vma[1]); 1037 if (ret) 1038 goto done; 1039 1040 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 1041 if (ret) 1042 goto done; 1043 1044 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 1045 done: 1046 if (ret) { 1047 nvif_vmm_put(vmm, &old_mem->vma[1]); 1048 nvif_vmm_put(vmm, &old_mem->vma[0]); 1049 } 1050 return 0; 1051 } 1052 1053 static int 1054 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, 1055 bool no_wait_gpu, struct ttm_resource *new_reg) 1056 { 1057 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1058 struct nouveau_channel *chan = drm->ttm.chan; 1059 struct nouveau_cli *cli = (void *)chan->user.client; 1060 struct nouveau_fence *fence; 1061 int ret; 1062 1063 /* create temporary vmas for the transfer and attach them to the 1064 * old nvkm_mem node, these will get cleaned up after ttm has 1065 * destroyed the ttm_resource 1066 */ 1067 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 1068 ret = nouveau_bo_move_prep(drm, bo, new_reg); 1069 if (ret) 1070 return ret; 1071 } 1072 1073 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 1074 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); 1075 if (ret == 0) { 1076 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 1077 if (ret == 0) { 1078 ret = nouveau_fence_new(chan, false, &fence); 1079 if (ret == 0) { 1080 ret = ttm_bo_move_accel_cleanup(bo, 1081 &fence->base, 1082 evict, 1083 new_reg); 1084 nouveau_fence_unref(&fence); 1085 } 1086 } 1087 } 1088 mutex_unlock(&cli->mutex); 1089 return ret; 1090 } 1091 1092 void 1093 nouveau_bo_move_init(struct nouveau_drm *drm) 1094 { 1095 static const struct _method_table { 1096 const char *name; 1097 int engine; 1098 s32 oclass; 1099 int (*exec)(struct nouveau_channel *, 1100 struct ttm_buffer_object *, 1101 struct ttm_resource *, struct ttm_resource *); 1102 int (*init)(struct nouveau_channel *, u32 handle); 1103 } _methods[] = { 1104 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, 1105 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1106 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 1107 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1108 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 1109 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1110 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1111 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1112 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1113 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1114 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1115 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1116 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 1117 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 1118 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 1119 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 1120 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 1121 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 1122 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 1123 {}, 1124 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, 1125 }; 1126 const struct _method_table *mthd = _methods; 1127 const char *name = "CPU"; 1128 int ret; 1129 1130 do { 1131 struct nouveau_channel *chan; 1132 1133 if (mthd->engine) 1134 chan = drm->cechan; 1135 else 1136 chan = drm->channel; 1137 if (chan == NULL) 1138 continue; 1139 1140 ret = nvif_object_init(&chan->user, 1141 mthd->oclass | (mthd->engine << 16), 1142 mthd->oclass, NULL, 0, 1143 &drm->ttm.copy); 1144 if (ret == 0) { 1145 ret = mthd->init(chan, drm->ttm.copy.handle); 1146 if (ret) { 1147 nvif_object_fini(&drm->ttm.copy); 1148 continue; 1149 } 1150 1151 drm->ttm.move = mthd->exec; 1152 drm->ttm.chan = chan; 1153 name = mthd->name; 1154 break; 1155 } 1156 } while ((++mthd)->exec); 1157 1158 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 1159 } 1160 1161 static int 1162 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 1163 bool no_wait_gpu, struct ttm_resource *new_reg) 1164 { 1165 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1166 struct ttm_place placement_memtype = { 1167 .fpfn = 0, 1168 .lpfn = 0, 1169 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1170 }; 1171 struct ttm_placement placement; 1172 struct ttm_resource tmp_reg; 1173 int ret; 1174 1175 placement.num_placement = placement.num_busy_placement = 1; 1176 placement.placement = placement.busy_placement = &placement_memtype; 1177 1178 tmp_reg = *new_reg; 1179 tmp_reg.mm_node = NULL; 1180 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1181 if (ret) 1182 return ret; 1183 1184 ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx); 1185 if (ret) 1186 goto out; 1187 1188 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); 1189 if (ret) 1190 goto out; 1191 1192 ret = ttm_bo_move_ttm(bo, &ctx, new_reg); 1193 out: 1194 ttm_bo_mem_put(bo, &tmp_reg); 1195 return ret; 1196 } 1197 1198 static int 1199 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 1200 bool no_wait_gpu, struct ttm_resource *new_reg) 1201 { 1202 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1203 struct ttm_place placement_memtype = { 1204 .fpfn = 0, 1205 .lpfn = 0, 1206 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1207 }; 1208 struct ttm_placement placement; 1209 struct ttm_resource tmp_reg; 1210 int ret; 1211 1212 placement.num_placement = placement.num_busy_placement = 1; 1213 placement.placement = placement.busy_placement = &placement_memtype; 1214 1215 tmp_reg = *new_reg; 1216 tmp_reg.mm_node = NULL; 1217 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1218 if (ret) 1219 return ret; 1220 1221 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg); 1222 if (ret) 1223 goto out; 1224 1225 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); 1226 if (ret) 1227 goto out; 1228 1229 out: 1230 ttm_bo_mem_put(bo, &tmp_reg); 1231 return ret; 1232 } 1233 1234 static void 1235 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, 1236 struct ttm_resource *new_reg) 1237 { 1238 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 1239 struct nouveau_bo *nvbo = nouveau_bo(bo); 1240 struct nouveau_vma *vma; 1241 1242 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 1243 if (bo->destroy != nouveau_bo_del_ttm) 1244 return; 1245 1246 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 1247 mem->mem.page == nvbo->page) { 1248 list_for_each_entry(vma, &nvbo->vma_list, head) { 1249 nouveau_vma_map(vma, mem); 1250 } 1251 } else { 1252 list_for_each_entry(vma, &nvbo->vma_list, head) { 1253 WARN_ON(ttm_bo_wait(bo, false, false)); 1254 nouveau_vma_unmap(vma); 1255 } 1256 } 1257 1258 if (new_reg) { 1259 if (new_reg->mm_node) 1260 nvbo->offset = (new_reg->start << PAGE_SHIFT); 1261 else 1262 nvbo->offset = 0; 1263 } 1264 1265 } 1266 1267 static int 1268 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg, 1269 struct nouveau_drm_tile **new_tile) 1270 { 1271 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1272 struct drm_device *dev = drm->dev; 1273 struct nouveau_bo *nvbo = nouveau_bo(bo); 1274 u64 offset = new_reg->start << PAGE_SHIFT; 1275 1276 *new_tile = NULL; 1277 if (new_reg->mem_type != TTM_PL_VRAM) 1278 return 0; 1279 1280 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 1281 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, 1282 nvbo->mode, nvbo->zeta); 1283 } 1284 1285 return 0; 1286 } 1287 1288 static void 1289 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 1290 struct nouveau_drm_tile *new_tile, 1291 struct nouveau_drm_tile **old_tile) 1292 { 1293 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1294 struct drm_device *dev = drm->dev; 1295 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv); 1296 1297 nv10_bo_put_tile_region(dev, *old_tile, fence); 1298 *old_tile = new_tile; 1299 } 1300 1301 static int 1302 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 1303 struct ttm_operation_ctx *ctx, 1304 struct ttm_resource *new_reg) 1305 { 1306 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1307 struct nouveau_bo *nvbo = nouveau_bo(bo); 1308 struct ttm_resource *old_reg = &bo->mem; 1309 struct nouveau_drm_tile *new_tile = NULL; 1310 int ret = 0; 1311 1312 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1313 if (ret) 1314 return ret; 1315 1316 if (nvbo->pin_refcnt) 1317 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 1318 1319 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1320 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 1321 if (ret) 1322 return ret; 1323 } 1324 1325 /* Fake bo copy. */ 1326 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 1327 BUG_ON(bo->mem.mm_node != NULL); 1328 bo->mem = *new_reg; 1329 new_reg->mm_node = NULL; 1330 goto out; 1331 } 1332 1333 /* Hardware assisted copy. */ 1334 if (drm->ttm.move) { 1335 if (new_reg->mem_type == TTM_PL_SYSTEM) 1336 ret = nouveau_bo_move_flipd(bo, evict, 1337 ctx->interruptible, 1338 ctx->no_wait_gpu, new_reg); 1339 else if (old_reg->mem_type == TTM_PL_SYSTEM) 1340 ret = nouveau_bo_move_flips(bo, evict, 1341 ctx->interruptible, 1342 ctx->no_wait_gpu, new_reg); 1343 else 1344 ret = nouveau_bo_move_m2mf(bo, evict, 1345 ctx->interruptible, 1346 ctx->no_wait_gpu, new_reg); 1347 if (!ret) 1348 goto out; 1349 } 1350 1351 /* Fallback to software copy. */ 1352 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1353 if (ret == 0) 1354 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1355 1356 out: 1357 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1358 if (ret) 1359 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1360 else 1361 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1362 } 1363 1364 return ret; 1365 } 1366 1367 static int 1368 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 1369 { 1370 struct nouveau_bo *nvbo = nouveau_bo(bo); 1371 1372 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node, 1373 filp->private_data); 1374 } 1375 1376 static int 1377 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) 1378 { 1379 struct nouveau_drm *drm = nouveau_bdev(bdev); 1380 struct nvkm_device *device = nvxx_device(&drm->client.device); 1381 struct nouveau_mem *mem = nouveau_mem(reg); 1382 1383 reg->bus.addr = NULL; 1384 reg->bus.offset = 0; 1385 reg->bus.size = reg->num_pages << PAGE_SHIFT; 1386 reg->bus.base = 0; 1387 reg->bus.is_iomem = false; 1388 1389 switch (reg->mem_type) { 1390 case TTM_PL_SYSTEM: 1391 /* System memory */ 1392 return 0; 1393 case TTM_PL_TT: 1394 #if IS_ENABLED(CONFIG_AGP) 1395 if (drm->agp.bridge) { 1396 reg->bus.offset = reg->start << PAGE_SHIFT; 1397 reg->bus.base = drm->agp.base; 1398 reg->bus.is_iomem = !drm->agp.cma; 1399 } 1400 #endif 1401 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) 1402 /* untiled */ 1403 break; 1404 /* fall through - tiled memory */ 1405 case TTM_PL_VRAM: 1406 reg->bus.offset = reg->start << PAGE_SHIFT; 1407 reg->bus.base = device->func->resource_addr(device, 1); 1408 reg->bus.is_iomem = true; 1409 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1410 union { 1411 struct nv50_mem_map_v0 nv50; 1412 struct gf100_mem_map_v0 gf100; 1413 } args; 1414 u64 handle, length; 1415 u32 argc = 0; 1416 int ret; 1417 1418 switch (mem->mem.object.oclass) { 1419 case NVIF_CLASS_MEM_NV50: 1420 args.nv50.version = 0; 1421 args.nv50.ro = 0; 1422 args.nv50.kind = mem->kind; 1423 args.nv50.comp = mem->comp; 1424 argc = sizeof(args.nv50); 1425 break; 1426 case NVIF_CLASS_MEM_GF100: 1427 args.gf100.version = 0; 1428 args.gf100.ro = 0; 1429 args.gf100.kind = mem->kind; 1430 argc = sizeof(args.gf100); 1431 break; 1432 default: 1433 WARN_ON(1); 1434 break; 1435 } 1436 1437 ret = nvif_object_map_handle(&mem->mem.object, 1438 &args, argc, 1439 &handle, &length); 1440 if (ret != 1) { 1441 if (WARN_ON(ret == 0)) 1442 return -EINVAL; 1443 return ret; 1444 } 1445 1446 reg->bus.base = 0; 1447 reg->bus.offset = handle; 1448 } 1449 break; 1450 default: 1451 return -EINVAL; 1452 } 1453 return 0; 1454 } 1455 1456 static void 1457 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_resource *reg) 1458 { 1459 struct nouveau_drm *drm = nouveau_bdev(bdev); 1460 struct nouveau_mem *mem = nouveau_mem(reg); 1461 1462 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1463 switch (reg->mem_type) { 1464 case TTM_PL_TT: 1465 if (mem->kind) 1466 nvif_object_unmap_handle(&mem->mem.object); 1467 break; 1468 case TTM_PL_VRAM: 1469 nvif_object_unmap_handle(&mem->mem.object); 1470 break; 1471 default: 1472 break; 1473 } 1474 } 1475 } 1476 1477 static int 1478 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1479 { 1480 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1481 struct nouveau_bo *nvbo = nouveau_bo(bo); 1482 struct nvkm_device *device = nvxx_device(&drm->client.device); 1483 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1484 int i, ret; 1485 1486 /* as long as the bo isn't in vram, and isn't tiled, we've got 1487 * nothing to do here. 1488 */ 1489 if (bo->mem.mem_type != TTM_PL_VRAM) { 1490 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1491 !nvbo->kind) 1492 return 0; 1493 1494 if (bo->mem.mem_type == TTM_PL_SYSTEM) { 1495 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); 1496 1497 ret = nouveau_bo_validate(nvbo, false, false); 1498 if (ret) 1499 return ret; 1500 } 1501 return 0; 1502 } 1503 1504 /* make sure bo is in mappable vram */ 1505 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1506 bo->mem.start + bo->mem.num_pages < mappable) 1507 return 0; 1508 1509 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1510 nvbo->placements[i].fpfn = 0; 1511 nvbo->placements[i].lpfn = mappable; 1512 } 1513 1514 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1515 nvbo->busy_placements[i].fpfn = 0; 1516 nvbo->busy_placements[i].lpfn = mappable; 1517 } 1518 1519 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); 1520 return nouveau_bo_validate(nvbo, false, false); 1521 } 1522 1523 static int 1524 nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1525 { 1526 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1527 struct nouveau_drm *drm; 1528 struct device *dev; 1529 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1530 1531 if (ttm->state != tt_unpopulated) 1532 return 0; 1533 1534 if (slave && ttm->sg) { 1535 /* make userspace faulting work */ 1536 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1537 ttm_dma->dma_address, ttm->num_pages); 1538 ttm->state = tt_unbound; 1539 return 0; 1540 } 1541 1542 drm = nouveau_bdev(ttm->bdev); 1543 dev = drm->dev->dev; 1544 1545 #if IS_ENABLED(CONFIG_AGP) 1546 if (drm->agp.bridge) { 1547 return ttm_agp_tt_populate(ttm, ctx); 1548 } 1549 #endif 1550 1551 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1552 if (swiotlb_nr_tbl()) { 1553 return ttm_dma_populate((void *)ttm, dev, ctx); 1554 } 1555 #endif 1556 return ttm_populate_and_map_pages(dev, ttm_dma, ctx); 1557 } 1558 1559 static void 1560 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) 1561 { 1562 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1563 struct nouveau_drm *drm; 1564 struct device *dev; 1565 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1566 1567 if (slave) 1568 return; 1569 1570 drm = nouveau_bdev(ttm->bdev); 1571 dev = drm->dev->dev; 1572 1573 #if IS_ENABLED(CONFIG_AGP) 1574 if (drm->agp.bridge) { 1575 ttm_agp_tt_unpopulate(ttm); 1576 return; 1577 } 1578 #endif 1579 1580 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1581 if (swiotlb_nr_tbl()) { 1582 ttm_dma_unpopulate((void *)ttm, dev); 1583 return; 1584 } 1585 #endif 1586 1587 ttm_unmap_and_unpopulate_pages(dev, ttm_dma); 1588 } 1589 1590 void 1591 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1592 { 1593 struct dma_resv *resv = nvbo->bo.base.resv; 1594 1595 if (exclusive) 1596 dma_resv_add_excl_fence(resv, &fence->base); 1597 else if (fence) 1598 dma_resv_add_shared_fence(resv, &fence->base); 1599 } 1600 1601 struct ttm_bo_driver nouveau_bo_driver = { 1602 .ttm_tt_create = &nouveau_ttm_tt_create, 1603 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1604 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1605 .eviction_valuable = ttm_bo_eviction_valuable, 1606 .evict_flags = nouveau_bo_evict_flags, 1607 .move_notify = nouveau_bo_move_ntfy, 1608 .move = nouveau_bo_move, 1609 .verify_access = nouveau_bo_verify_access, 1610 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, 1611 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1612 .io_mem_free = &nouveau_ttm_io_mem_free, 1613 }; 1614