1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 #include <linux/swiotlb.h> 32 33 #include "nouveau_drv.h" 34 #include "nouveau_dma.h" 35 #include "nouveau_fence.h" 36 37 #include "nouveau_bo.h" 38 #include "nouveau_ttm.h" 39 #include "nouveau_gem.h" 40 #include "nouveau_mem.h" 41 #include "nouveau_vmm.h" 42 43 #include <nvif/class.h> 44 #include <nvif/if500b.h> 45 #include <nvif/if900b.h> 46 47 /* 48 * NV10-NV40 tiling helpers 49 */ 50 51 static void 52 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 53 u32 addr, u32 size, u32 pitch, u32 flags) 54 { 55 struct nouveau_drm *drm = nouveau_drm(dev); 56 int i = reg - drm->tile.reg; 57 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 58 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 59 60 nouveau_fence_unref(®->fence); 61 62 if (tile->pitch) 63 nvkm_fb_tile_fini(fb, i, tile); 64 65 if (pitch) 66 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 67 68 nvkm_fb_tile_prog(fb, i, tile); 69 } 70 71 static struct nouveau_drm_tile * 72 nv10_bo_get_tile_region(struct drm_device *dev, int i) 73 { 74 struct nouveau_drm *drm = nouveau_drm(dev); 75 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 76 77 spin_lock(&drm->tile.lock); 78 79 if (!tile->used && 80 (!tile->fence || nouveau_fence_done(tile->fence))) 81 tile->used = true; 82 else 83 tile = NULL; 84 85 spin_unlock(&drm->tile.lock); 86 return tile; 87 } 88 89 static void 90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 91 struct dma_fence *fence) 92 { 93 struct nouveau_drm *drm = nouveau_drm(dev); 94 95 if (tile) { 96 spin_lock(&drm->tile.lock); 97 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 98 tile->used = false; 99 spin_unlock(&drm->tile.lock); 100 } 101 } 102 103 static struct nouveau_drm_tile * 104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 105 u32 size, u32 pitch, u32 zeta) 106 { 107 struct nouveau_drm *drm = nouveau_drm(dev); 108 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 109 struct nouveau_drm_tile *tile, *found = NULL; 110 int i; 111 112 for (i = 0; i < fb->tile.regions; i++) { 113 tile = nv10_bo_get_tile_region(dev, i); 114 115 if (pitch && !found) { 116 found = tile; 117 continue; 118 119 } else if (tile && fb->tile.region[i].pitch) { 120 /* Kill an unused tile region. */ 121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 122 } 123 124 nv10_bo_put_tile_region(dev, tile, NULL); 125 } 126 127 if (found) 128 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 129 return found; 130 } 131 132 static void 133 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 134 { 135 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 136 struct drm_device *dev = drm->dev; 137 struct nouveau_bo *nvbo = nouveau_bo(bo); 138 139 WARN_ON(nvbo->pin_refcnt > 0); 140 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 141 142 /* 143 * If nouveau_bo_new() allocated this buffer, the GEM object was never 144 * initialized, so don't attempt to release it. 145 */ 146 if (bo->base.dev) 147 drm_gem_object_release(&bo->base); 148 149 kfree(nvbo); 150 } 151 152 static inline u64 153 roundup_64(u64 x, u32 y) 154 { 155 x += y - 1; 156 do_div(x, y); 157 return x * y; 158 } 159 160 static void 161 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, 162 int *align, u64 *size) 163 { 164 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 165 struct nvif_device *device = &drm->client.device; 166 167 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 168 if (nvbo->mode) { 169 if (device->info.chipset >= 0x40) { 170 *align = 65536; 171 *size = roundup_64(*size, 64 * nvbo->mode); 172 173 } else if (device->info.chipset >= 0x30) { 174 *align = 32768; 175 *size = roundup_64(*size, 64 * nvbo->mode); 176 177 } else if (device->info.chipset >= 0x20) { 178 *align = 16384; 179 *size = roundup_64(*size, 64 * nvbo->mode); 180 181 } else if (device->info.chipset >= 0x10) { 182 *align = 16384; 183 *size = roundup_64(*size, 32 * nvbo->mode); 184 } 185 } 186 } else { 187 *size = roundup_64(*size, (1 << nvbo->page)); 188 *align = max((1 << nvbo->page), *align); 189 } 190 191 *size = roundup_64(*size, PAGE_SIZE); 192 } 193 194 struct nouveau_bo * 195 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 flags, 196 u32 tile_mode, u32 tile_flags) 197 { 198 struct nouveau_drm *drm = cli->drm; 199 struct nouveau_bo *nvbo; 200 struct nvif_mmu *mmu = &cli->mmu; 201 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm; 202 int i, pi = -1; 203 204 if (!*size) { 205 NV_WARN(drm, "skipped size %016llx\n", *size); 206 return ERR_PTR(-EINVAL); 207 } 208 209 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 210 if (!nvbo) 211 return ERR_PTR(-ENOMEM); 212 INIT_LIST_HEAD(&nvbo->head); 213 INIT_LIST_HEAD(&nvbo->entry); 214 INIT_LIST_HEAD(&nvbo->vma_list); 215 nvbo->bo.bdev = &drm->ttm.bdev; 216 217 /* This is confusing, and doesn't actually mean we want an uncached 218 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 219 * into in nouveau_gem_new(). 220 */ 221 if (flags & TTM_PL_FLAG_UNCACHED) { 222 /* Determine if we can get a cache-coherent map, forcing 223 * uncached mapping if we can't. 224 */ 225 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 226 nvbo->force_coherent = true; 227 } 228 229 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 230 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 231 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 232 kfree(nvbo); 233 return ERR_PTR(-EINVAL); 234 } 235 236 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 237 } else 238 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 239 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 240 nvbo->comp = (tile_flags & 0x00030000) >> 16; 241 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 242 kfree(nvbo); 243 return ERR_PTR(-EINVAL); 244 } 245 } else { 246 nvbo->zeta = (tile_flags & 0x00000007); 247 } 248 nvbo->mode = tile_mode; 249 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 250 251 /* Determine the desirable target GPU page size for the buffer. */ 252 for (i = 0; i < vmm->page_nr; i++) { 253 /* Because we cannot currently allow VMM maps to fail 254 * during buffer migration, we need to determine page 255 * size for the buffer up-front, and pre-allocate its 256 * page tables. 257 * 258 * Skip page sizes that can't support needed domains. 259 */ 260 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 261 (flags & TTM_PL_FLAG_VRAM) && !vmm->page[i].vram) 262 continue; 263 if ((flags & TTM_PL_FLAG_TT) && 264 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 265 continue; 266 267 /* Select this page size if it's the first that supports 268 * the potential memory domains, or when it's compatible 269 * with the requested compression settings. 270 */ 271 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 272 pi = i; 273 274 /* Stop once the buffer is larger than the current page size. */ 275 if (*size >= 1ULL << vmm->page[i].shift) 276 break; 277 } 278 279 if (WARN_ON(pi < 0)) 280 return ERR_PTR(-EINVAL); 281 282 /* Disable compression if suitable settings couldn't be found. */ 283 if (nvbo->comp && !vmm->page[pi].comp) { 284 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 285 nvbo->kind = mmu->kind[nvbo->kind]; 286 nvbo->comp = 0; 287 } 288 nvbo->page = vmm->page[pi].shift; 289 290 nouveau_bo_fixup_align(nvbo, flags, align, size); 291 292 return nvbo; 293 } 294 295 int 296 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 flags, 297 struct sg_table *sg, struct dma_resv *robj) 298 { 299 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device; 300 size_t acc_size; 301 int ret; 302 303 acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo)); 304 305 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; 306 nouveau_bo_placement_set(nvbo, flags, 0); 307 308 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type, 309 &nvbo->placement, align >> PAGE_SHIFT, false, 310 acc_size, sg, robj, nouveau_bo_del_ttm); 311 if (ret) { 312 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 313 return ret; 314 } 315 316 return 0; 317 } 318 319 int 320 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 321 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, 322 struct sg_table *sg, struct dma_resv *robj, 323 struct nouveau_bo **pnvbo) 324 { 325 struct nouveau_bo *nvbo; 326 int ret; 327 328 nvbo = nouveau_bo_alloc(cli, &size, &align, flags, tile_mode, 329 tile_flags); 330 if (IS_ERR(nvbo)) 331 return PTR_ERR(nvbo); 332 333 ret = nouveau_bo_init(nvbo, size, align, flags, sg, robj); 334 if (ret) 335 return ret; 336 337 *pnvbo = nvbo; 338 return 0; 339 } 340 341 static void 342 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) 343 { 344 *n = 0; 345 346 if (type & TTM_PL_FLAG_VRAM) 347 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; 348 if (type & TTM_PL_FLAG_TT) 349 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; 350 if (type & TTM_PL_FLAG_SYSTEM) 351 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; 352 } 353 354 static void 355 set_placement_range(struct nouveau_bo *nvbo, uint32_t type) 356 { 357 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 358 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; 359 unsigned i, fpfn, lpfn; 360 361 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 362 nvbo->mode && (type & TTM_PL_FLAG_VRAM) && 363 nvbo->bo.mem.num_pages < vram_pages / 4) { 364 /* 365 * Make sure that the color and depth buffers are handled 366 * by independent memory controller units. Up to a 9x 367 * speed up when alpha-blending and depth-test are enabled 368 * at the same time. 369 */ 370 if (nvbo->zeta) { 371 fpfn = vram_pages / 2; 372 lpfn = ~0; 373 } else { 374 fpfn = 0; 375 lpfn = vram_pages / 2; 376 } 377 for (i = 0; i < nvbo->placement.num_placement; ++i) { 378 nvbo->placements[i].fpfn = fpfn; 379 nvbo->placements[i].lpfn = lpfn; 380 } 381 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 382 nvbo->busy_placements[i].fpfn = fpfn; 383 nvbo->busy_placements[i].lpfn = lpfn; 384 } 385 } 386 } 387 388 void 389 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) 390 { 391 struct ttm_placement *pl = &nvbo->placement; 392 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED : 393 TTM_PL_MASK_CACHING) | 394 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); 395 396 pl->placement = nvbo->placements; 397 set_placement_list(nvbo->placements, &pl->num_placement, 398 type, flags); 399 400 pl->busy_placement = nvbo->busy_placements; 401 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 402 type | busy, flags); 403 404 set_placement_range(nvbo, type); 405 } 406 407 int 408 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig) 409 { 410 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 411 struct ttm_buffer_object *bo = &nvbo->bo; 412 bool force = false, evict = false; 413 int ret; 414 415 ret = ttm_bo_reserve(bo, false, false, NULL); 416 if (ret) 417 return ret; 418 419 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 420 memtype == TTM_PL_FLAG_VRAM && contig) { 421 if (!nvbo->contig) { 422 nvbo->contig = true; 423 force = true; 424 evict = true; 425 } 426 } 427 428 if (nvbo->pin_refcnt) { 429 if (!(memtype & (1 << bo->mem.mem_type)) || evict) { 430 NV_ERROR(drm, "bo %p pinned elsewhere: " 431 "0x%08x vs 0x%08x\n", bo, 432 1 << bo->mem.mem_type, memtype); 433 ret = -EBUSY; 434 } 435 nvbo->pin_refcnt++; 436 goto out; 437 } 438 439 if (evict) { 440 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0); 441 ret = nouveau_bo_validate(nvbo, false, false); 442 if (ret) 443 goto out; 444 } 445 446 nvbo->pin_refcnt++; 447 nouveau_bo_placement_set(nvbo, memtype, 0); 448 449 /* drop pin_refcnt temporarily, so we don't trip the assertion 450 * in nouveau_bo_move() that makes sure we're not trying to 451 * move a pinned buffer 452 */ 453 nvbo->pin_refcnt--; 454 ret = nouveau_bo_validate(nvbo, false, false); 455 if (ret) 456 goto out; 457 nvbo->pin_refcnt++; 458 459 switch (bo->mem.mem_type) { 460 case TTM_PL_VRAM: 461 drm->gem.vram_available -= bo->mem.size; 462 break; 463 case TTM_PL_TT: 464 drm->gem.gart_available -= bo->mem.size; 465 break; 466 default: 467 break; 468 } 469 470 out: 471 if (force && ret) 472 nvbo->contig = false; 473 ttm_bo_unreserve(bo); 474 return ret; 475 } 476 477 int 478 nouveau_bo_unpin(struct nouveau_bo *nvbo) 479 { 480 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 481 struct ttm_buffer_object *bo = &nvbo->bo; 482 int ret, ref; 483 484 ret = ttm_bo_reserve(bo, false, false, NULL); 485 if (ret) 486 return ret; 487 488 ref = --nvbo->pin_refcnt; 489 WARN_ON_ONCE(ref < 0); 490 if (ref) 491 goto out; 492 493 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); 494 495 ret = nouveau_bo_validate(nvbo, false, false); 496 if (ret == 0) { 497 switch (bo->mem.mem_type) { 498 case TTM_PL_VRAM: 499 drm->gem.vram_available += bo->mem.size; 500 break; 501 case TTM_PL_TT: 502 drm->gem.gart_available += bo->mem.size; 503 break; 504 default: 505 break; 506 } 507 } 508 509 out: 510 ttm_bo_unreserve(bo); 511 return ret; 512 } 513 514 int 515 nouveau_bo_map(struct nouveau_bo *nvbo) 516 { 517 int ret; 518 519 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 520 if (ret) 521 return ret; 522 523 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 524 525 ttm_bo_unreserve(&nvbo->bo); 526 return ret; 527 } 528 529 void 530 nouveau_bo_unmap(struct nouveau_bo *nvbo) 531 { 532 if (!nvbo) 533 return; 534 535 ttm_bo_kunmap(&nvbo->kmap); 536 } 537 538 void 539 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 540 { 541 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 542 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 543 int i; 544 545 if (!ttm_dma) 546 return; 547 548 /* Don't waste time looping if the object is coherent */ 549 if (nvbo->force_coherent) 550 return; 551 552 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 553 dma_sync_single_for_device(drm->dev->dev, 554 ttm_dma->dma_address[i], 555 PAGE_SIZE, DMA_TO_DEVICE); 556 } 557 558 void 559 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 560 { 561 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 562 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm; 563 int i; 564 565 if (!ttm_dma) 566 return; 567 568 /* Don't waste time looping if the object is coherent */ 569 if (nvbo->force_coherent) 570 return; 571 572 for (i = 0; i < ttm_dma->ttm.num_pages; i++) 573 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 574 PAGE_SIZE, DMA_FROM_DEVICE); 575 } 576 577 int 578 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 579 bool no_wait_gpu) 580 { 581 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 582 int ret; 583 584 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 585 if (ret) 586 return ret; 587 588 nouveau_bo_sync_for_device(nvbo); 589 590 return 0; 591 } 592 593 void 594 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 595 { 596 bool is_iomem; 597 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 598 599 mem += index; 600 601 if (is_iomem) 602 iowrite16_native(val, (void __force __iomem *)mem); 603 else 604 *mem = val; 605 } 606 607 u32 608 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 609 { 610 bool is_iomem; 611 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 612 613 mem += index; 614 615 if (is_iomem) 616 return ioread32_native((void __force __iomem *)mem); 617 else 618 return *mem; 619 } 620 621 void 622 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 623 { 624 bool is_iomem; 625 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 626 627 mem += index; 628 629 if (is_iomem) 630 iowrite32_native(val, (void __force __iomem *)mem); 631 else 632 *mem = val; 633 } 634 635 static struct ttm_tt * 636 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 637 { 638 #if IS_ENABLED(CONFIG_AGP) 639 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 640 641 if (drm->agp.bridge) { 642 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 643 } 644 #endif 645 646 return nouveau_sgdma_create_ttm(bo, page_flags); 647 } 648 649 static int 650 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 651 struct ttm_mem_type_manager *man) 652 { 653 struct nouveau_drm *drm = nouveau_bdev(bdev); 654 struct nvif_mmu *mmu = &drm->client.mmu; 655 656 switch (type) { 657 case TTM_PL_SYSTEM: 658 man->flags = 0; 659 man->available_caching = TTM_PL_MASK_CACHING; 660 man->default_caching = TTM_PL_FLAG_CACHED; 661 break; 662 case TTM_PL_VRAM: 663 man->flags = TTM_MEMTYPE_FLAG_FIXED; 664 man->available_caching = TTM_PL_FLAG_UNCACHED | 665 TTM_PL_FLAG_WC; 666 man->default_caching = TTM_PL_FLAG_WC; 667 668 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 669 /* Some BARs do not support being ioremapped WC */ 670 const u8 type = mmu->type[drm->ttm.type_vram].type; 671 if (type & NVIF_MEM_UNCACHED) { 672 man->available_caching = TTM_PL_FLAG_UNCACHED; 673 man->default_caching = TTM_PL_FLAG_UNCACHED; 674 } 675 676 man->func = &nouveau_vram_manager; 677 man->use_io_reserve_lru = true; 678 } else { 679 man->func = &ttm_bo_manager_func; 680 } 681 break; 682 case TTM_PL_TT: 683 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) 684 man->func = &nouveau_gart_manager; 685 else 686 if (!drm->agp.bridge) 687 man->func = &nv04_gart_manager; 688 else 689 man->func = &ttm_bo_manager_func; 690 691 if (drm->agp.bridge) { 692 man->flags = 0; 693 man->available_caching = TTM_PL_FLAG_UNCACHED | 694 TTM_PL_FLAG_WC; 695 man->default_caching = TTM_PL_FLAG_WC; 696 } else { 697 man->flags = 0; 698 man->available_caching = TTM_PL_MASK_CACHING; 699 man->default_caching = TTM_PL_FLAG_CACHED; 700 } 701 702 break; 703 default: 704 return -EINVAL; 705 } 706 return 0; 707 } 708 709 static void 710 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 711 { 712 struct nouveau_bo *nvbo = nouveau_bo(bo); 713 714 switch (bo->mem.mem_type) { 715 case TTM_PL_VRAM: 716 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 717 TTM_PL_FLAG_SYSTEM); 718 break; 719 default: 720 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); 721 break; 722 } 723 724 *pl = nvbo->placement; 725 } 726 727 728 static int 729 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) 730 { 731 int ret = RING_SPACE(chan, 2); 732 if (ret == 0) { 733 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 734 OUT_RING (chan, handle & 0x0000ffff); 735 FIRE_RING (chan); 736 } 737 return ret; 738 } 739 740 static int 741 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 742 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 743 { 744 struct nouveau_mem *mem = nouveau_mem(old_reg); 745 int ret = RING_SPACE(chan, 10); 746 if (ret == 0) { 747 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); 748 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 749 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 750 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 751 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 752 OUT_RING (chan, PAGE_SIZE); 753 OUT_RING (chan, PAGE_SIZE); 754 OUT_RING (chan, PAGE_SIZE); 755 OUT_RING (chan, new_reg->num_pages); 756 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); 757 } 758 return ret; 759 } 760 761 static int 762 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) 763 { 764 int ret = RING_SPACE(chan, 2); 765 if (ret == 0) { 766 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); 767 OUT_RING (chan, handle); 768 } 769 return ret; 770 } 771 772 static int 773 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 774 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 775 { 776 struct nouveau_mem *mem = nouveau_mem(old_reg); 777 u64 src_offset = mem->vma[0].addr; 778 u64 dst_offset = mem->vma[1].addr; 779 u32 page_count = new_reg->num_pages; 780 int ret; 781 782 page_count = new_reg->num_pages; 783 while (page_count) { 784 int line_count = (page_count > 8191) ? 8191 : page_count; 785 786 ret = RING_SPACE(chan, 11); 787 if (ret) 788 return ret; 789 790 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); 791 OUT_RING (chan, upper_32_bits(src_offset)); 792 OUT_RING (chan, lower_32_bits(src_offset)); 793 OUT_RING (chan, upper_32_bits(dst_offset)); 794 OUT_RING (chan, lower_32_bits(dst_offset)); 795 OUT_RING (chan, PAGE_SIZE); 796 OUT_RING (chan, PAGE_SIZE); 797 OUT_RING (chan, PAGE_SIZE); 798 OUT_RING (chan, line_count); 799 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 800 OUT_RING (chan, 0x00000110); 801 802 page_count -= line_count; 803 src_offset += (PAGE_SIZE * line_count); 804 dst_offset += (PAGE_SIZE * line_count); 805 } 806 807 return 0; 808 } 809 810 static int 811 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 812 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 813 { 814 struct nouveau_mem *mem = nouveau_mem(old_reg); 815 u64 src_offset = mem->vma[0].addr; 816 u64 dst_offset = mem->vma[1].addr; 817 u32 page_count = new_reg->num_pages; 818 int ret; 819 820 page_count = new_reg->num_pages; 821 while (page_count) { 822 int line_count = (page_count > 2047) ? 2047 : page_count; 823 824 ret = RING_SPACE(chan, 12); 825 if (ret) 826 return ret; 827 828 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); 829 OUT_RING (chan, upper_32_bits(dst_offset)); 830 OUT_RING (chan, lower_32_bits(dst_offset)); 831 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); 832 OUT_RING (chan, upper_32_bits(src_offset)); 833 OUT_RING (chan, lower_32_bits(src_offset)); 834 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 835 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 836 OUT_RING (chan, PAGE_SIZE); /* line_length */ 837 OUT_RING (chan, line_count); 838 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); 839 OUT_RING (chan, 0x00100110); 840 841 page_count -= line_count; 842 src_offset += (PAGE_SIZE * line_count); 843 dst_offset += (PAGE_SIZE * line_count); 844 } 845 846 return 0; 847 } 848 849 static int 850 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 851 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 852 { 853 struct nouveau_mem *mem = nouveau_mem(old_reg); 854 u64 src_offset = mem->vma[0].addr; 855 u64 dst_offset = mem->vma[1].addr; 856 u32 page_count = new_reg->num_pages; 857 int ret; 858 859 page_count = new_reg->num_pages; 860 while (page_count) { 861 int line_count = (page_count > 8191) ? 8191 : page_count; 862 863 ret = RING_SPACE(chan, 11); 864 if (ret) 865 return ret; 866 867 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 868 OUT_RING (chan, upper_32_bits(src_offset)); 869 OUT_RING (chan, lower_32_bits(src_offset)); 870 OUT_RING (chan, upper_32_bits(dst_offset)); 871 OUT_RING (chan, lower_32_bits(dst_offset)); 872 OUT_RING (chan, PAGE_SIZE); 873 OUT_RING (chan, PAGE_SIZE); 874 OUT_RING (chan, PAGE_SIZE); 875 OUT_RING (chan, line_count); 876 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); 877 OUT_RING (chan, 0x00000110); 878 879 page_count -= line_count; 880 src_offset += (PAGE_SIZE * line_count); 881 dst_offset += (PAGE_SIZE * line_count); 882 } 883 884 return 0; 885 } 886 887 static int 888 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 889 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 890 { 891 struct nouveau_mem *mem = nouveau_mem(old_reg); 892 int ret = RING_SPACE(chan, 7); 893 if (ret == 0) { 894 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); 895 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 896 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 897 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 898 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 899 OUT_RING (chan, 0x00000000 /* COPY */); 900 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 901 } 902 return ret; 903 } 904 905 static int 906 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 907 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 908 { 909 struct nouveau_mem *mem = nouveau_mem(old_reg); 910 int ret = RING_SPACE(chan, 7); 911 if (ret == 0) { 912 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); 913 OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); 914 OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); 915 OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); 916 OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); 917 OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); 918 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); 919 } 920 return ret; 921 } 922 923 static int 924 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) 925 { 926 int ret = RING_SPACE(chan, 6); 927 if (ret == 0) { 928 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 929 OUT_RING (chan, handle); 930 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); 931 OUT_RING (chan, chan->drm->ntfy.handle); 932 OUT_RING (chan, chan->vram.handle); 933 OUT_RING (chan, chan->vram.handle); 934 } 935 936 return ret; 937 } 938 939 static int 940 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 941 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 942 { 943 struct nouveau_mem *mem = nouveau_mem(old_reg); 944 u64 length = (new_reg->num_pages << PAGE_SHIFT); 945 u64 src_offset = mem->vma[0].addr; 946 u64 dst_offset = mem->vma[1].addr; 947 int src_tiled = !!mem->kind; 948 int dst_tiled = !!nouveau_mem(new_reg)->kind; 949 int ret; 950 951 while (length) { 952 u32 amount, stride, height; 953 954 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); 955 if (ret) 956 return ret; 957 958 amount = min(length, (u64)(4 * 1024 * 1024)); 959 stride = 16 * 4; 960 height = amount / stride; 961 962 if (src_tiled) { 963 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); 964 OUT_RING (chan, 0); 965 OUT_RING (chan, 0); 966 OUT_RING (chan, stride); 967 OUT_RING (chan, height); 968 OUT_RING (chan, 1); 969 OUT_RING (chan, 0); 970 OUT_RING (chan, 0); 971 } else { 972 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); 973 OUT_RING (chan, 1); 974 } 975 if (dst_tiled) { 976 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); 977 OUT_RING (chan, 0); 978 OUT_RING (chan, 0); 979 OUT_RING (chan, stride); 980 OUT_RING (chan, height); 981 OUT_RING (chan, 1); 982 OUT_RING (chan, 0); 983 OUT_RING (chan, 0); 984 } else { 985 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); 986 OUT_RING (chan, 1); 987 } 988 989 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); 990 OUT_RING (chan, upper_32_bits(src_offset)); 991 OUT_RING (chan, upper_32_bits(dst_offset)); 992 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); 993 OUT_RING (chan, lower_32_bits(src_offset)); 994 OUT_RING (chan, lower_32_bits(dst_offset)); 995 OUT_RING (chan, stride); 996 OUT_RING (chan, stride); 997 OUT_RING (chan, stride); 998 OUT_RING (chan, height); 999 OUT_RING (chan, 0x00000101); 1000 OUT_RING (chan, 0x00000000); 1001 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 1002 OUT_RING (chan, 0); 1003 1004 length -= amount; 1005 src_offset += amount; 1006 dst_offset += amount; 1007 } 1008 1009 return 0; 1010 } 1011 1012 static int 1013 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) 1014 { 1015 int ret = RING_SPACE(chan, 4); 1016 if (ret == 0) { 1017 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); 1018 OUT_RING (chan, handle); 1019 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); 1020 OUT_RING (chan, chan->drm->ntfy.handle); 1021 } 1022 1023 return ret; 1024 } 1025 1026 static inline uint32_t 1027 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, 1028 struct nouveau_channel *chan, struct ttm_mem_reg *reg) 1029 { 1030 if (reg->mem_type == TTM_PL_TT) 1031 return NvDmaTT; 1032 return chan->vram.handle; 1033 } 1034 1035 static int 1036 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, 1037 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) 1038 { 1039 u32 src_offset = old_reg->start << PAGE_SHIFT; 1040 u32 dst_offset = new_reg->start << PAGE_SHIFT; 1041 u32 page_count = new_reg->num_pages; 1042 int ret; 1043 1044 ret = RING_SPACE(chan, 3); 1045 if (ret) 1046 return ret; 1047 1048 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); 1049 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); 1050 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); 1051 1052 page_count = new_reg->num_pages; 1053 while (page_count) { 1054 int line_count = (page_count > 2047) ? 2047 : page_count; 1055 1056 ret = RING_SPACE(chan, 11); 1057 if (ret) 1058 return ret; 1059 1060 BEGIN_NV04(chan, NvSubCopy, 1061 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 1062 OUT_RING (chan, src_offset); 1063 OUT_RING (chan, dst_offset); 1064 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 1065 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 1066 OUT_RING (chan, PAGE_SIZE); /* line_length */ 1067 OUT_RING (chan, line_count); 1068 OUT_RING (chan, 0x00000101); 1069 OUT_RING (chan, 0x00000000); 1070 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 1071 OUT_RING (chan, 0); 1072 1073 page_count -= line_count; 1074 src_offset += (PAGE_SIZE * line_count); 1075 dst_offset += (PAGE_SIZE * line_count); 1076 } 1077 1078 return 0; 1079 } 1080 1081 static int 1082 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 1083 struct ttm_mem_reg *reg) 1084 { 1085 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 1086 struct nouveau_mem *new_mem = nouveau_mem(reg); 1087 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 1088 int ret; 1089 1090 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 1091 old_mem->mem.size, &old_mem->vma[0]); 1092 if (ret) 1093 return ret; 1094 1095 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 1096 new_mem->mem.size, &old_mem->vma[1]); 1097 if (ret) 1098 goto done; 1099 1100 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 1101 if (ret) 1102 goto done; 1103 1104 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 1105 done: 1106 if (ret) { 1107 nvif_vmm_put(vmm, &old_mem->vma[1]); 1108 nvif_vmm_put(vmm, &old_mem->vma[0]); 1109 } 1110 return 0; 1111 } 1112 1113 static int 1114 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, 1115 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1116 { 1117 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1118 struct nouveau_channel *chan = drm->ttm.chan; 1119 struct nouveau_cli *cli = (void *)chan->user.client; 1120 struct nouveau_fence *fence; 1121 int ret; 1122 1123 /* create temporary vmas for the transfer and attach them to the 1124 * old nvkm_mem node, these will get cleaned up after ttm has 1125 * destroyed the ttm_mem_reg 1126 */ 1127 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 1128 ret = nouveau_bo_move_prep(drm, bo, new_reg); 1129 if (ret) 1130 return ret; 1131 } 1132 1133 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 1134 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); 1135 if (ret == 0) { 1136 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 1137 if (ret == 0) { 1138 ret = nouveau_fence_new(chan, false, &fence); 1139 if (ret == 0) { 1140 ret = ttm_bo_move_accel_cleanup(bo, 1141 &fence->base, 1142 evict, 1143 new_reg); 1144 nouveau_fence_unref(&fence); 1145 } 1146 } 1147 } 1148 mutex_unlock(&cli->mutex); 1149 return ret; 1150 } 1151 1152 void 1153 nouveau_bo_move_init(struct nouveau_drm *drm) 1154 { 1155 static const struct _method_table { 1156 const char *name; 1157 int engine; 1158 s32 oclass; 1159 int (*exec)(struct nouveau_channel *, 1160 struct ttm_buffer_object *, 1161 struct ttm_mem_reg *, struct ttm_mem_reg *); 1162 int (*init)(struct nouveau_channel *, u32 handle); 1163 } _methods[] = { 1164 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, 1165 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1166 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 1167 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1168 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 1169 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1170 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1171 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1172 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1173 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1174 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 1175 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 1176 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 1177 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 1178 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 1179 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 1180 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 1181 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 1182 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 1183 {}, 1184 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, 1185 }; 1186 const struct _method_table *mthd = _methods; 1187 const char *name = "CPU"; 1188 int ret; 1189 1190 do { 1191 struct nouveau_channel *chan; 1192 1193 if (mthd->engine) 1194 chan = drm->cechan; 1195 else 1196 chan = drm->channel; 1197 if (chan == NULL) 1198 continue; 1199 1200 ret = nvif_object_init(&chan->user, 1201 mthd->oclass | (mthd->engine << 16), 1202 mthd->oclass, NULL, 0, 1203 &drm->ttm.copy); 1204 if (ret == 0) { 1205 ret = mthd->init(chan, drm->ttm.copy.handle); 1206 if (ret) { 1207 nvif_object_fini(&drm->ttm.copy); 1208 continue; 1209 } 1210 1211 drm->ttm.move = mthd->exec; 1212 drm->ttm.chan = chan; 1213 name = mthd->name; 1214 break; 1215 } 1216 } while ((++mthd)->exec); 1217 1218 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 1219 } 1220 1221 static int 1222 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 1223 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1224 { 1225 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1226 struct ttm_place placement_memtype = { 1227 .fpfn = 0, 1228 .lpfn = 0, 1229 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1230 }; 1231 struct ttm_placement placement; 1232 struct ttm_mem_reg tmp_reg; 1233 int ret; 1234 1235 placement.num_placement = placement.num_busy_placement = 1; 1236 placement.placement = placement.busy_placement = &placement_memtype; 1237 1238 tmp_reg = *new_reg; 1239 tmp_reg.mm_node = NULL; 1240 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1241 if (ret) 1242 return ret; 1243 1244 ret = ttm_tt_bind(bo->ttm, &tmp_reg, &ctx); 1245 if (ret) 1246 goto out; 1247 1248 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_reg); 1249 if (ret) 1250 goto out; 1251 1252 ret = ttm_bo_move_ttm(bo, &ctx, new_reg); 1253 out: 1254 ttm_bo_mem_put(bo, &tmp_reg); 1255 return ret; 1256 } 1257 1258 static int 1259 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 1260 bool no_wait_gpu, struct ttm_mem_reg *new_reg) 1261 { 1262 struct ttm_operation_ctx ctx = { intr, no_wait_gpu }; 1263 struct ttm_place placement_memtype = { 1264 .fpfn = 0, 1265 .lpfn = 0, 1266 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING 1267 }; 1268 struct ttm_placement placement; 1269 struct ttm_mem_reg tmp_reg; 1270 int ret; 1271 1272 placement.num_placement = placement.num_busy_placement = 1; 1273 placement.placement = placement.busy_placement = &placement_memtype; 1274 1275 tmp_reg = *new_reg; 1276 tmp_reg.mm_node = NULL; 1277 ret = ttm_bo_mem_space(bo, &placement, &tmp_reg, &ctx); 1278 if (ret) 1279 return ret; 1280 1281 ret = ttm_bo_move_ttm(bo, &ctx, &tmp_reg); 1282 if (ret) 1283 goto out; 1284 1285 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_reg); 1286 if (ret) 1287 goto out; 1288 1289 out: 1290 ttm_bo_mem_put(bo, &tmp_reg); 1291 return ret; 1292 } 1293 1294 static void 1295 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, 1296 struct ttm_mem_reg *new_reg) 1297 { 1298 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 1299 struct nouveau_bo *nvbo = nouveau_bo(bo); 1300 struct nouveau_vma *vma; 1301 1302 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 1303 if (bo->destroy != nouveau_bo_del_ttm) 1304 return; 1305 1306 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 1307 mem->mem.page == nvbo->page) { 1308 list_for_each_entry(vma, &nvbo->vma_list, head) { 1309 nouveau_vma_map(vma, mem); 1310 } 1311 } else { 1312 list_for_each_entry(vma, &nvbo->vma_list, head) { 1313 WARN_ON(ttm_bo_wait(bo, false, false)); 1314 nouveau_vma_unmap(vma); 1315 } 1316 } 1317 1318 if (new_reg) { 1319 if (new_reg->mm_node) 1320 nvbo->offset = (new_reg->start << PAGE_SHIFT); 1321 else 1322 nvbo->offset = 0; 1323 } 1324 1325 } 1326 1327 static int 1328 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_reg, 1329 struct nouveau_drm_tile **new_tile) 1330 { 1331 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1332 struct drm_device *dev = drm->dev; 1333 struct nouveau_bo *nvbo = nouveau_bo(bo); 1334 u64 offset = new_reg->start << PAGE_SHIFT; 1335 1336 *new_tile = NULL; 1337 if (new_reg->mem_type != TTM_PL_VRAM) 1338 return 0; 1339 1340 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 1341 *new_tile = nv10_bo_set_tiling(dev, offset, new_reg->size, 1342 nvbo->mode, nvbo->zeta); 1343 } 1344 1345 return 0; 1346 } 1347 1348 static void 1349 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 1350 struct nouveau_drm_tile *new_tile, 1351 struct nouveau_drm_tile **old_tile) 1352 { 1353 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1354 struct drm_device *dev = drm->dev; 1355 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv); 1356 1357 nv10_bo_put_tile_region(dev, *old_tile, fence); 1358 *old_tile = new_tile; 1359 } 1360 1361 static int 1362 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 1363 struct ttm_operation_ctx *ctx, 1364 struct ttm_mem_reg *new_reg) 1365 { 1366 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1367 struct nouveau_bo *nvbo = nouveau_bo(bo); 1368 struct ttm_mem_reg *old_reg = &bo->mem; 1369 struct nouveau_drm_tile *new_tile = NULL; 1370 int ret = 0; 1371 1372 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1373 if (ret) 1374 return ret; 1375 1376 if (nvbo->pin_refcnt) 1377 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 1378 1379 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1380 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 1381 if (ret) 1382 return ret; 1383 } 1384 1385 /* Fake bo copy. */ 1386 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 1387 BUG_ON(bo->mem.mm_node != NULL); 1388 bo->mem = *new_reg; 1389 new_reg->mm_node = NULL; 1390 goto out; 1391 } 1392 1393 /* Hardware assisted copy. */ 1394 if (drm->ttm.move) { 1395 if (new_reg->mem_type == TTM_PL_SYSTEM) 1396 ret = nouveau_bo_move_flipd(bo, evict, 1397 ctx->interruptible, 1398 ctx->no_wait_gpu, new_reg); 1399 else if (old_reg->mem_type == TTM_PL_SYSTEM) 1400 ret = nouveau_bo_move_flips(bo, evict, 1401 ctx->interruptible, 1402 ctx->no_wait_gpu, new_reg); 1403 else 1404 ret = nouveau_bo_move_m2mf(bo, evict, 1405 ctx->interruptible, 1406 ctx->no_wait_gpu, new_reg); 1407 if (!ret) 1408 goto out; 1409 } 1410 1411 /* Fallback to software copy. */ 1412 ret = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 1413 if (ret == 0) 1414 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1415 1416 out: 1417 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1418 if (ret) 1419 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1420 else 1421 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1422 } 1423 1424 return ret; 1425 } 1426 1427 static int 1428 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 1429 { 1430 struct nouveau_bo *nvbo = nouveau_bo(bo); 1431 1432 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node, 1433 filp->private_data); 1434 } 1435 1436 static int 1437 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1438 { 1439 struct nouveau_drm *drm = nouveau_bdev(bdev); 1440 struct nvkm_device *device = nvxx_device(&drm->client.device); 1441 struct nouveau_mem *mem = nouveau_mem(reg); 1442 1443 reg->bus.addr = NULL; 1444 reg->bus.offset = 0; 1445 reg->bus.size = reg->num_pages << PAGE_SHIFT; 1446 reg->bus.base = 0; 1447 reg->bus.is_iomem = false; 1448 1449 switch (reg->mem_type) { 1450 case TTM_PL_SYSTEM: 1451 /* System memory */ 1452 return 0; 1453 case TTM_PL_TT: 1454 #if IS_ENABLED(CONFIG_AGP) 1455 if (drm->agp.bridge) { 1456 reg->bus.offset = reg->start << PAGE_SHIFT; 1457 reg->bus.base = drm->agp.base; 1458 reg->bus.is_iomem = !drm->agp.cma; 1459 } 1460 #endif 1461 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) 1462 /* untiled */ 1463 break; 1464 /* fall through - tiled memory */ 1465 case TTM_PL_VRAM: 1466 reg->bus.offset = reg->start << PAGE_SHIFT; 1467 reg->bus.base = device->func->resource_addr(device, 1); 1468 reg->bus.is_iomem = true; 1469 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1470 union { 1471 struct nv50_mem_map_v0 nv50; 1472 struct gf100_mem_map_v0 gf100; 1473 } args; 1474 u64 handle, length; 1475 u32 argc = 0; 1476 int ret; 1477 1478 switch (mem->mem.object.oclass) { 1479 case NVIF_CLASS_MEM_NV50: 1480 args.nv50.version = 0; 1481 args.nv50.ro = 0; 1482 args.nv50.kind = mem->kind; 1483 args.nv50.comp = mem->comp; 1484 argc = sizeof(args.nv50); 1485 break; 1486 case NVIF_CLASS_MEM_GF100: 1487 args.gf100.version = 0; 1488 args.gf100.ro = 0; 1489 args.gf100.kind = mem->kind; 1490 argc = sizeof(args.gf100); 1491 break; 1492 default: 1493 WARN_ON(1); 1494 break; 1495 } 1496 1497 ret = nvif_object_map_handle(&mem->mem.object, 1498 &args, argc, 1499 &handle, &length); 1500 if (ret != 1) { 1501 if (WARN_ON(ret == 0)) 1502 return -EINVAL; 1503 return ret; 1504 } 1505 1506 reg->bus.base = 0; 1507 reg->bus.offset = handle; 1508 } 1509 break; 1510 default: 1511 return -EINVAL; 1512 } 1513 return 0; 1514 } 1515 1516 static void 1517 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) 1518 { 1519 struct nouveau_drm *drm = nouveau_bdev(bdev); 1520 struct nouveau_mem *mem = nouveau_mem(reg); 1521 1522 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1523 switch (reg->mem_type) { 1524 case TTM_PL_TT: 1525 if (mem->kind) 1526 nvif_object_unmap_handle(&mem->mem.object); 1527 break; 1528 case TTM_PL_VRAM: 1529 nvif_object_unmap_handle(&mem->mem.object); 1530 break; 1531 default: 1532 break; 1533 } 1534 } 1535 } 1536 1537 static int 1538 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1539 { 1540 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1541 struct nouveau_bo *nvbo = nouveau_bo(bo); 1542 struct nvkm_device *device = nvxx_device(&drm->client.device); 1543 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1544 int i, ret; 1545 1546 /* as long as the bo isn't in vram, and isn't tiled, we've got 1547 * nothing to do here. 1548 */ 1549 if (bo->mem.mem_type != TTM_PL_VRAM) { 1550 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1551 !nvbo->kind) 1552 return 0; 1553 1554 if (bo->mem.mem_type == TTM_PL_SYSTEM) { 1555 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); 1556 1557 ret = nouveau_bo_validate(nvbo, false, false); 1558 if (ret) 1559 return ret; 1560 } 1561 return 0; 1562 } 1563 1564 /* make sure bo is in mappable vram */ 1565 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1566 bo->mem.start + bo->mem.num_pages < mappable) 1567 return 0; 1568 1569 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1570 nvbo->placements[i].fpfn = 0; 1571 nvbo->placements[i].lpfn = mappable; 1572 } 1573 1574 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1575 nvbo->busy_placements[i].fpfn = 0; 1576 nvbo->busy_placements[i].lpfn = mappable; 1577 } 1578 1579 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); 1580 return nouveau_bo_validate(nvbo, false, false); 1581 } 1582 1583 static int 1584 nouveau_ttm_tt_populate(struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1585 { 1586 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1587 struct nouveau_drm *drm; 1588 struct device *dev; 1589 unsigned i; 1590 int r; 1591 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1592 1593 if (ttm->state != tt_unpopulated) 1594 return 0; 1595 1596 if (slave && ttm->sg) { 1597 /* make userspace faulting work */ 1598 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 1599 ttm_dma->dma_address, ttm->num_pages); 1600 ttm->state = tt_unbound; 1601 return 0; 1602 } 1603 1604 drm = nouveau_bdev(ttm->bdev); 1605 dev = drm->dev->dev; 1606 1607 #if IS_ENABLED(CONFIG_AGP) 1608 if (drm->agp.bridge) { 1609 return ttm_agp_tt_populate(ttm, ctx); 1610 } 1611 #endif 1612 1613 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1614 if (swiotlb_nr_tbl()) { 1615 return ttm_dma_populate((void *)ttm, dev, ctx); 1616 } 1617 #endif 1618 1619 r = ttm_pool_populate(ttm, ctx); 1620 if (r) { 1621 return r; 1622 } 1623 1624 for (i = 0; i < ttm->num_pages; i++) { 1625 dma_addr_t addr; 1626 1627 addr = dma_map_page(dev, ttm->pages[i], 0, PAGE_SIZE, 1628 DMA_BIDIRECTIONAL); 1629 1630 if (dma_mapping_error(dev, addr)) { 1631 while (i--) { 1632 dma_unmap_page(dev, ttm_dma->dma_address[i], 1633 PAGE_SIZE, DMA_BIDIRECTIONAL); 1634 ttm_dma->dma_address[i] = 0; 1635 } 1636 ttm_pool_unpopulate(ttm); 1637 return -EFAULT; 1638 } 1639 1640 ttm_dma->dma_address[i] = addr; 1641 } 1642 return 0; 1643 } 1644 1645 static void 1646 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) 1647 { 1648 struct ttm_dma_tt *ttm_dma = (void *)ttm; 1649 struct nouveau_drm *drm; 1650 struct device *dev; 1651 unsigned i; 1652 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1653 1654 if (slave) 1655 return; 1656 1657 drm = nouveau_bdev(ttm->bdev); 1658 dev = drm->dev->dev; 1659 1660 #if IS_ENABLED(CONFIG_AGP) 1661 if (drm->agp.bridge) { 1662 ttm_agp_tt_unpopulate(ttm); 1663 return; 1664 } 1665 #endif 1666 1667 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86) 1668 if (swiotlb_nr_tbl()) { 1669 ttm_dma_unpopulate((void *)ttm, dev); 1670 return; 1671 } 1672 #endif 1673 1674 for (i = 0; i < ttm->num_pages; i++) { 1675 if (ttm_dma->dma_address[i]) { 1676 dma_unmap_page(dev, ttm_dma->dma_address[i], PAGE_SIZE, 1677 DMA_BIDIRECTIONAL); 1678 } 1679 } 1680 1681 ttm_pool_unpopulate(ttm); 1682 } 1683 1684 void 1685 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1686 { 1687 struct dma_resv *resv = nvbo->bo.base.resv; 1688 1689 if (exclusive) 1690 dma_resv_add_excl_fence(resv, &fence->base); 1691 else if (fence) 1692 dma_resv_add_shared_fence(resv, &fence->base); 1693 } 1694 1695 struct ttm_bo_driver nouveau_bo_driver = { 1696 .ttm_tt_create = &nouveau_ttm_tt_create, 1697 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1698 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1699 .init_mem_type = nouveau_bo_init_mem_type, 1700 .eviction_valuable = ttm_bo_eviction_valuable, 1701 .evict_flags = nouveau_bo_evict_flags, 1702 .move_notify = nouveau_bo_move_ntfy, 1703 .move = nouveau_bo_move, 1704 .verify_access = nouveau_bo_verify_access, 1705 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, 1706 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1707 .io_mem_free = &nouveau_ttm_io_mem_free, 1708 }; 1709