1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include "drmP.h" 31 32 #include "nouveau_drm.h" 33 #include "nouveau_drv.h" 34 #include "nouveau_dma.h" 35 36 #include <linux/log2.h> 37 #include <linux/slab.h> 38 39 static void 40 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 41 { 42 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 43 struct drm_device *dev = dev_priv->dev; 44 struct nouveau_bo *nvbo = nouveau_bo(bo); 45 46 ttm_bo_kunmap(&nvbo->kmap); 47 48 if (unlikely(nvbo->gem)) 49 DRM_ERROR("bo %p still attached to GEM object\n", bo); 50 51 if (nvbo->tile) 52 nv10_mem_expire_tiling(dev, nvbo->tile, NULL); 53 54 spin_lock(&dev_priv->ttm.bo_list_lock); 55 list_del(&nvbo->head); 56 spin_unlock(&dev_priv->ttm.bo_list_lock); 57 kfree(nvbo); 58 } 59 60 static void 61 nouveau_bo_fixup_align(struct drm_device *dev, 62 uint32_t tile_mode, uint32_t tile_flags, 63 int *align, int *size) 64 { 65 struct drm_nouveau_private *dev_priv = dev->dev_private; 66 67 /* 68 * Some of the tile_flags have a periodic structure of N*4096 bytes, 69 * align to to that as well as the page size. Align the size to the 70 * appropriate boundaries. This does imply that sizes are rounded up 71 * 3-7 pages, so be aware of this and do not waste memory by allocating 72 * many small buffers. 73 */ 74 if (dev_priv->card_type == NV_50) { 75 uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15; 76 int i; 77 78 switch (tile_flags) { 79 case 0x1800: 80 case 0x2800: 81 case 0x4800: 82 case 0x7a00: 83 if (is_power_of_2(block_size)) { 84 for (i = 1; i < 10; i++) { 85 *align = 12 * i * block_size; 86 if (!(*align % 65536)) 87 break; 88 } 89 } else { 90 for (i = 1; i < 10; i++) { 91 *align = 8 * i * block_size; 92 if (!(*align % 65536)) 93 break; 94 } 95 } 96 *size = roundup(*size, *align); 97 break; 98 default: 99 break; 100 } 101 102 } else { 103 if (tile_mode) { 104 if (dev_priv->chipset >= 0x40) { 105 *align = 65536; 106 *size = roundup(*size, 64 * tile_mode); 107 108 } else if (dev_priv->chipset >= 0x30) { 109 *align = 32768; 110 *size = roundup(*size, 64 * tile_mode); 111 112 } else if (dev_priv->chipset >= 0x20) { 113 *align = 16384; 114 *size = roundup(*size, 64 * tile_mode); 115 116 } else if (dev_priv->chipset >= 0x10) { 117 *align = 16384; 118 *size = roundup(*size, 32 * tile_mode); 119 } 120 } 121 } 122 123 /* ALIGN works only on powers of two. */ 124 *size = roundup(*size, PAGE_SIZE); 125 126 if (dev_priv->card_type == NV_50) { 127 *size = roundup(*size, 65536); 128 *align = max(65536, *align); 129 } 130 } 131 132 int 133 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, 134 int size, int align, uint32_t flags, uint32_t tile_mode, 135 uint32_t tile_flags, bool no_vm, bool mappable, 136 struct nouveau_bo **pnvbo) 137 { 138 struct drm_nouveau_private *dev_priv = dev->dev_private; 139 struct nouveau_bo *nvbo; 140 int ret = 0; 141 142 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 143 if (!nvbo) 144 return -ENOMEM; 145 INIT_LIST_HEAD(&nvbo->head); 146 INIT_LIST_HEAD(&nvbo->entry); 147 nvbo->mappable = mappable; 148 nvbo->no_vm = no_vm; 149 nvbo->tile_mode = tile_mode; 150 nvbo->tile_flags = tile_flags; 151 152 nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size); 153 align >>= PAGE_SHIFT; 154 155 nvbo->placement.fpfn = 0; 156 nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; 157 nouveau_bo_placement_set(nvbo, flags); 158 159 nvbo->channel = chan; 160 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, 161 ttm_bo_type_device, &nvbo->placement, align, 0, 162 false, NULL, size, nouveau_bo_del_ttm); 163 nvbo->channel = NULL; 164 if (ret) { 165 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 166 return ret; 167 } 168 169 spin_lock(&dev_priv->ttm.bo_list_lock); 170 list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list); 171 spin_unlock(&dev_priv->ttm.bo_list_lock); 172 *pnvbo = nvbo; 173 return 0; 174 } 175 176 void 177 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype) 178 { 179 int n = 0; 180 181 if (memtype & TTM_PL_FLAG_VRAM) 182 nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING; 183 if (memtype & TTM_PL_FLAG_TT) 184 nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; 185 if (memtype & TTM_PL_FLAG_SYSTEM) 186 nvbo->placements[n++] = TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; 187 nvbo->placement.placement = nvbo->placements; 188 nvbo->placement.busy_placement = nvbo->placements; 189 nvbo->placement.num_placement = n; 190 nvbo->placement.num_busy_placement = n; 191 192 if (nvbo->pin_refcnt) { 193 while (n--) 194 nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT; 195 } 196 } 197 198 int 199 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) 200 { 201 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); 202 struct ttm_buffer_object *bo = &nvbo->bo; 203 int ret, i; 204 205 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { 206 NV_ERROR(nouveau_bdev(bo->bdev)->dev, 207 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, 208 1 << bo->mem.mem_type, memtype); 209 return -EINVAL; 210 } 211 212 if (nvbo->pin_refcnt++) 213 return 0; 214 215 ret = ttm_bo_reserve(bo, false, false, false, 0); 216 if (ret) 217 goto out; 218 219 nouveau_bo_placement_set(nvbo, memtype); 220 for (i = 0; i < nvbo->placement.num_placement; i++) 221 nvbo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 222 223 ret = ttm_bo_validate(bo, &nvbo->placement, false, false); 224 if (ret == 0) { 225 switch (bo->mem.mem_type) { 226 case TTM_PL_VRAM: 227 dev_priv->fb_aper_free -= bo->mem.size; 228 break; 229 case TTM_PL_TT: 230 dev_priv->gart_info.aper_free -= bo->mem.size; 231 break; 232 default: 233 break; 234 } 235 } 236 ttm_bo_unreserve(bo); 237 out: 238 if (unlikely(ret)) 239 nvbo->pin_refcnt--; 240 return ret; 241 } 242 243 int 244 nouveau_bo_unpin(struct nouveau_bo *nvbo) 245 { 246 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); 247 struct ttm_buffer_object *bo = &nvbo->bo; 248 int ret, i; 249 250 if (--nvbo->pin_refcnt) 251 return 0; 252 253 ret = ttm_bo_reserve(bo, false, false, false, 0); 254 if (ret) 255 return ret; 256 257 for (i = 0; i < nvbo->placement.num_placement; i++) 258 nvbo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 259 260 ret = ttm_bo_validate(bo, &nvbo->placement, false, false); 261 if (ret == 0) { 262 switch (bo->mem.mem_type) { 263 case TTM_PL_VRAM: 264 dev_priv->fb_aper_free += bo->mem.size; 265 break; 266 case TTM_PL_TT: 267 dev_priv->gart_info.aper_free += bo->mem.size; 268 break; 269 default: 270 break; 271 } 272 } 273 274 ttm_bo_unreserve(bo); 275 return ret; 276 } 277 278 int 279 nouveau_bo_map(struct nouveau_bo *nvbo) 280 { 281 int ret; 282 283 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0); 284 if (ret) 285 return ret; 286 287 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 288 ttm_bo_unreserve(&nvbo->bo); 289 return ret; 290 } 291 292 void 293 nouveau_bo_unmap(struct nouveau_bo *nvbo) 294 { 295 ttm_bo_kunmap(&nvbo->kmap); 296 } 297 298 u16 299 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) 300 { 301 bool is_iomem; 302 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 303 mem = &mem[index]; 304 if (is_iomem) 305 return ioread16_native((void __force __iomem *)mem); 306 else 307 return *mem; 308 } 309 310 void 311 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 312 { 313 bool is_iomem; 314 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 315 mem = &mem[index]; 316 if (is_iomem) 317 iowrite16_native(val, (void __force __iomem *)mem); 318 else 319 *mem = val; 320 } 321 322 u32 323 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 324 { 325 bool is_iomem; 326 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 327 mem = &mem[index]; 328 if (is_iomem) 329 return ioread32_native((void __force __iomem *)mem); 330 else 331 return *mem; 332 } 333 334 void 335 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 336 { 337 bool is_iomem; 338 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 339 mem = &mem[index]; 340 if (is_iomem) 341 iowrite32_native(val, (void __force __iomem *)mem); 342 else 343 *mem = val; 344 } 345 346 static struct ttm_backend * 347 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) 348 { 349 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); 350 struct drm_device *dev = dev_priv->dev; 351 352 switch (dev_priv->gart_info.type) { 353 #if __OS_HAS_AGP 354 case NOUVEAU_GART_AGP: 355 return ttm_agp_backend_init(bdev, dev->agp->bridge); 356 #endif 357 case NOUVEAU_GART_SGDMA: 358 return nouveau_sgdma_init_ttm(dev); 359 default: 360 NV_ERROR(dev, "Unknown GART type %d\n", 361 dev_priv->gart_info.type); 362 break; 363 } 364 365 return NULL; 366 } 367 368 static int 369 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 370 { 371 /* We'll do this from user space. */ 372 return 0; 373 } 374 375 static int 376 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 377 struct ttm_mem_type_manager *man) 378 { 379 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); 380 struct drm_device *dev = dev_priv->dev; 381 382 switch (type) { 383 case TTM_PL_SYSTEM: 384 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 385 man->available_caching = TTM_PL_MASK_CACHING; 386 man->default_caching = TTM_PL_FLAG_CACHED; 387 break; 388 case TTM_PL_VRAM: 389 man->flags = TTM_MEMTYPE_FLAG_FIXED | 390 TTM_MEMTYPE_FLAG_MAPPABLE | 391 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; 392 man->available_caching = TTM_PL_FLAG_UNCACHED | 393 TTM_PL_FLAG_WC; 394 man->default_caching = TTM_PL_FLAG_WC; 395 396 man->io_addr = NULL; 397 man->io_offset = drm_get_resource_start(dev, 1); 398 man->io_size = drm_get_resource_len(dev, 1); 399 if (man->io_size > nouveau_mem_fb_amount(dev)) 400 man->io_size = nouveau_mem_fb_amount(dev); 401 402 man->gpu_offset = dev_priv->vm_vram_base; 403 break; 404 case TTM_PL_TT: 405 switch (dev_priv->gart_info.type) { 406 case NOUVEAU_GART_AGP: 407 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | 408 TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; 409 man->available_caching = TTM_PL_FLAG_UNCACHED; 410 man->default_caching = TTM_PL_FLAG_UNCACHED; 411 break; 412 case NOUVEAU_GART_SGDMA: 413 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | 414 TTM_MEMTYPE_FLAG_CMA; 415 man->available_caching = TTM_PL_MASK_CACHING; 416 man->default_caching = TTM_PL_FLAG_CACHED; 417 break; 418 default: 419 NV_ERROR(dev, "Unknown GART type: %d\n", 420 dev_priv->gart_info.type); 421 return -EINVAL; 422 } 423 424 man->io_offset = dev_priv->gart_info.aper_base; 425 man->io_size = dev_priv->gart_info.aper_size; 426 man->io_addr = NULL; 427 man->gpu_offset = dev_priv->vm_gart_base; 428 break; 429 default: 430 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type); 431 return -EINVAL; 432 } 433 return 0; 434 } 435 436 static void 437 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 438 { 439 struct nouveau_bo *nvbo = nouveau_bo(bo); 440 441 switch (bo->mem.mem_type) { 442 case TTM_PL_VRAM: 443 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT); 444 break; 445 default: 446 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); 447 break; 448 } 449 450 *pl = nvbo->placement; 451 } 452 453 454 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access 455 * TTM_PL_{VRAM,TT} directly. 456 */ 457 458 static int 459 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, 460 struct nouveau_bo *nvbo, bool evict, bool no_wait, 461 struct ttm_mem_reg *new_mem) 462 { 463 struct nouveau_fence *fence = NULL; 464 int ret; 465 466 ret = nouveau_fence_new(chan, &fence, true); 467 if (ret) 468 return ret; 469 470 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, 471 evict, no_wait, new_mem); 472 if (nvbo->channel && nvbo->channel != chan) 473 ret = nouveau_fence_wait(fence, NULL, false, false); 474 nouveau_fence_unref((void *)&fence); 475 return ret; 476 } 477 478 static inline uint32_t 479 nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan, 480 struct ttm_mem_reg *mem) 481 { 482 if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) { 483 if (mem->mem_type == TTM_PL_TT) 484 return NvDmaGART; 485 return NvDmaVRAM; 486 } 487 488 if (mem->mem_type == TTM_PL_TT) 489 return chan->gart_handle; 490 return chan->vram_handle; 491 } 492 493 static int 494 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, 495 int no_wait, struct ttm_mem_reg *new_mem) 496 { 497 struct nouveau_bo *nvbo = nouveau_bo(bo); 498 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 499 struct ttm_mem_reg *old_mem = &bo->mem; 500 struct nouveau_channel *chan; 501 uint64_t src_offset, dst_offset; 502 uint32_t page_count; 503 int ret; 504 505 chan = nvbo->channel; 506 if (!chan || nvbo->tile_flags || nvbo->no_vm) 507 chan = dev_priv->channel; 508 509 src_offset = old_mem->mm_node->start << PAGE_SHIFT; 510 dst_offset = new_mem->mm_node->start << PAGE_SHIFT; 511 if (chan != dev_priv->channel) { 512 if (old_mem->mem_type == TTM_PL_TT) 513 src_offset += dev_priv->vm_gart_base; 514 else 515 src_offset += dev_priv->vm_vram_base; 516 517 if (new_mem->mem_type == TTM_PL_TT) 518 dst_offset += dev_priv->vm_gart_base; 519 else 520 dst_offset += dev_priv->vm_vram_base; 521 } 522 523 ret = RING_SPACE(chan, 3); 524 if (ret) 525 return ret; 526 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); 527 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem)); 528 OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem)); 529 530 if (dev_priv->card_type >= NV_50) { 531 ret = RING_SPACE(chan, 4); 532 if (ret) 533 return ret; 534 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); 535 OUT_RING(chan, 1); 536 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1); 537 OUT_RING(chan, 1); 538 } 539 540 page_count = new_mem->num_pages; 541 while (page_count) { 542 int line_count = (page_count > 2047) ? 2047 : page_count; 543 544 if (dev_priv->card_type >= NV_50) { 545 ret = RING_SPACE(chan, 3); 546 if (ret) 547 return ret; 548 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2); 549 OUT_RING(chan, upper_32_bits(src_offset)); 550 OUT_RING(chan, upper_32_bits(dst_offset)); 551 } 552 ret = RING_SPACE(chan, 11); 553 if (ret) 554 return ret; 555 BEGIN_RING(chan, NvSubM2MF, 556 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); 557 OUT_RING(chan, lower_32_bits(src_offset)); 558 OUT_RING(chan, lower_32_bits(dst_offset)); 559 OUT_RING(chan, PAGE_SIZE); /* src_pitch */ 560 OUT_RING(chan, PAGE_SIZE); /* dst_pitch */ 561 OUT_RING(chan, PAGE_SIZE); /* line_length */ 562 OUT_RING(chan, line_count); 563 OUT_RING(chan, (1<<8)|(1<<0)); 564 OUT_RING(chan, 0); 565 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); 566 OUT_RING(chan, 0); 567 568 page_count -= line_count; 569 src_offset += (PAGE_SIZE * line_count); 570 dst_offset += (PAGE_SIZE * line_count); 571 } 572 573 return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait, new_mem); 574 } 575 576 static int 577 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, 578 bool no_wait, struct ttm_mem_reg *new_mem) 579 { 580 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; 581 struct ttm_placement placement; 582 struct ttm_mem_reg tmp_mem; 583 int ret; 584 585 placement.fpfn = placement.lpfn = 0; 586 placement.num_placement = placement.num_busy_placement = 1; 587 placement.placement = placement.busy_placement = &placement_memtype; 588 589 tmp_mem = *new_mem; 590 tmp_mem.mm_node = NULL; 591 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait); 592 if (ret) 593 return ret; 594 595 ret = ttm_tt_bind(bo->ttm, &tmp_mem); 596 if (ret) 597 goto out; 598 599 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem); 600 if (ret) 601 goto out; 602 603 ret = ttm_bo_move_ttm(bo, evict, no_wait, new_mem); 604 out: 605 if (tmp_mem.mm_node) { 606 spin_lock(&bo->bdev->glob->lru_lock); 607 drm_mm_put_block(tmp_mem.mm_node); 608 spin_unlock(&bo->bdev->glob->lru_lock); 609 } 610 611 return ret; 612 } 613 614 static int 615 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, 616 bool no_wait, struct ttm_mem_reg *new_mem) 617 { 618 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; 619 struct ttm_placement placement; 620 struct ttm_mem_reg tmp_mem; 621 int ret; 622 623 placement.fpfn = placement.lpfn = 0; 624 placement.num_placement = placement.num_busy_placement = 1; 625 placement.placement = placement.busy_placement = &placement_memtype; 626 627 tmp_mem = *new_mem; 628 tmp_mem.mm_node = NULL; 629 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait); 630 if (ret) 631 return ret; 632 633 ret = ttm_bo_move_ttm(bo, evict, no_wait, &tmp_mem); 634 if (ret) 635 goto out; 636 637 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem); 638 if (ret) 639 goto out; 640 641 out: 642 if (tmp_mem.mm_node) { 643 spin_lock(&bo->bdev->glob->lru_lock); 644 drm_mm_put_block(tmp_mem.mm_node); 645 spin_unlock(&bo->bdev->glob->lru_lock); 646 } 647 648 return ret; 649 } 650 651 static int 652 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, 653 struct nouveau_tile_reg **new_tile) 654 { 655 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 656 struct drm_device *dev = dev_priv->dev; 657 struct nouveau_bo *nvbo = nouveau_bo(bo); 658 uint64_t offset; 659 int ret; 660 661 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) { 662 /* Nothing to do. */ 663 *new_tile = NULL; 664 return 0; 665 } 666 667 offset = new_mem->mm_node->start << PAGE_SHIFT; 668 669 if (dev_priv->card_type == NV_50) { 670 ret = nv50_mem_vm_bind_linear(dev, 671 offset + dev_priv->vm_vram_base, 672 new_mem->size, nvbo->tile_flags, 673 offset); 674 if (ret) 675 return ret; 676 677 } else if (dev_priv->card_type >= NV_10) { 678 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, 679 nvbo->tile_mode); 680 } 681 682 return 0; 683 } 684 685 static void 686 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 687 struct nouveau_tile_reg *new_tile, 688 struct nouveau_tile_reg **old_tile) 689 { 690 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 691 struct drm_device *dev = dev_priv->dev; 692 693 if (dev_priv->card_type >= NV_10 && 694 dev_priv->card_type < NV_50) { 695 if (*old_tile) 696 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj); 697 698 *old_tile = new_tile; 699 } 700 } 701 702 static int 703 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, 704 bool no_wait, struct ttm_mem_reg *new_mem) 705 { 706 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); 707 struct nouveau_bo *nvbo = nouveau_bo(bo); 708 struct ttm_mem_reg *old_mem = &bo->mem; 709 struct nouveau_tile_reg *new_tile = NULL; 710 int ret = 0; 711 712 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); 713 if (ret) 714 return ret; 715 716 /* Software copy if the card isn't up and running yet. */ 717 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE || 718 !dev_priv->channel) { 719 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 720 goto out; 721 } 722 723 /* Fake bo copy. */ 724 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 725 BUG_ON(bo->mem.mm_node != NULL); 726 bo->mem = *new_mem; 727 new_mem->mm_node = NULL; 728 goto out; 729 } 730 731 /* Hardware assisted copy. */ 732 if (new_mem->mem_type == TTM_PL_SYSTEM) 733 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem); 734 else if (old_mem->mem_type == TTM_PL_SYSTEM) 735 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem); 736 else 737 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem); 738 739 if (!ret) 740 goto out; 741 742 /* Fallback to software copy. */ 743 ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); 744 745 out: 746 if (ret) 747 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 748 else 749 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 750 751 return ret; 752 } 753 754 static int 755 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 756 { 757 return 0; 758 } 759 760 struct ttm_bo_driver nouveau_bo_driver = { 761 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry, 762 .invalidate_caches = nouveau_bo_invalidate_caches, 763 .init_mem_type = nouveau_bo_init_mem_type, 764 .evict_flags = nouveau_bo_evict_flags, 765 .move = nouveau_bo_move, 766 .verify_access = nouveau_bo_verify_access, 767 .sync_obj_signaled = nouveau_fence_signalled, 768 .sync_obj_wait = nouveau_fence_wait, 769 .sync_obj_flush = nouveau_fence_flush, 770 .sync_obj_unref = nouveau_fence_unref, 771 .sync_obj_ref = nouveau_fence_ref, 772 }; 773 774