1 /* 2 * Copyright 2007 Dave Airlied 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 /* 25 * Authors: Dave Airlied <airlied@linux.ie> 26 * Ben Skeggs <darktama@iinet.net.au> 27 * Jeremy Kolb <jkolb@brandeis.edu> 28 */ 29 30 #include <linux/dma-mapping.h> 31 32 #include "nouveau_drv.h" 33 #include "nouveau_chan.h" 34 #include "nouveau_fence.h" 35 36 #include "nouveau_bo.h" 37 #include "nouveau_ttm.h" 38 #include "nouveau_gem.h" 39 #include "nouveau_mem.h" 40 #include "nouveau_vmm.h" 41 42 #include <nvif/class.h> 43 #include <nvif/if500b.h> 44 #include <nvif/if900b.h> 45 46 static int nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm, 47 struct ttm_resource *reg); 48 static void nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm); 49 50 /* 51 * NV10-NV40 tiling helpers 52 */ 53 54 static void 55 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 56 u32 addr, u32 size, u32 pitch, u32 flags) 57 { 58 struct nouveau_drm *drm = nouveau_drm(dev); 59 int i = reg - drm->tile.reg; 60 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 61 struct nvkm_fb_tile *tile = &fb->tile.region[i]; 62 63 nouveau_fence_unref(®->fence); 64 65 if (tile->pitch) 66 nvkm_fb_tile_fini(fb, i, tile); 67 68 if (pitch) 69 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); 70 71 nvkm_fb_tile_prog(fb, i, tile); 72 } 73 74 static struct nouveau_drm_tile * 75 nv10_bo_get_tile_region(struct drm_device *dev, int i) 76 { 77 struct nouveau_drm *drm = nouveau_drm(dev); 78 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 79 80 spin_lock(&drm->tile.lock); 81 82 if (!tile->used && 83 (!tile->fence || nouveau_fence_done(tile->fence))) 84 tile->used = true; 85 else 86 tile = NULL; 87 88 spin_unlock(&drm->tile.lock); 89 return tile; 90 } 91 92 static void 93 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 94 struct dma_fence *fence) 95 { 96 struct nouveau_drm *drm = nouveau_drm(dev); 97 98 if (tile) { 99 spin_lock(&drm->tile.lock); 100 tile->fence = (struct nouveau_fence *)dma_fence_get(fence); 101 tile->used = false; 102 spin_unlock(&drm->tile.lock); 103 } 104 } 105 106 static struct nouveau_drm_tile * 107 nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 108 u32 size, u32 pitch, u32 zeta) 109 { 110 struct nouveau_drm *drm = nouveau_drm(dev); 111 struct nvkm_fb *fb = nvxx_fb(&drm->client.device); 112 struct nouveau_drm_tile *tile, *found = NULL; 113 int i; 114 115 for (i = 0; i < fb->tile.regions; i++) { 116 tile = nv10_bo_get_tile_region(dev, i); 117 118 if (pitch && !found) { 119 found = tile; 120 continue; 121 122 } else if (tile && fb->tile.region[i].pitch) { 123 /* Kill an unused tile region. */ 124 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); 125 } 126 127 nv10_bo_put_tile_region(dev, tile, NULL); 128 } 129 130 if (found) 131 nv10_bo_update_tile_region(dev, found, addr, size, pitch, zeta); 132 return found; 133 } 134 135 static void 136 nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 137 { 138 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 139 struct drm_device *dev = drm->dev; 140 struct nouveau_bo *nvbo = nouveau_bo(bo); 141 142 WARN_ON(nvbo->bo.pin_count > 0); 143 nouveau_bo_del_io_reserve_lru(bo); 144 nv10_bo_put_tile_region(dev, nvbo->tile, NULL); 145 146 /* 147 * If nouveau_bo_new() allocated this buffer, the GEM object was never 148 * initialized, so don't attempt to release it. 149 */ 150 if (bo->base.dev) 151 drm_gem_object_release(&bo->base); 152 153 kfree(nvbo); 154 } 155 156 static inline u64 157 roundup_64(u64 x, u32 y) 158 { 159 x += y - 1; 160 do_div(x, y); 161 return x * y; 162 } 163 164 static void 165 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, int *align, u64 *size) 166 { 167 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 168 struct nvif_device *device = &drm->client.device; 169 170 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { 171 if (nvbo->mode) { 172 if (device->info.chipset >= 0x40) { 173 *align = 65536; 174 *size = roundup_64(*size, 64 * nvbo->mode); 175 176 } else if (device->info.chipset >= 0x30) { 177 *align = 32768; 178 *size = roundup_64(*size, 64 * nvbo->mode); 179 180 } else if (device->info.chipset >= 0x20) { 181 *align = 16384; 182 *size = roundup_64(*size, 64 * nvbo->mode); 183 184 } else if (device->info.chipset >= 0x10) { 185 *align = 16384; 186 *size = roundup_64(*size, 32 * nvbo->mode); 187 } 188 } 189 } else { 190 *size = roundup_64(*size, (1 << nvbo->page)); 191 *align = max((1 << nvbo->page), *align); 192 } 193 194 *size = roundup_64(*size, PAGE_SIZE); 195 } 196 197 struct nouveau_bo * 198 nouveau_bo_alloc(struct nouveau_cli *cli, u64 *size, int *align, u32 domain, 199 u32 tile_mode, u32 tile_flags) 200 { 201 struct nouveau_drm *drm = cli->drm; 202 struct nouveau_bo *nvbo; 203 struct nvif_mmu *mmu = &cli->mmu; 204 struct nvif_vmm *vmm = cli->svm.cli ? &cli->svm.vmm : &cli->vmm.vmm; 205 int i, pi = -1; 206 207 if (!*size) { 208 NV_WARN(drm, "skipped size %016llx\n", *size); 209 return ERR_PTR(-EINVAL); 210 } 211 212 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); 213 if (!nvbo) 214 return ERR_PTR(-ENOMEM); 215 INIT_LIST_HEAD(&nvbo->head); 216 INIT_LIST_HEAD(&nvbo->entry); 217 INIT_LIST_HEAD(&nvbo->vma_list); 218 nvbo->bo.bdev = &drm->ttm.bdev; 219 220 /* This is confusing, and doesn't actually mean we want an uncached 221 * mapping, but is what NOUVEAU_GEM_DOMAIN_COHERENT gets translated 222 * into in nouveau_gem_new(). 223 */ 224 if (domain & NOUVEAU_GEM_DOMAIN_COHERENT) { 225 /* Determine if we can get a cache-coherent map, forcing 226 * uncached mapping if we can't. 227 */ 228 if (!nouveau_drm_use_coherent_gpu_mapping(drm)) 229 nvbo->force_coherent = true; 230 } 231 232 if (cli->device.info.family >= NV_DEVICE_INFO_V0_FERMI) { 233 nvbo->kind = (tile_flags & 0x0000ff00) >> 8; 234 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 235 kfree(nvbo); 236 return ERR_PTR(-EINVAL); 237 } 238 239 nvbo->comp = mmu->kind[nvbo->kind] != nvbo->kind; 240 } else 241 if (cli->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 242 nvbo->kind = (tile_flags & 0x00007f00) >> 8; 243 nvbo->comp = (tile_flags & 0x00030000) >> 16; 244 if (!nvif_mmu_kind_valid(mmu, nvbo->kind)) { 245 kfree(nvbo); 246 return ERR_PTR(-EINVAL); 247 } 248 } else { 249 nvbo->zeta = (tile_flags & 0x00000007); 250 } 251 nvbo->mode = tile_mode; 252 nvbo->contig = !(tile_flags & NOUVEAU_GEM_TILE_NONCONTIG); 253 254 /* Determine the desirable target GPU page size for the buffer. */ 255 for (i = 0; i < vmm->page_nr; i++) { 256 /* Because we cannot currently allow VMM maps to fail 257 * during buffer migration, we need to determine page 258 * size for the buffer up-front, and pre-allocate its 259 * page tables. 260 * 261 * Skip page sizes that can't support needed domains. 262 */ 263 if (cli->device.info.family > NV_DEVICE_INFO_V0_CURIE && 264 (domain & NOUVEAU_GEM_DOMAIN_VRAM) && !vmm->page[i].vram) 265 continue; 266 if ((domain & NOUVEAU_GEM_DOMAIN_GART) && 267 (!vmm->page[i].host || vmm->page[i].shift > PAGE_SHIFT)) 268 continue; 269 270 /* Select this page size if it's the first that supports 271 * the potential memory domains, or when it's compatible 272 * with the requested compression settings. 273 */ 274 if (pi < 0 || !nvbo->comp || vmm->page[i].comp) 275 pi = i; 276 277 /* Stop once the buffer is larger than the current page size. */ 278 if (*size >= 1ULL << vmm->page[i].shift) 279 break; 280 } 281 282 if (WARN_ON(pi < 0)) 283 return ERR_PTR(-EINVAL); 284 285 /* Disable compression if suitable settings couldn't be found. */ 286 if (nvbo->comp && !vmm->page[pi].comp) { 287 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) 288 nvbo->kind = mmu->kind[nvbo->kind]; 289 nvbo->comp = 0; 290 } 291 nvbo->page = vmm->page[pi].shift; 292 293 nouveau_bo_fixup_align(nvbo, align, size); 294 295 return nvbo; 296 } 297 298 int 299 nouveau_bo_init(struct nouveau_bo *nvbo, u64 size, int align, u32 domain, 300 struct sg_table *sg, struct dma_resv *robj) 301 { 302 int type = sg ? ttm_bo_type_sg : ttm_bo_type_device; 303 size_t acc_size; 304 int ret; 305 306 acc_size = ttm_bo_dma_acc_size(nvbo->bo.bdev, size, sizeof(*nvbo)); 307 308 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; 309 nouveau_bo_placement_set(nvbo, domain, 0); 310 INIT_LIST_HEAD(&nvbo->io_reserve_lru); 311 312 ret = ttm_bo_init(nvbo->bo.bdev, &nvbo->bo, size, type, 313 &nvbo->placement, align >> PAGE_SHIFT, false, 314 acc_size, sg, robj, nouveau_bo_del_ttm); 315 if (ret) { 316 /* ttm will call nouveau_bo_del_ttm if it fails.. */ 317 return ret; 318 } 319 320 return 0; 321 } 322 323 int 324 nouveau_bo_new(struct nouveau_cli *cli, u64 size, int align, 325 uint32_t domain, uint32_t tile_mode, uint32_t tile_flags, 326 struct sg_table *sg, struct dma_resv *robj, 327 struct nouveau_bo **pnvbo) 328 { 329 struct nouveau_bo *nvbo; 330 int ret; 331 332 nvbo = nouveau_bo_alloc(cli, &size, &align, domain, tile_mode, 333 tile_flags); 334 if (IS_ERR(nvbo)) 335 return PTR_ERR(nvbo); 336 337 ret = nouveau_bo_init(nvbo, size, align, domain, sg, robj); 338 if (ret) 339 return ret; 340 341 *pnvbo = nvbo; 342 return 0; 343 } 344 345 static void 346 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t domain) 347 { 348 *n = 0; 349 350 if (domain & NOUVEAU_GEM_DOMAIN_VRAM) { 351 pl[*n].mem_type = TTM_PL_VRAM; 352 pl[*n].flags = 0; 353 (*n)++; 354 } 355 if (domain & NOUVEAU_GEM_DOMAIN_GART) { 356 pl[*n].mem_type = TTM_PL_TT; 357 pl[*n].flags = 0; 358 (*n)++; 359 } 360 if (domain & NOUVEAU_GEM_DOMAIN_CPU) { 361 pl[*n].mem_type = TTM_PL_SYSTEM; 362 pl[(*n)++].flags = 0; 363 } 364 } 365 366 static void 367 set_placement_range(struct nouveau_bo *nvbo, uint32_t domain) 368 { 369 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 370 u32 vram_pages = drm->client.device.info.ram_size >> PAGE_SHIFT; 371 unsigned i, fpfn, lpfn; 372 373 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && 374 nvbo->mode && (domain & NOUVEAU_GEM_DOMAIN_VRAM) && 375 nvbo->bo.mem.num_pages < vram_pages / 4) { 376 /* 377 * Make sure that the color and depth buffers are handled 378 * by independent memory controller units. Up to a 9x 379 * speed up when alpha-blending and depth-test are enabled 380 * at the same time. 381 */ 382 if (nvbo->zeta) { 383 fpfn = vram_pages / 2; 384 lpfn = ~0; 385 } else { 386 fpfn = 0; 387 lpfn = vram_pages / 2; 388 } 389 for (i = 0; i < nvbo->placement.num_placement; ++i) { 390 nvbo->placements[i].fpfn = fpfn; 391 nvbo->placements[i].lpfn = lpfn; 392 } 393 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 394 nvbo->busy_placements[i].fpfn = fpfn; 395 nvbo->busy_placements[i].lpfn = lpfn; 396 } 397 } 398 } 399 400 void 401 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t domain, 402 uint32_t busy) 403 { 404 struct ttm_placement *pl = &nvbo->placement; 405 406 pl->placement = nvbo->placements; 407 set_placement_list(nvbo->placements, &pl->num_placement, domain); 408 409 pl->busy_placement = nvbo->busy_placements; 410 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, 411 domain | busy); 412 413 set_placement_range(nvbo, domain); 414 } 415 416 int 417 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t domain, bool contig) 418 { 419 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 420 struct ttm_buffer_object *bo = &nvbo->bo; 421 bool force = false, evict = false; 422 int ret; 423 424 ret = ttm_bo_reserve(bo, false, false, NULL); 425 if (ret) 426 return ret; 427 428 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 429 domain == NOUVEAU_GEM_DOMAIN_VRAM && contig) { 430 if (!nvbo->contig) { 431 nvbo->contig = true; 432 force = true; 433 evict = true; 434 } 435 } 436 437 if (nvbo->bo.pin_count) { 438 bool error = evict; 439 440 switch (bo->mem.mem_type) { 441 case TTM_PL_VRAM: 442 error |= !(domain & NOUVEAU_GEM_DOMAIN_VRAM); 443 break; 444 case TTM_PL_TT: 445 error |= !(domain & NOUVEAU_GEM_DOMAIN_GART); 446 default: 447 break; 448 } 449 450 if (error) { 451 NV_ERROR(drm, "bo %p pinned elsewhere: " 452 "0x%08x vs 0x%08x\n", bo, 453 bo->mem.mem_type, domain); 454 ret = -EBUSY; 455 } 456 ttm_bo_pin(&nvbo->bo); 457 goto out; 458 } 459 460 if (evict) { 461 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0); 462 ret = nouveau_bo_validate(nvbo, false, false); 463 if (ret) 464 goto out; 465 } 466 467 nouveau_bo_placement_set(nvbo, domain, 0); 468 ret = nouveau_bo_validate(nvbo, false, false); 469 if (ret) 470 goto out; 471 472 ttm_bo_pin(&nvbo->bo); 473 474 switch (bo->mem.mem_type) { 475 case TTM_PL_VRAM: 476 drm->gem.vram_available -= bo->base.size; 477 break; 478 case TTM_PL_TT: 479 drm->gem.gart_available -= bo->base.size; 480 break; 481 default: 482 break; 483 } 484 485 out: 486 if (force && ret) 487 nvbo->contig = false; 488 ttm_bo_unreserve(bo); 489 return ret; 490 } 491 492 int 493 nouveau_bo_unpin(struct nouveau_bo *nvbo) 494 { 495 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 496 struct ttm_buffer_object *bo = &nvbo->bo; 497 int ret; 498 499 ret = ttm_bo_reserve(bo, false, false, NULL); 500 if (ret) 501 return ret; 502 503 ttm_bo_unpin(&nvbo->bo); 504 if (!nvbo->bo.pin_count) { 505 switch (bo->mem.mem_type) { 506 case TTM_PL_VRAM: 507 drm->gem.vram_available += bo->base.size; 508 break; 509 case TTM_PL_TT: 510 drm->gem.gart_available += bo->base.size; 511 break; 512 default: 513 break; 514 } 515 } 516 517 ttm_bo_unreserve(bo); 518 return 0; 519 } 520 521 int 522 nouveau_bo_map(struct nouveau_bo *nvbo) 523 { 524 int ret; 525 526 ret = ttm_bo_reserve(&nvbo->bo, false, false, NULL); 527 if (ret) 528 return ret; 529 530 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); 531 532 ttm_bo_unreserve(&nvbo->bo); 533 return ret; 534 } 535 536 void 537 nouveau_bo_unmap(struct nouveau_bo *nvbo) 538 { 539 if (!nvbo) 540 return; 541 542 ttm_bo_kunmap(&nvbo->kmap); 543 } 544 545 void 546 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) 547 { 548 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 549 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 550 int i, j; 551 552 if (!ttm_dma) 553 return; 554 555 /* Don't waste time looping if the object is coherent */ 556 if (nvbo->force_coherent) 557 return; 558 559 for (i = 0; i < ttm_dma->num_pages; ++i) { 560 struct page *p = ttm_dma->pages[i]; 561 size_t num_pages = 1; 562 563 for (j = i + 1; j < ttm_dma->num_pages; ++j) { 564 if (++p != ttm_dma->pages[j]) 565 break; 566 567 ++num_pages; 568 } 569 dma_sync_single_for_device(drm->dev->dev, 570 ttm_dma->dma_address[i], 571 num_pages * PAGE_SIZE, DMA_TO_DEVICE); 572 i += num_pages; 573 } 574 } 575 576 void 577 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) 578 { 579 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); 580 struct ttm_tt *ttm_dma = (struct ttm_tt *)nvbo->bo.ttm; 581 int i, j; 582 583 if (!ttm_dma) 584 return; 585 586 /* Don't waste time looping if the object is coherent */ 587 if (nvbo->force_coherent) 588 return; 589 590 for (i = 0; i < ttm_dma->num_pages; ++i) { 591 struct page *p = ttm_dma->pages[i]; 592 size_t num_pages = 1; 593 594 for (j = i + 1; j < ttm_dma->num_pages; ++j) { 595 if (++p != ttm_dma->pages[j]) 596 break; 597 598 ++num_pages; 599 } 600 601 dma_sync_single_for_cpu(drm->dev->dev, ttm_dma->dma_address[i], 602 num_pages * PAGE_SIZE, DMA_FROM_DEVICE); 603 i += num_pages; 604 } 605 } 606 607 void nouveau_bo_add_io_reserve_lru(struct ttm_buffer_object *bo) 608 { 609 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 610 struct nouveau_bo *nvbo = nouveau_bo(bo); 611 612 mutex_lock(&drm->ttm.io_reserve_mutex); 613 list_move_tail(&nvbo->io_reserve_lru, &drm->ttm.io_reserve_lru); 614 mutex_unlock(&drm->ttm.io_reserve_mutex); 615 } 616 617 void nouveau_bo_del_io_reserve_lru(struct ttm_buffer_object *bo) 618 { 619 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 620 struct nouveau_bo *nvbo = nouveau_bo(bo); 621 622 mutex_lock(&drm->ttm.io_reserve_mutex); 623 list_del_init(&nvbo->io_reserve_lru); 624 mutex_unlock(&drm->ttm.io_reserve_mutex); 625 } 626 627 int 628 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, 629 bool no_wait_gpu) 630 { 631 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 632 int ret; 633 634 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, &ctx); 635 if (ret) 636 return ret; 637 638 nouveau_bo_sync_for_device(nvbo); 639 640 return 0; 641 } 642 643 void 644 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) 645 { 646 bool is_iomem; 647 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 648 649 mem += index; 650 651 if (is_iomem) 652 iowrite16_native(val, (void __force __iomem *)mem); 653 else 654 *mem = val; 655 } 656 657 u32 658 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) 659 { 660 bool is_iomem; 661 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 662 663 mem += index; 664 665 if (is_iomem) 666 return ioread32_native((void __force __iomem *)mem); 667 else 668 return *mem; 669 } 670 671 void 672 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) 673 { 674 bool is_iomem; 675 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); 676 677 mem += index; 678 679 if (is_iomem) 680 iowrite32_native(val, (void __force __iomem *)mem); 681 else 682 *mem = val; 683 } 684 685 static struct ttm_tt * 686 nouveau_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) 687 { 688 #if IS_ENABLED(CONFIG_AGP) 689 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 690 691 if (drm->agp.bridge) { 692 return ttm_agp_tt_create(bo, drm->agp.bridge, page_flags); 693 } 694 #endif 695 696 return nouveau_sgdma_create_ttm(bo, page_flags); 697 } 698 699 static int 700 nouveau_ttm_tt_bind(struct ttm_bo_device *bdev, struct ttm_tt *ttm, 701 struct ttm_resource *reg) 702 { 703 #if IS_ENABLED(CONFIG_AGP) 704 struct nouveau_drm *drm = nouveau_bdev(bdev); 705 #endif 706 if (!reg) 707 return -EINVAL; 708 #if IS_ENABLED(CONFIG_AGP) 709 if (drm->agp.bridge) 710 return ttm_agp_bind(ttm, reg); 711 #endif 712 return nouveau_sgdma_bind(bdev, ttm, reg); 713 } 714 715 static void 716 nouveau_ttm_tt_unbind(struct ttm_bo_device *bdev, struct ttm_tt *ttm) 717 { 718 #if IS_ENABLED(CONFIG_AGP) 719 struct nouveau_drm *drm = nouveau_bdev(bdev); 720 721 if (drm->agp.bridge) { 722 ttm_agp_unbind(ttm); 723 return; 724 } 725 #endif 726 nouveau_sgdma_unbind(bdev, ttm); 727 } 728 729 static void 730 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) 731 { 732 struct nouveau_bo *nvbo = nouveau_bo(bo); 733 734 switch (bo->mem.mem_type) { 735 case TTM_PL_VRAM: 736 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 737 NOUVEAU_GEM_DOMAIN_CPU); 738 break; 739 default: 740 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_CPU, 0); 741 break; 742 } 743 744 *pl = nvbo->placement; 745 } 746 747 static int 748 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, 749 struct ttm_resource *reg) 750 { 751 struct nouveau_mem *old_mem = nouveau_mem(&bo->mem); 752 struct nouveau_mem *new_mem = nouveau_mem(reg); 753 struct nvif_vmm *vmm = &drm->client.vmm.vmm; 754 int ret; 755 756 ret = nvif_vmm_get(vmm, LAZY, false, old_mem->mem.page, 0, 757 old_mem->mem.size, &old_mem->vma[0]); 758 if (ret) 759 return ret; 760 761 ret = nvif_vmm_get(vmm, LAZY, false, new_mem->mem.page, 0, 762 new_mem->mem.size, &old_mem->vma[1]); 763 if (ret) 764 goto done; 765 766 ret = nouveau_mem_map(old_mem, vmm, &old_mem->vma[0]); 767 if (ret) 768 goto done; 769 770 ret = nouveau_mem_map(new_mem, vmm, &old_mem->vma[1]); 771 done: 772 if (ret) { 773 nvif_vmm_put(vmm, &old_mem->vma[1]); 774 nvif_vmm_put(vmm, &old_mem->vma[0]); 775 } 776 return 0; 777 } 778 779 static int 780 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, 781 struct ttm_operation_ctx *ctx, 782 struct ttm_resource *new_reg) 783 { 784 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 785 struct nouveau_channel *chan = drm->ttm.chan; 786 struct nouveau_cli *cli = (void *)chan->user.client; 787 struct nouveau_fence *fence; 788 int ret; 789 790 /* create temporary vmas for the transfer and attach them to the 791 * old nvkm_mem node, these will get cleaned up after ttm has 792 * destroyed the ttm_resource 793 */ 794 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) { 795 ret = nouveau_bo_move_prep(drm, bo, new_reg); 796 if (ret) 797 return ret; 798 } 799 800 if (drm_drv_uses_atomic_modeset(drm->dev)) 801 mutex_lock(&cli->mutex); 802 else 803 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); 804 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, ctx->interruptible); 805 if (ret == 0) { 806 ret = drm->ttm.move(chan, bo, &bo->mem, new_reg); 807 if (ret == 0) { 808 ret = nouveau_fence_new(chan, false, &fence); 809 if (ret == 0) { 810 ret = ttm_bo_move_accel_cleanup(bo, 811 &fence->base, 812 evict, false, 813 new_reg); 814 nouveau_fence_unref(&fence); 815 } 816 } 817 } 818 mutex_unlock(&cli->mutex); 819 return ret; 820 } 821 822 void 823 nouveau_bo_move_init(struct nouveau_drm *drm) 824 { 825 static const struct _method_table { 826 const char *name; 827 int engine; 828 s32 oclass; 829 int (*exec)(struct nouveau_channel *, 830 struct ttm_buffer_object *, 831 struct ttm_resource *, struct ttm_resource *); 832 int (*init)(struct nouveau_channel *, u32 handle); 833 } _methods[] = { 834 { "COPY", 4, 0xc5b5, nve0_bo_move_copy, nve0_bo_move_init }, 835 { "GRCE", 0, 0xc5b5, nve0_bo_move_copy, nvc0_bo_move_init }, 836 { "COPY", 4, 0xc3b5, nve0_bo_move_copy, nve0_bo_move_init }, 837 { "GRCE", 0, 0xc3b5, nve0_bo_move_copy, nvc0_bo_move_init }, 838 { "COPY", 4, 0xc1b5, nve0_bo_move_copy, nve0_bo_move_init }, 839 { "GRCE", 0, 0xc1b5, nve0_bo_move_copy, nvc0_bo_move_init }, 840 { "COPY", 4, 0xc0b5, nve0_bo_move_copy, nve0_bo_move_init }, 841 { "GRCE", 0, 0xc0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 842 { "COPY", 4, 0xb0b5, nve0_bo_move_copy, nve0_bo_move_init }, 843 { "GRCE", 0, 0xb0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 844 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, 845 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, 846 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, 847 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, 848 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, 849 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, 850 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, 851 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, 852 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, 853 {}, 854 }; 855 const struct _method_table *mthd = _methods; 856 const char *name = "CPU"; 857 int ret; 858 859 do { 860 struct nouveau_channel *chan; 861 862 if (mthd->engine) 863 chan = drm->cechan; 864 else 865 chan = drm->channel; 866 if (chan == NULL) 867 continue; 868 869 ret = nvif_object_ctor(&chan->user, "ttmBoMove", 870 mthd->oclass | (mthd->engine << 16), 871 mthd->oclass, NULL, 0, 872 &drm->ttm.copy); 873 if (ret == 0) { 874 ret = mthd->init(chan, drm->ttm.copy.handle); 875 if (ret) { 876 nvif_object_dtor(&drm->ttm.copy); 877 continue; 878 } 879 880 drm->ttm.move = mthd->exec; 881 drm->ttm.chan = chan; 882 name = mthd->name; 883 break; 884 } 885 } while ((++mthd)->exec); 886 887 NV_INFO(drm, "MM: using %s for buffer copies\n", name); 888 } 889 890 static void 891 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, bool evict, 892 struct ttm_resource *new_reg) 893 { 894 struct nouveau_mem *mem = new_reg ? nouveau_mem(new_reg) : NULL; 895 struct nouveau_bo *nvbo = nouveau_bo(bo); 896 struct nouveau_vma *vma; 897 898 /* ttm can now (stupidly) pass the driver bos it didn't create... */ 899 if (bo->destroy != nouveau_bo_del_ttm) 900 return; 901 902 nouveau_bo_del_io_reserve_lru(bo); 903 904 if (mem && new_reg->mem_type != TTM_PL_SYSTEM && 905 mem->mem.page == nvbo->page) { 906 list_for_each_entry(vma, &nvbo->vma_list, head) { 907 nouveau_vma_map(vma, mem); 908 } 909 } else { 910 list_for_each_entry(vma, &nvbo->vma_list, head) { 911 WARN_ON(ttm_bo_wait(bo, false, false)); 912 nouveau_vma_unmap(vma); 913 } 914 } 915 916 if (new_reg) { 917 if (new_reg->mm_node) 918 nvbo->offset = (new_reg->start << PAGE_SHIFT); 919 else 920 nvbo->offset = 0; 921 } 922 923 } 924 925 static int 926 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_resource *new_reg, 927 struct nouveau_drm_tile **new_tile) 928 { 929 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 930 struct drm_device *dev = drm->dev; 931 struct nouveau_bo *nvbo = nouveau_bo(bo); 932 u64 offset = new_reg->start << PAGE_SHIFT; 933 934 *new_tile = NULL; 935 if (new_reg->mem_type != TTM_PL_VRAM) 936 return 0; 937 938 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 939 *new_tile = nv10_bo_set_tiling(dev, offset, bo->base.size, 940 nvbo->mode, nvbo->zeta); 941 } 942 943 return 0; 944 } 945 946 static void 947 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, 948 struct nouveau_drm_tile *new_tile, 949 struct nouveau_drm_tile **old_tile) 950 { 951 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 952 struct drm_device *dev = drm->dev; 953 struct dma_fence *fence = dma_resv_get_excl(bo->base.resv); 954 955 nv10_bo_put_tile_region(dev, *old_tile, fence); 956 *old_tile = new_tile; 957 } 958 959 static int 960 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, 961 struct ttm_operation_ctx *ctx, 962 struct ttm_resource *new_reg, 963 struct ttm_place *hop) 964 { 965 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 966 struct nouveau_bo *nvbo = nouveau_bo(bo); 967 struct ttm_resource *old_reg = &bo->mem; 968 struct nouveau_drm_tile *new_tile = NULL; 969 int ret = 0; 970 971 972 if (new_reg->mem_type == TTM_PL_TT) { 973 ret = nouveau_ttm_tt_bind(bo->bdev, bo->ttm, new_reg); 974 if (ret) 975 return ret; 976 } 977 978 nouveau_bo_move_ntfy(bo, evict, new_reg); 979 ret = ttm_bo_wait_ctx(bo, ctx); 980 if (ret) 981 goto out_ntfy; 982 983 if (nvbo->bo.pin_count) 984 NV_WARN(drm, "Moving pinned object %p!\n", nvbo); 985 986 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 987 ret = nouveau_bo_vm_bind(bo, new_reg, &new_tile); 988 if (ret) 989 goto out_ntfy; 990 } 991 992 /* Fake bo copy. */ 993 if (old_reg->mem_type == TTM_PL_SYSTEM && !bo->ttm) { 994 ttm_bo_move_null(bo, new_reg); 995 goto out; 996 } 997 998 if (old_reg->mem_type == TTM_PL_SYSTEM && 999 new_reg->mem_type == TTM_PL_TT) { 1000 ttm_bo_move_null(bo, new_reg); 1001 goto out; 1002 } 1003 1004 if (old_reg->mem_type == TTM_PL_TT && 1005 new_reg->mem_type == TTM_PL_SYSTEM) { 1006 nouveau_ttm_tt_unbind(bo->bdev, bo->ttm); 1007 ttm_resource_free(bo, &bo->mem); 1008 ttm_bo_assign_mem(bo, new_reg); 1009 goto out; 1010 } 1011 1012 /* Hardware assisted copy. */ 1013 if (drm->ttm.move) { 1014 if ((old_reg->mem_type == TTM_PL_SYSTEM && 1015 new_reg->mem_type == TTM_PL_VRAM) || 1016 (old_reg->mem_type == TTM_PL_VRAM && 1017 new_reg->mem_type == TTM_PL_SYSTEM)) { 1018 hop->fpfn = 0; 1019 hop->lpfn = 0; 1020 hop->mem_type = TTM_PL_TT; 1021 hop->flags = 0; 1022 return -EMULTIHOP; 1023 } 1024 ret = nouveau_bo_move_m2mf(bo, evict, ctx, 1025 new_reg); 1026 } else 1027 ret = -ENODEV; 1028 1029 if (ret) { 1030 /* Fallback to software copy. */ 1031 ret = ttm_bo_move_memcpy(bo, ctx, new_reg); 1032 } 1033 1034 out: 1035 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA) { 1036 if (ret) 1037 nouveau_bo_vm_cleanup(bo, NULL, &new_tile); 1038 else 1039 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); 1040 } 1041 out_ntfy: 1042 if (ret) { 1043 swap(*new_reg, bo->mem); 1044 nouveau_bo_move_ntfy(bo, false, new_reg); 1045 swap(*new_reg, bo->mem); 1046 } 1047 return ret; 1048 } 1049 1050 static int 1051 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) 1052 { 1053 struct nouveau_bo *nvbo = nouveau_bo(bo); 1054 1055 return drm_vma_node_verify_access(&nvbo->bo.base.vma_node, 1056 filp->private_data); 1057 } 1058 1059 static void 1060 nouveau_ttm_io_mem_free_locked(struct nouveau_drm *drm, 1061 struct ttm_resource *reg) 1062 { 1063 struct nouveau_mem *mem = nouveau_mem(reg); 1064 1065 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1066 switch (reg->mem_type) { 1067 case TTM_PL_TT: 1068 if (mem->kind) 1069 nvif_object_unmap_handle(&mem->mem.object); 1070 break; 1071 case TTM_PL_VRAM: 1072 nvif_object_unmap_handle(&mem->mem.object); 1073 break; 1074 default: 1075 break; 1076 } 1077 } 1078 } 1079 1080 static int 1081 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *reg) 1082 { 1083 struct nouveau_drm *drm = nouveau_bdev(bdev); 1084 struct nvkm_device *device = nvxx_device(&drm->client.device); 1085 struct nouveau_mem *mem = nouveau_mem(reg); 1086 struct nvif_mmu *mmu = &drm->client.mmu; 1087 int ret; 1088 1089 mutex_lock(&drm->ttm.io_reserve_mutex); 1090 retry: 1091 switch (reg->mem_type) { 1092 case TTM_PL_SYSTEM: 1093 /* System memory */ 1094 ret = 0; 1095 goto out; 1096 case TTM_PL_TT: 1097 #if IS_ENABLED(CONFIG_AGP) 1098 if (drm->agp.bridge) { 1099 reg->bus.offset = (reg->start << PAGE_SHIFT) + 1100 drm->agp.base; 1101 reg->bus.is_iomem = !drm->agp.cma; 1102 reg->bus.caching = ttm_write_combined; 1103 } 1104 #endif 1105 if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || 1106 !mem->kind) { 1107 /* untiled */ 1108 ret = 0; 1109 break; 1110 } 1111 fallthrough; /* tiled memory */ 1112 case TTM_PL_VRAM: 1113 reg->bus.offset = (reg->start << PAGE_SHIFT) + 1114 device->func->resource_addr(device, 1); 1115 reg->bus.is_iomem = true; 1116 1117 /* Some BARs do not support being ioremapped WC */ 1118 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA && 1119 mmu->type[drm->ttm.type_vram].type & NVIF_MEM_UNCACHED) 1120 reg->bus.caching = ttm_uncached; 1121 else 1122 reg->bus.caching = ttm_write_combined; 1123 1124 if (drm->client.mem->oclass >= NVIF_CLASS_MEM_NV50) { 1125 union { 1126 struct nv50_mem_map_v0 nv50; 1127 struct gf100_mem_map_v0 gf100; 1128 } args; 1129 u64 handle, length; 1130 u32 argc = 0; 1131 1132 switch (mem->mem.object.oclass) { 1133 case NVIF_CLASS_MEM_NV50: 1134 args.nv50.version = 0; 1135 args.nv50.ro = 0; 1136 args.nv50.kind = mem->kind; 1137 args.nv50.comp = mem->comp; 1138 argc = sizeof(args.nv50); 1139 break; 1140 case NVIF_CLASS_MEM_GF100: 1141 args.gf100.version = 0; 1142 args.gf100.ro = 0; 1143 args.gf100.kind = mem->kind; 1144 argc = sizeof(args.gf100); 1145 break; 1146 default: 1147 WARN_ON(1); 1148 break; 1149 } 1150 1151 ret = nvif_object_map_handle(&mem->mem.object, 1152 &args, argc, 1153 &handle, &length); 1154 if (ret != 1) { 1155 if (WARN_ON(ret == 0)) 1156 ret = -EINVAL; 1157 goto out; 1158 } 1159 1160 reg->bus.offset = handle; 1161 } 1162 ret = 0; 1163 break; 1164 default: 1165 ret = -EINVAL; 1166 } 1167 1168 out: 1169 if (ret == -ENOSPC) { 1170 struct nouveau_bo *nvbo; 1171 1172 nvbo = list_first_entry_or_null(&drm->ttm.io_reserve_lru, 1173 typeof(*nvbo), 1174 io_reserve_lru); 1175 if (nvbo) { 1176 list_del_init(&nvbo->io_reserve_lru); 1177 drm_vma_node_unmap(&nvbo->bo.base.vma_node, 1178 bdev->dev_mapping); 1179 nouveau_ttm_io_mem_free_locked(drm, &nvbo->bo.mem); 1180 goto retry; 1181 } 1182 1183 } 1184 mutex_unlock(&drm->ttm.io_reserve_mutex); 1185 return ret; 1186 } 1187 1188 static void 1189 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_resource *reg) 1190 { 1191 struct nouveau_drm *drm = nouveau_bdev(bdev); 1192 1193 mutex_lock(&drm->ttm.io_reserve_mutex); 1194 nouveau_ttm_io_mem_free_locked(drm, reg); 1195 mutex_unlock(&drm->ttm.io_reserve_mutex); 1196 } 1197 1198 vm_fault_t nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) 1199 { 1200 struct nouveau_drm *drm = nouveau_bdev(bo->bdev); 1201 struct nouveau_bo *nvbo = nouveau_bo(bo); 1202 struct nvkm_device *device = nvxx_device(&drm->client.device); 1203 u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; 1204 int i, ret; 1205 1206 /* as long as the bo isn't in vram, and isn't tiled, we've got 1207 * nothing to do here. 1208 */ 1209 if (bo->mem.mem_type != TTM_PL_VRAM) { 1210 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_TESLA || 1211 !nvbo->kind) 1212 return 0; 1213 1214 if (bo->mem.mem_type != TTM_PL_SYSTEM) 1215 return 0; 1216 1217 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_GART, 0); 1218 1219 } else { 1220 /* make sure bo is in mappable vram */ 1221 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA || 1222 bo->mem.start + bo->mem.num_pages < mappable) 1223 return 0; 1224 1225 for (i = 0; i < nvbo->placement.num_placement; ++i) { 1226 nvbo->placements[i].fpfn = 0; 1227 nvbo->placements[i].lpfn = mappable; 1228 } 1229 1230 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { 1231 nvbo->busy_placements[i].fpfn = 0; 1232 nvbo->busy_placements[i].lpfn = mappable; 1233 } 1234 1235 nouveau_bo_placement_set(nvbo, NOUVEAU_GEM_DOMAIN_VRAM, 0); 1236 } 1237 1238 ret = nouveau_bo_validate(nvbo, false, false); 1239 if (unlikely(ret == -EBUSY || ret == -ERESTARTSYS)) 1240 return VM_FAULT_NOPAGE; 1241 else if (unlikely(ret)) 1242 return VM_FAULT_SIGBUS; 1243 1244 ttm_bo_move_to_lru_tail_unlocked(bo); 1245 return 0; 1246 } 1247 1248 static int 1249 nouveau_ttm_tt_populate(struct ttm_bo_device *bdev, 1250 struct ttm_tt *ttm, struct ttm_operation_ctx *ctx) 1251 { 1252 struct ttm_tt *ttm_dma = (void *)ttm; 1253 struct nouveau_drm *drm; 1254 struct device *dev; 1255 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1256 1257 if (ttm_tt_is_populated(ttm)) 1258 return 0; 1259 1260 if (slave && ttm->sg) { 1261 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm_dma->dma_address, 1262 ttm->num_pages); 1263 return 0; 1264 } 1265 1266 drm = nouveau_bdev(bdev); 1267 dev = drm->dev->dev; 1268 1269 return ttm_pool_alloc(&drm->ttm.bdev.pool, ttm, ctx); 1270 } 1271 1272 static void 1273 nouveau_ttm_tt_unpopulate(struct ttm_bo_device *bdev, 1274 struct ttm_tt *ttm) 1275 { 1276 struct nouveau_drm *drm; 1277 struct device *dev; 1278 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 1279 1280 if (slave) 1281 return; 1282 1283 drm = nouveau_bdev(bdev); 1284 dev = drm->dev->dev; 1285 1286 return ttm_pool_free(&drm->ttm.bdev.pool, ttm); 1287 } 1288 1289 static void 1290 nouveau_ttm_tt_destroy(struct ttm_bo_device *bdev, 1291 struct ttm_tt *ttm) 1292 { 1293 #if IS_ENABLED(CONFIG_AGP) 1294 struct nouveau_drm *drm = nouveau_bdev(bdev); 1295 if (drm->agp.bridge) { 1296 ttm_agp_unbind(ttm); 1297 ttm_tt_destroy_common(bdev, ttm); 1298 ttm_agp_destroy(ttm); 1299 return; 1300 } 1301 #endif 1302 nouveau_sgdma_destroy(bdev, ttm); 1303 } 1304 1305 void 1306 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) 1307 { 1308 struct dma_resv *resv = nvbo->bo.base.resv; 1309 1310 if (exclusive) 1311 dma_resv_add_excl_fence(resv, &fence->base); 1312 else if (fence) 1313 dma_resv_add_shared_fence(resv, &fence->base); 1314 } 1315 1316 static void 1317 nouveau_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1318 { 1319 nouveau_bo_move_ntfy(bo, false, NULL); 1320 } 1321 1322 struct ttm_bo_driver nouveau_bo_driver = { 1323 .ttm_tt_create = &nouveau_ttm_tt_create, 1324 .ttm_tt_populate = &nouveau_ttm_tt_populate, 1325 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, 1326 .ttm_tt_destroy = &nouveau_ttm_tt_destroy, 1327 .eviction_valuable = ttm_bo_eviction_valuable, 1328 .evict_flags = nouveau_bo_evict_flags, 1329 .delete_mem_notify = nouveau_bo_delete_mem_notify, 1330 .move = nouveau_bo_move, 1331 .verify_access = nouveau_bo_verify_access, 1332 .io_mem_reserve = &nouveau_ttm_io_mem_reserve, 1333 .io_mem_free = &nouveau_ttm_io_mem_free, 1334 }; 1335