1 /* 2 * Copyright 2007-2008 Nouveau Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef __NOUVEAU_BIOS_H__ 25 #define __NOUVEAU_BIOS_H__ 26 27 #include "nvreg.h" 28 #include "nouveau_i2c.h" 29 30 #define DCB_MAX_NUM_ENTRIES 16 31 #define DCB_MAX_NUM_I2C_ENTRIES 16 32 #define DCB_MAX_NUM_GPIO_ENTRIES 32 33 #define DCB_MAX_NUM_CONNECTOR_ENTRIES 16 34 35 #define DCB_LOC_ON_CHIP 0 36 37 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) 38 #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) 39 #define ROMPTR(bios, x) (ROM16(x) ? &(bios)->data[ROM16(x)] : NULL) 40 41 struct bit_entry { 42 uint8_t id; 43 uint8_t version; 44 uint16_t length; 45 uint16_t offset; 46 uint8_t *data; 47 }; 48 49 int bit_table(struct drm_device *, u8 id, struct bit_entry *); 50 51 struct dcb_i2c_entry { 52 uint32_t entry; 53 uint8_t port_type; 54 uint8_t read, write; 55 struct nouveau_i2c_chan *chan; 56 }; 57 58 enum dcb_gpio_tag { 59 DCB_GPIO_TVDAC0 = 0xc, 60 DCB_GPIO_TVDAC1 = 0x2d, 61 }; 62 63 struct dcb_gpio_entry { 64 enum dcb_gpio_tag tag; 65 int line; 66 bool invert; 67 uint32_t entry; 68 uint8_t state_default; 69 uint8_t state[2]; 70 }; 71 72 struct dcb_gpio_table { 73 int entries; 74 struct dcb_gpio_entry entry[DCB_MAX_NUM_GPIO_ENTRIES]; 75 }; 76 77 enum dcb_connector_type { 78 DCB_CONNECTOR_VGA = 0x00, 79 DCB_CONNECTOR_TV_0 = 0x10, 80 DCB_CONNECTOR_TV_1 = 0x11, 81 DCB_CONNECTOR_TV_3 = 0x13, 82 DCB_CONNECTOR_DVI_I = 0x30, 83 DCB_CONNECTOR_DVI_D = 0x31, 84 DCB_CONNECTOR_LVDS = 0x40, 85 DCB_CONNECTOR_LVDS_SPWG = 0x41, 86 DCB_CONNECTOR_DP = 0x46, 87 DCB_CONNECTOR_eDP = 0x47, 88 DCB_CONNECTOR_HDMI_0 = 0x60, 89 DCB_CONNECTOR_HDMI_1 = 0x61, 90 DCB_CONNECTOR_NONE = 0xff 91 }; 92 93 struct dcb_connector_table_entry { 94 uint8_t index; 95 uint32_t entry; 96 enum dcb_connector_type type; 97 uint8_t index2; 98 uint8_t gpio_tag; 99 void *drm; 100 }; 101 102 struct dcb_connector_table { 103 int entries; 104 struct dcb_connector_table_entry entry[DCB_MAX_NUM_CONNECTOR_ENTRIES]; 105 }; 106 107 enum dcb_type { 108 OUTPUT_ANALOG = 0, 109 OUTPUT_TV = 1, 110 OUTPUT_TMDS = 2, 111 OUTPUT_LVDS = 3, 112 OUTPUT_DP = 6, 113 OUTPUT_EOL = 14, /* DCB 4.0+, appears to be end-of-list */ 114 OUTPUT_ANY = -1 115 }; 116 117 struct dcb_entry { 118 int index; /* may not be raw dcb index if merging has happened */ 119 enum dcb_type type; 120 uint8_t i2c_index; 121 uint8_t heads; 122 uint8_t connector; 123 uint8_t bus; 124 uint8_t location; 125 uint8_t or; 126 bool duallink_possible; 127 union { 128 struct sor_conf { 129 int link; 130 } sorconf; 131 struct { 132 int maxfreq; 133 } crtconf; 134 struct { 135 struct sor_conf sor; 136 bool use_straps_for_mode; 137 bool use_acpi_for_edid; 138 bool use_power_scripts; 139 } lvdsconf; 140 struct { 141 bool has_component_output; 142 } tvconf; 143 struct { 144 struct sor_conf sor; 145 int link_nr; 146 int link_bw; 147 } dpconf; 148 struct { 149 struct sor_conf sor; 150 int slave_addr; 151 } tmdsconf; 152 }; 153 bool i2c_upper_default; 154 }; 155 156 struct dcb_table { 157 uint8_t version; 158 159 int entries; 160 struct dcb_entry entry[DCB_MAX_NUM_ENTRIES]; 161 162 uint8_t *i2c_table; 163 uint8_t i2c_default_indices; 164 struct dcb_i2c_entry i2c[DCB_MAX_NUM_I2C_ENTRIES]; 165 166 uint16_t gpio_table_ptr; 167 struct dcb_gpio_table gpio; 168 uint16_t connector_table_ptr; 169 struct dcb_connector_table connector; 170 }; 171 172 enum nouveau_or { 173 OUTPUT_A = (1 << 0), 174 OUTPUT_B = (1 << 1), 175 OUTPUT_C = (1 << 2) 176 }; 177 178 enum LVDS_script { 179 /* Order *does* matter here */ 180 LVDS_INIT = 1, 181 LVDS_RESET, 182 LVDS_BACKLIGHT_ON, 183 LVDS_BACKLIGHT_OFF, 184 LVDS_PANEL_ON, 185 LVDS_PANEL_OFF 186 }; 187 188 /* these match types in pll limits table version 0x40, 189 * nouveau uses them on all chipsets internally where a 190 * specific pll needs to be referenced, but the exact 191 * register isn't known. 192 */ 193 enum pll_types { 194 PLL_CORE = 0x01, 195 PLL_SHADER = 0x02, 196 PLL_UNK03 = 0x03, 197 PLL_MEMORY = 0x04, 198 PLL_UNK05 = 0x05, 199 PLL_UNK40 = 0x40, 200 PLL_UNK41 = 0x41, 201 PLL_UNK42 = 0x42, 202 PLL_VPLL0 = 0x80, 203 PLL_VPLL1 = 0x81, 204 PLL_MAX = 0xff 205 }; 206 207 struct pll_lims { 208 u32 reg; 209 210 struct { 211 int minfreq; 212 int maxfreq; 213 int min_inputfreq; 214 int max_inputfreq; 215 216 uint8_t min_m; 217 uint8_t max_m; 218 uint8_t min_n; 219 uint8_t max_n; 220 } vco1, vco2; 221 222 uint8_t max_log2p; 223 /* 224 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p 225 * value) is no different to 6 (at least for vplls) so allowing the MNP 226 * calc to use 7 causes the generated clock to be out by a factor of 2. 227 * however, max_log2p cannot be fixed-up during parsing as the 228 * unmodified max_log2p value is still needed for setting mplls, hence 229 * an additional max_usable_log2p member 230 */ 231 uint8_t max_usable_log2p; 232 uint8_t log2p_bias; 233 234 uint8_t min_p; 235 uint8_t max_p; 236 237 int refclk; 238 }; 239 240 struct nvbios { 241 struct drm_device *dev; 242 enum { 243 NVBIOS_BMP, 244 NVBIOS_BIT 245 } type; 246 uint16_t offset; 247 248 uint8_t chip_version; 249 250 uint32_t dactestval; 251 uint32_t tvdactestval; 252 uint8_t digital_min_front_porch; 253 bool fp_no_ddc; 254 255 spinlock_t lock; 256 257 uint8_t data[NV_PROM_SIZE]; 258 unsigned int length; 259 bool execute; 260 261 uint8_t major_version; 262 uint8_t feature_byte; 263 bool is_mobile; 264 265 uint32_t fmaxvco, fminvco; 266 267 bool old_style_init; 268 uint16_t init_script_tbls_ptr; 269 uint16_t extra_init_script_tbl_ptr; 270 uint16_t macro_index_tbl_ptr; 271 uint16_t macro_tbl_ptr; 272 uint16_t condition_tbl_ptr; 273 uint16_t io_condition_tbl_ptr; 274 uint16_t io_flag_condition_tbl_ptr; 275 uint16_t init_function_tbl_ptr; 276 277 uint16_t pll_limit_tbl_ptr; 278 uint16_t ram_restrict_tbl_ptr; 279 uint8_t ram_restrict_group_count; 280 281 uint16_t some_script_ptr; /* BIT I + 14 */ 282 uint16_t init96_tbl_ptr; /* BIT I + 16 */ 283 284 struct dcb_table dcb; 285 286 struct { 287 int crtchead; 288 } state; 289 290 struct { 291 struct dcb_entry *output; 292 uint16_t script_table_ptr; 293 uint16_t dp_table_ptr; 294 } display; 295 296 struct { 297 uint16_t fptablepointer; /* also used by tmds */ 298 uint16_t fpxlatetableptr; 299 int xlatwidth; 300 uint16_t lvdsmanufacturerpointer; 301 uint16_t fpxlatemanufacturertableptr; 302 uint16_t mode_ptr; 303 uint16_t xlated_entry; 304 bool power_off_for_reset; 305 bool reset_after_pclk_change; 306 bool dual_link; 307 bool link_c_increment; 308 bool if_is_24bit; 309 int duallink_transition_clk; 310 uint8_t strapless_is_24bit; 311 uint8_t *edid; 312 313 /* will need resetting after suspend */ 314 int last_script_invoc; 315 bool lvds_init_run; 316 } fp; 317 318 struct { 319 uint16_t output0_script_ptr; 320 uint16_t output1_script_ptr; 321 } tmds; 322 323 struct { 324 uint16_t mem_init_tbl_ptr; 325 uint16_t sdr_seq_tbl_ptr; 326 uint16_t ddr_seq_tbl_ptr; 327 328 struct { 329 uint8_t crt, tv, panel; 330 } i2c_indices; 331 332 uint16_t lvds_single_a_script_ptr; 333 } legacy; 334 }; 335 336 #endif 337