17632b30eSBen Skeggs #ifndef __NVKM_CLK_H__ 27632b30eSBen Skeggs #define __NVKM_CLK_H__ 3f3867f43SBen Skeggs #include <core/subdev.h> 47632b30eSBen Skeggs #include <core/notify.h> 5d3b378c0SKarol Herbst #include <subdev/pci.h> 6f3867f43SBen Skeggs struct nvbios_pll; 77632b30eSBen Skeggs struct nvkm_pll_vals; 8f3867f43SBen Skeggs 9f3867f43SBen Skeggs enum nv_clk_src { 10f3867f43SBen Skeggs nv_clk_src_crystal, 11f3867f43SBen Skeggs nv_clk_src_href, 12f3867f43SBen Skeggs 13f3867f43SBen Skeggs nv_clk_src_hclk, 14f3867f43SBen Skeggs nv_clk_src_hclkm3, 15f3867f43SBen Skeggs nv_clk_src_hclkm3d2, 16f3867f43SBen Skeggs nv_clk_src_hclkm2d3, /* NVAA */ 17f3867f43SBen Skeggs nv_clk_src_hclkm4, /* NVAA */ 18f3867f43SBen Skeggs nv_clk_src_cclk, /* NVAA */ 19f3867f43SBen Skeggs 20f3867f43SBen Skeggs nv_clk_src_host, 21f3867f43SBen Skeggs 22f3867f43SBen Skeggs nv_clk_src_sppll0, 23f3867f43SBen Skeggs nv_clk_src_sppll1, 24f3867f43SBen Skeggs 25f3867f43SBen Skeggs nv_clk_src_mpllsrcref, 26f3867f43SBen Skeggs nv_clk_src_mpllsrc, 27f3867f43SBen Skeggs nv_clk_src_mpll, 28f3867f43SBen Skeggs nv_clk_src_mdiv, 29f3867f43SBen Skeggs 30f3867f43SBen Skeggs nv_clk_src_core, 31f3867f43SBen Skeggs nv_clk_src_core_intm, 32f3867f43SBen Skeggs nv_clk_src_shader, 33f3867f43SBen Skeggs 34f3867f43SBen Skeggs nv_clk_src_mem, 35f3867f43SBen Skeggs 36f3867f43SBen Skeggs nv_clk_src_gpc, 37f3867f43SBen Skeggs nv_clk_src_rop, 38f3867f43SBen Skeggs nv_clk_src_hubk01, 39f3867f43SBen Skeggs nv_clk_src_hubk06, 40f3867f43SBen Skeggs nv_clk_src_hubk07, 41f3867f43SBen Skeggs nv_clk_src_copy, 42547dd271SBen Skeggs nv_clk_src_pmu, 43f3867f43SBen Skeggs nv_clk_src_disp, 44f3867f43SBen Skeggs nv_clk_src_vdec, 45f3867f43SBen Skeggs 46f3867f43SBen Skeggs nv_clk_src_dom6, 47f3867f43SBen Skeggs 48f3867f43SBen Skeggs nv_clk_src_max, 49f3867f43SBen Skeggs }; 50f3867f43SBen Skeggs 517632b30eSBen Skeggs struct nvkm_cstate { 52f3867f43SBen Skeggs struct list_head head; 53f3867f43SBen Skeggs u8 voltage; 54f3867f43SBen Skeggs u32 domain[nv_clk_src_max]; 55761c8f69SKarol Herbst u8 id; 56f3867f43SBen Skeggs }; 57f3867f43SBen Skeggs 587632b30eSBen Skeggs struct nvkm_pstate { 59f3867f43SBen Skeggs struct list_head head; 60f3867f43SBen Skeggs struct list_head list; /* c-states */ 617632b30eSBen Skeggs struct nvkm_cstate base; 62f3867f43SBen Skeggs u8 pstate; 63f3867f43SBen Skeggs u8 fanspeed; 64d3b378c0SKarol Herbst enum nvkm_pcie_speed pcie_speed; 65d3b378c0SKarol Herbst u8 pcie_width; 66f3867f43SBen Skeggs }; 67f3867f43SBen Skeggs 687632b30eSBen Skeggs struct nvkm_domain { 697632b30eSBen Skeggs enum nv_clk_src name; 707632b30eSBen Skeggs u8 bios; /* 0xff for none */ 717632b30eSBen Skeggs #define NVKM_CLK_DOM_FLAG_CORE 0x01 727632b30eSBen Skeggs u8 flags; 737632b30eSBen Skeggs const char *mname; 747632b30eSBen Skeggs int mdiv; 757632b30eSBen Skeggs }; 76f3867f43SBen Skeggs 777632b30eSBen Skeggs struct nvkm_clk { 786625f55cSBen Skeggs const struct nvkm_clk_func *func; 793eca809bSBen Skeggs struct nvkm_subdev subdev; 807632b30eSBen Skeggs 816625f55cSBen Skeggs const struct nvkm_domain *domains; 827632b30eSBen Skeggs struct nvkm_pstate bstate; 83f3867f43SBen Skeggs 84f3867f43SBen Skeggs struct list_head states; 85f3867f43SBen Skeggs int state_nr; 86f3867f43SBen Skeggs 87f3867f43SBen Skeggs struct work_struct work; 88f3867f43SBen Skeggs wait_queue_head_t wait; 89f3867f43SBen Skeggs atomic_t waiting; 90f3867f43SBen Skeggs 91f3867f43SBen Skeggs struct nvkm_notify pwrsrc_ntfy; 92f3867f43SBen Skeggs int pwrsrc; 93f3867f43SBen Skeggs int pstate; /* current */ 94f3867f43SBen Skeggs int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ 95f3867f43SBen Skeggs int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ 96f3867f43SBen Skeggs int astate; /* perfmon adjustment (base) */ 97f3867f43SBen Skeggs int dstate; /* display adjustment (min+) */ 9861a8b84fSKarol Herbst u8 temp; 99f3867f43SBen Skeggs 100f3867f43SBen Skeggs bool allow_reclock; 101f3867f43SBen Skeggs 102f3867f43SBen Skeggs /*XXX: die, these are here *only* to support the completely 1036625f55cSBen Skeggs * bat-shit insane what-was-nouveau_hw.c code 104f3867f43SBen Skeggs */ 1057632b30eSBen Skeggs int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk, 1067632b30eSBen Skeggs struct nvkm_pll_vals *pv); 1077632b30eSBen Skeggs int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv); 108f3867f43SBen Skeggs }; 109f3867f43SBen Skeggs 1106625f55cSBen Skeggs int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src); 1117632b30eSBen Skeggs int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr); 1127632b30eSBen Skeggs int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); 1137632b30eSBen Skeggs int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); 11461a8b84fSKarol Herbst int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature); 1156625f55cSBen Skeggs 1166625f55cSBen Skeggs int nv04_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 1176625f55cSBen Skeggs int nv40_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 1186625f55cSBen Skeggs int nv50_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 1196625f55cSBen Skeggs int g84_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 1206625f55cSBen Skeggs int mcp77_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 1216625f55cSBen Skeggs int gt215_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 1226625f55cSBen Skeggs int gf100_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 1236625f55cSBen Skeggs int gk104_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 1246625f55cSBen Skeggs int gk20a_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 12552829d4fSAlexandre Courbot int gm20b_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 126f3867f43SBen Skeggs #endif 127