1 #ifndef __NVBIOS_PLL_H__
2 #define __NVBIOS_PLL_H__
3 /*XXX: kill me */
4 struct nvkm_pll_vals {
5 	union {
6 		struct {
7 #ifdef __BIG_ENDIAN
8 			uint8_t N1, M1, N2, M2;
9 #else
10 			uint8_t M1, N1, M2, N2;
11 #endif
12 		};
13 		struct {
14 			uint16_t NM1, NM2;
15 		} __attribute__((packed));
16 	};
17 	int log2P;
18 
19 	int refclk;
20 };
21 
22 /* these match types in pll limits table version 0x40,
23  * nvkm uses them on all chipsets internally where a
24  * specific pll needs to be referenced, but the exact
25  * register isn't known.
26  */
27 enum nvbios_pll_type {
28 	PLL_CORE   = 0x01,
29 	PLL_SHADER = 0x02,
30 	PLL_UNK03  = 0x03,
31 	PLL_MEMORY = 0x04,
32 	PLL_VDEC   = 0x05,
33 	PLL_UNK40  = 0x40,
34 	PLL_UNK41  = 0x41,
35 	PLL_UNK42  = 0x42,
36 	PLL_VPLL0  = 0x80,
37 	PLL_VPLL1  = 0x81,
38 	PLL_VPLL2  = 0x82,
39 	PLL_VPLL3  = 0x83,
40 	PLL_MAX    = 0xff
41 };
42 
43 struct nvbios_pll {
44 	enum nvbios_pll_type type;
45 	u32 reg;
46 	u32 refclk;
47 
48 	u8 min_p;
49 	u8 max_p;
50 	u8 bias_p;
51 
52 	/*
53 	 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
54 	 * value) is no different to 6 (at least for vplls) so allowing the MNP
55 	 * calc to use 7 causes the generated clock to be out by a factor of 2.
56 	 * however, max_log2p cannot be fixed-up during parsing as the
57 	 * unmodified max_log2p value is still needed for setting mplls, hence
58 	 * an additional max_usable_log2p member
59 	 */
60 	u8 max_p_usable;
61 
62 	struct {
63 		u32 min_freq;
64 		u32 max_freq;
65 		u32 min_inputfreq;
66 		u32 max_inputfreq;
67 		u8  min_m;
68 		u8  max_m;
69 		u8  min_n;
70 		u8  max_n;
71 	} vco1, vco2;
72 };
73 
74 int nvbios_pll_parse(struct nvkm_bios *, u32 type, struct nvbios_pll *);
75 #endif
76