1b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */ 239b7e6e5SMartin Peres #ifndef __NVBIOS_ICCSENSE_H__ 339b7e6e5SMartin Peres #define __NVBIOS_ICCSENSE_H__ 4a8c119a4SKarol Herbst struct pwr_rail_resistor_t { 5a8c119a4SKarol Herbst u8 mohm; 6a8c119a4SKarol Herbst bool enabled; 7a8c119a4SKarol Herbst }; 8a8c119a4SKarol Herbst 939b7e6e5SMartin Peres struct pwr_rail_t { 1039b7e6e5SMartin Peres u8 mode; 1139b7e6e5SMartin Peres u8 extdev_id; 12a8c119a4SKarol Herbst u8 resistor_count; 13a8c119a4SKarol Herbst struct pwr_rail_resistor_t resistors[3]; 14a8c119a4SKarol Herbst u16 config; 1539b7e6e5SMartin Peres }; 1639b7e6e5SMartin Peres 1739b7e6e5SMartin Peres struct nvbios_iccsense { 1839b7e6e5SMartin Peres int nr_entry; 1939b7e6e5SMartin Peres struct pwr_rail_t *rail; 2039b7e6e5SMartin Peres }; 2139b7e6e5SMartin Peres 2239b7e6e5SMartin Peres int nvbios_iccsense_parse(struct nvkm_bios *, struct nvbios_iccsense *); 2339b7e6e5SMartin Peres #endif 24