1 /* SPDX-License-Identifier: MIT */
2 #ifndef __NVKM_DEVICE_TEGRA_H__
3 #define __NVKM_DEVICE_TEGRA_H__
4 #include <core/device.h>
5 #include <core/mm.h>
6 
7 struct nvkm_device_tegra {
8 	const struct nvkm_device_tegra_func *func;
9 	struct nvkm_device device;
10 	struct platform_device *pdev;
11 	int irq;
12 
13 	struct reset_control *rst;
14 	struct clk *clk;
15 	struct clk *clk_ref;
16 	struct clk *clk_pwr;
17 
18 	struct regulator *vdd;
19 
20 	struct {
21 		/*
22 		 * Protects accesses to mm from subsystems
23 		 */
24 		struct mutex mutex;
25 
26 		struct nvkm_mm mm;
27 		struct iommu_domain *domain;
28 		unsigned long pgshift;
29 	} iommu;
30 
31 	int gpu_speedo;
32 	int gpu_speedo_id;
33 };
34 
35 struct nvkm_device_tegra_func {
36 	/*
37 	 * If an IOMMU is used, indicates which address bit will trigger a
38 	 * IOMMU translation when set (when this bit is not set, IOMMU is
39 	 * bypassed). A value of 0 means an IOMMU is never used.
40 	 */
41 	u8 iommu_bit;
42 	/*
43 	 * Whether the chip requires a reference clock
44 	 */
45 	bool require_ref_clk;
46 	/*
47 	 * Whether the chip requires the VDD regulator
48 	 */
49 	bool require_vdd;
50 };
51 
52 int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
53 			  struct platform_device *,
54 			  const char *cfg, const char *dbg,
55 			  bool detect, bool mmio, u64 subdev_mask,
56 			  struct nvkm_device **);
57 #endif
58