1b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */ 27974dd1bSBen Skeggs #ifndef __NVKM_DEVICE_TEGRA_H__ 37974dd1bSBen Skeggs #define __NVKM_DEVICE_TEGRA_H__ 47974dd1bSBen Skeggs #include <core/device.h> 543a70661SBen Skeggs #include <core/mm.h> 67974dd1bSBen Skeggs 77974dd1bSBen Skeggs struct nvkm_device_tegra { 8e396ecd1SAlexandre Courbot const struct nvkm_device_tegra_func *func; 97974dd1bSBen Skeggs struct nvkm_device device; 107974dd1bSBen Skeggs struct platform_device *pdev; 112b700825SBen Skeggs int irq; 1243a70661SBen Skeggs 1343a70661SBen Skeggs struct reset_control *rst; 1443a70661SBen Skeggs struct clk *clk; 1534440ed6SAlexandre Courbot struct clk *clk_ref; 1643a70661SBen Skeggs struct clk *clk_pwr; 1743a70661SBen Skeggs 1843a70661SBen Skeggs struct regulator *vdd; 1943a70661SBen Skeggs 2043a70661SBen Skeggs struct { 2143a70661SBen Skeggs /* 2243a70661SBen Skeggs * Protects accesses to mm from subsystems 2343a70661SBen Skeggs */ 2443a70661SBen Skeggs struct mutex mutex; 2543a70661SBen Skeggs 2643a70661SBen Skeggs struct nvkm_mm mm; 2743a70661SBen Skeggs struct iommu_domain *domain; 2843a70661SBen Skeggs unsigned long pgshift; 2943a70661SBen Skeggs } iommu; 3043a70661SBen Skeggs 3143a70661SBen Skeggs int gpu_speedo; 32d2680907SAlexandre Courbot int gpu_speedo_id; 337974dd1bSBen Skeggs }; 347974dd1bSBen Skeggs 35e396ecd1SAlexandre Courbot struct nvkm_device_tegra_func { 36e396ecd1SAlexandre Courbot /* 37e396ecd1SAlexandre Courbot * If an IOMMU is used, indicates which address bit will trigger a 38e396ecd1SAlexandre Courbot * IOMMU translation when set (when this bit is not set, IOMMU is 39e396ecd1SAlexandre Courbot * bypassed). A value of 0 means an IOMMU is never used. 40e396ecd1SAlexandre Courbot */ 41e396ecd1SAlexandre Courbot u8 iommu_bit; 4234440ed6SAlexandre Courbot /* 4334440ed6SAlexandre Courbot * Whether the chip requires a reference clock 4434440ed6SAlexandre Courbot */ 4534440ed6SAlexandre Courbot bool require_ref_clk; 46e6e1817aSAlexandre Courbot /* 47e6e1817aSAlexandre Courbot * Whether the chip requires the VDD regulator 48e6e1817aSAlexandre Courbot */ 49e6e1817aSAlexandre Courbot bool require_vdd; 50e396ecd1SAlexandre Courbot }; 51e396ecd1SAlexandre Courbot 52e396ecd1SAlexandre Courbot int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *, 53e396ecd1SAlexandre Courbot struct platform_device *, 547974dd1bSBen Skeggs const char *cfg, const char *dbg, 557974dd1bSBen Skeggs bool detect, bool mmio, u64 subdev_mask, 567974dd1bSBen Skeggs struct nvkm_device **); 577974dd1bSBen Skeggs #endif 58