1 /* SPDX-License-Identifier: MIT */ 2 #ifndef __NVIF_CLASS_H__ 3 #define __NVIF_CLASS_H__ 4 5 /* these class numbers are made up by us, and not nvidia-assigned */ 6 #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000 7 8 #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001 9 10 #define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002 11 #define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003 12 13 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004 14 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005 15 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006 16 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007 17 18 #define NVIF_CLASS_MMU /* if0008.h */ 0x80000008 19 #define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009 20 #define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009 21 #define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009 22 23 #define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a 24 #define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b 25 #define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b 26 #define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b 27 28 #define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c 29 #define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d 30 #define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d 31 #define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d 32 #define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d 33 #define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d 34 35 #define NVIF_CLASS_EVENT /* if000e.h */ 0x8000000e 36 37 #define NVIF_CLASS_DISP /* if0010.h */ 0x80000010 38 #define NVIF_CLASS_CONN /* if0011.h */ 0x80000011 39 #define NVIF_CLASS_OUTP /* if0012.h */ 0x80000012 40 #define NVIF_CLASS_HEAD /* if0013.h */ 0x80000013 41 #define NVIF_CLASS_DISP_CHAN /* if0014.h */ 0x80000014 42 43 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 44 #define NV_NULL_CLASS 0x00000030 45 46 #define NV_DEVICE /* cl0080.h */ 0x00000080 47 48 #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 49 #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 50 #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d 51 52 #define NV50_TWOD 0x0000502d 53 #define FERMI_TWOD_A 0x0000902d 54 55 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 56 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 57 58 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 59 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 60 61 #define NV04_DISP /* cl0046.h */ 0x00000046 62 63 #define VOLTA_USERMODE_A 0x0000c361 64 65 #define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069 66 #define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369 67 68 #define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b 69 #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e 70 #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e 71 #define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e 72 73 #define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f 74 #define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f 75 #define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f 76 #define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f 77 #define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f 78 #define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f 79 #define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f 80 #define VOLTA_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c36f 81 #define TURING_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c46f 82 #define AMPERE_CHANNEL_GPFIFO_B /* clc36f.h */ 0x0000c76f 83 84 #define NV50_DISP /* if0010.h */ 0x00005070 85 #define G82_DISP /* if0010.h */ 0x00008270 86 #define GT200_DISP /* if0010.h */ 0x00008370 87 #define GT214_DISP /* if0010.h */ 0x00008570 88 #define GT206_DISP /* if0010.h */ 0x00008870 89 #define GF110_DISP /* if0010.h */ 0x00009070 90 #define GK104_DISP /* if0010.h */ 0x00009170 91 #define GK110_DISP /* if0010.h */ 0x00009270 92 #define GM107_DISP /* if0010.h */ 0x00009470 93 #define GM200_DISP /* if0010.h */ 0x00009570 94 #define GP100_DISP /* if0010.h */ 0x00009770 95 #define GP102_DISP /* if0010.h */ 0x00009870 96 #define GV100_DISP /* if0010.h */ 0x0000c370 97 #define TU102_DISP /* if0010.h */ 0x0000c570 98 #define GA102_DISP /* if0010.h */ 0x0000c670 99 100 #define GV100_DISP_CAPS 0x0000c373 101 102 #define NV31_MPEG 0x00003174 103 #define G82_MPEG 0x00008274 104 105 #define NV74_VP2 0x00007476 106 107 #define NV50_DISP_CURSOR /* if0014.h */ 0x0000507a 108 #define G82_DISP_CURSOR /* if0014.h */ 0x0000827a 109 #define GT214_DISP_CURSOR /* if0014.h */ 0x0000857a 110 #define GF110_DISP_CURSOR /* if0014.h */ 0x0000907a 111 #define GK104_DISP_CURSOR /* if0014.h */ 0x0000917a 112 #define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a 113 #define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a 114 #define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a 115 116 #define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b 117 #define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b 118 #define GT214_DISP_OVERLAY /* if0014.h */ 0x0000857b 119 #define GF110_DISP_OVERLAY /* if0014.h */ 0x0000907b 120 #define GK104_DISP_OVERLAY /* if0014.h */ 0x0000917b 121 122 #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b 123 #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b 124 #define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b 125 126 #define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c 127 #define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c 128 #define GT200_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000837c 129 #define GT214_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000857c 130 #define GF110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000907c 131 #define GK104_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000917c 132 #define GK110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000927c 133 134 #define NV50_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000507d 135 #define G82_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000827d 136 #define GT200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000837d 137 #define GT214_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000857d 138 #define GT206_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000887d 139 #define GF110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000907d 140 #define GK104_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000917d 141 #define GK110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000927d 142 #define GM107_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000947d 143 #define GM200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000957d 144 #define GP100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000977d 145 #define GP102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000987d 146 #define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d 147 #define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d 148 #define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d 149 150 #define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e 151 #define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e 152 #define GT200_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000837e 153 #define GT214_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000857e 154 #define GF110_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000907e 155 #define GK104_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000917e 156 157 #define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e 158 #define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e 159 #define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e 160 161 #define NV50_TESLA 0x00005097 162 #define G82_TESLA 0x00008297 163 #define GT200_TESLA 0x00008397 164 #define GT214_TESLA 0x00008597 165 #define GT21A_TESLA 0x00008697 166 167 #define FERMI_A /* cl9097.h */ 0x00009097 168 #define FERMI_B /* cl9097.h */ 0x00009197 169 #define FERMI_C /* cl9097.h */ 0x00009297 170 171 #define KEPLER_A /* cl9097.h */ 0x0000a097 172 #define KEPLER_B /* cl9097.h */ 0x0000a197 173 #define KEPLER_C /* cl9097.h */ 0x0000a297 174 175 #define MAXWELL_A /* cl9097.h */ 0x0000b097 176 #define MAXWELL_B /* cl9097.h */ 0x0000b197 177 178 #define PASCAL_A /* cl9097.h */ 0x0000c097 179 #define PASCAL_B /* cl9097.h */ 0x0000c197 180 181 #define VOLTA_A /* cl9097.h */ 0x0000c397 182 183 #define TURING_A /* cl9097.h */ 0x0000c597 184 185 #define NV74_BSP 0x000074b0 186 187 #define GT212_MSVLD 0x000085b1 188 #define IGT21A_MSVLD 0x000086b1 189 #define G98_MSVLD 0x000088b1 190 #define GF100_MSVLD 0x000090b1 191 #define GK104_MSVLD 0x000095b1 192 193 #define GT212_MSPDEC 0x000085b2 194 #define G98_MSPDEC 0x000088b2 195 #define GF100_MSPDEC 0x000090b2 196 #define GK104_MSPDEC 0x000095b2 197 198 #define GT212_MSPPP 0x000085b3 199 #define G98_MSPPP 0x000088b3 200 #define GF100_MSPPP 0x000090b3 201 202 #define G98_SEC 0x000088b4 203 204 #define GT212_DMA 0x000085b5 205 #define FERMI_DMA 0x000090b5 206 #define KEPLER_DMA_COPY_A 0x0000a0b5 207 #define MAXWELL_DMA_COPY_A 0x0000b0b5 208 #define PASCAL_DMA_COPY_A 0x0000c0b5 209 #define PASCAL_DMA_COPY_B 0x0000c1b5 210 #define VOLTA_DMA_COPY_A 0x0000c3b5 211 #define TURING_DMA_COPY_A 0x0000c5b5 212 #define AMPERE_DMA_COPY_B 0x0000c7b5 213 214 #define FERMI_DECOMPRESS 0x000090b8 215 216 #define NV50_COMPUTE 0x000050c0 217 #define GT214_COMPUTE 0x000085c0 218 #define FERMI_COMPUTE_A 0x000090c0 219 #define FERMI_COMPUTE_B 0x000091c0 220 #define KEPLER_COMPUTE_A 0x0000a0c0 221 #define KEPLER_COMPUTE_B 0x0000a1c0 222 #define MAXWELL_COMPUTE_A 0x0000b0c0 223 #define MAXWELL_COMPUTE_B 0x0000b1c0 224 #define PASCAL_COMPUTE_A 0x0000c0c0 225 #define PASCAL_COMPUTE_B 0x0000c1c0 226 #define VOLTA_COMPUTE_A 0x0000c3c0 227 #define TURING_COMPUTE_A 0x0000c5c0 228 229 #define NV74_CIPHER 0x000074c1 230 #endif 231