1 #ifndef __NVIF_CLASS_H__ 2 #define __NVIF_CLASS_H__ 3 4 /******************************************************************************* 5 * class identifiers 6 ******************************************************************************/ 7 8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 9 #define NV_DEVICE 0x00000080 10 11 #define NV_DMA_FROM_MEMORY 0x00000002 12 #define NV_DMA_TO_MEMORY 0x00000003 13 #define NV_DMA_IN_MEMORY 0x0000003d 14 15 #define FERMI_TWOD_A 0x0000902d 16 17 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x0000903d 18 19 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 20 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 21 22 #define NV04_DISP 0x00000046 23 24 #define NV03_CHANNEL_DMA 0x0000006b 25 #define NV10_CHANNEL_DMA 0x0000006e 26 #define NV17_CHANNEL_DMA 0x0000176e 27 #define NV40_CHANNEL_DMA 0x0000406e 28 #define NV50_CHANNEL_DMA 0x0000506e 29 #define G82_CHANNEL_DMA 0x0000826e 30 31 #define NV50_CHANNEL_GPFIFO 0x0000506f 32 #define G82_CHANNEL_GPFIFO 0x0000826f 33 #define FERMI_CHANNEL_GPFIFO 0x0000906f 34 #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f 35 #define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f 36 37 #define NV50_DISP 0x00005070 38 #define G82_DISP 0x00008270 39 #define GT200_DISP 0x00008370 40 #define GT214_DISP 0x00008570 41 #define GT206_DISP 0x00008870 42 #define GF110_DISP 0x00009070 43 #define GK104_DISP 0x00009170 44 #define GK110_DISP 0x00009270 45 #define GM107_DISP 0x00009470 46 #define GM204_DISP 0x00009570 47 48 #define NV50_DISP_CURSOR 0x0000507a 49 #define G82_DISP_CURSOR 0x0000827a 50 #define GT214_DISP_CURSOR 0x0000857a 51 #define GF110_DISP_CURSOR 0x0000907a 52 #define GK104_DISP_CURSOR 0x0000917a 53 54 #define NV50_DISP_OVERLAY 0x0000507b 55 #define G82_DISP_OVERLAY 0x0000827b 56 #define GT214_DISP_OVERLAY 0x0000857b 57 #define GF110_DISP_OVERLAY 0x0000907b 58 #define GK104_DISP_OVERLAY 0x0000917b 59 60 #define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c 61 #define G82_DISP_BASE_CHANNEL_DMA 0x0000827c 62 #define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c 63 #define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c 64 #define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c 65 #define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c 66 #define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c 67 68 #define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d 69 #define G82_DISP_CORE_CHANNEL_DMA 0x0000827d 70 #define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d 71 #define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d 72 #define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d 73 #define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d 74 #define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d 75 #define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d 76 #define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d 77 #define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d 78 79 #define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e 80 #define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e 81 #define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e 82 #define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e 83 #define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e 84 #define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e 85 86 #define FERMI_A 0x00009097 87 #define FERMI_B 0x00009197 88 #define FERMI_C 0x00009297 89 90 #define KEPLER_A 0x0000a097 91 #define KEPLER_B 0x0000a197 92 #define KEPLER_C 0x0000a297 93 94 #define MAXWELL_A 0x0000b097 95 #define MAXWELL_B 0x0000b197 96 97 #define FERMI_COMPUTE_A 0x000090c0 98 #define FERMI_COMPUTE_B 0x000091c0 99 100 #define KEPLER_COMPUTE_A 0x0000a0c0 101 #define KEPLER_COMPUTE_B 0x0000a1c0 102 103 #define MAXWELL_COMPUTE_A 0x0000b0c0 104 #define MAXWELL_COMPUTE_B 0x0000b1c0 105 106 107 /******************************************************************************* 108 * client 109 ******************************************************************************/ 110 111 #define NV_CLIENT_DEVLIST 0x00 112 113 struct nv_client_devlist_v0 { 114 __u8 version; 115 __u8 count; 116 __u8 pad02[6]; 117 __u64 device[]; 118 }; 119 120 121 /******************************************************************************* 122 * device 123 ******************************************************************************/ 124 125 struct nv_device_v0 { 126 __u8 version; 127 __u8 pad01[7]; 128 __u64 device; /* device identifier, ~0 for client default */ 129 #define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL 130 #define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL 131 #define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL 132 #define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL 133 #define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL 134 #define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL 135 #define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL 136 #define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL 137 #define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL 138 #define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL 139 #define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL 140 #define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL 141 #define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL 142 #define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL 143 #define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL 144 #define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL 145 #define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL 146 #define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL 147 #define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL 148 #define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL 149 #define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL 150 __u64 disable; /* disable particular subsystems */ 151 __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ 152 }; 153 154 #define NV_DEVICE_V0_INFO 0x00 155 156 struct nv_device_info_v0 { 157 __u8 version; 158 #define NV_DEVICE_INFO_V0_IGP 0x00 159 #define NV_DEVICE_INFO_V0_PCI 0x01 160 #define NV_DEVICE_INFO_V0_AGP 0x02 161 #define NV_DEVICE_INFO_V0_PCIE 0x03 162 #define NV_DEVICE_INFO_V0_SOC 0x04 163 __u8 platform; 164 __u16 chipset; /* from NV_PMC_BOOT_0 */ 165 __u8 revision; /* from NV_PMC_BOOT_0 */ 166 #define NV_DEVICE_INFO_V0_TNT 0x01 167 #define NV_DEVICE_INFO_V0_CELSIUS 0x02 168 #define NV_DEVICE_INFO_V0_KELVIN 0x03 169 #define NV_DEVICE_INFO_V0_RANKINE 0x04 170 #define NV_DEVICE_INFO_V0_CURIE 0x05 171 #define NV_DEVICE_INFO_V0_TESLA 0x06 172 #define NV_DEVICE_INFO_V0_FERMI 0x07 173 #define NV_DEVICE_INFO_V0_KEPLER 0x08 174 #define NV_DEVICE_INFO_V0_MAXWELL 0x09 175 __u8 family; 176 __u8 pad06[2]; 177 __u64 ram_size; 178 __u64 ram_user; 179 }; 180 181 182 /******************************************************************************* 183 * context dma 184 ******************************************************************************/ 185 186 struct nv_dma_v0 { 187 __u8 version; 188 #define NV_DMA_V0_TARGET_VM 0x00 189 #define NV_DMA_V0_TARGET_VRAM 0x01 190 #define NV_DMA_V0_TARGET_PCI 0x02 191 #define NV_DMA_V0_TARGET_PCI_US 0x03 192 #define NV_DMA_V0_TARGET_AGP 0x04 193 __u8 target; 194 #define NV_DMA_V0_ACCESS_VM 0x00 195 #define NV_DMA_V0_ACCESS_RD 0x01 196 #define NV_DMA_V0_ACCESS_WR 0x02 197 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 198 __u8 access; 199 __u8 pad03[5]; 200 __u64 start; 201 __u64 limit; 202 /* ... chipset-specific class data */ 203 }; 204 205 struct nv50_dma_v0 { 206 __u8 version; 207 #define NV50_DMA_V0_PRIV_VM 0x00 208 #define NV50_DMA_V0_PRIV_US 0x01 209 #define NV50_DMA_V0_PRIV__S 0x02 210 __u8 priv; 211 #define NV50_DMA_V0_PART_VM 0x00 212 #define NV50_DMA_V0_PART_256 0x01 213 #define NV50_DMA_V0_PART_1KB 0x02 214 __u8 part; 215 #define NV50_DMA_V0_COMP_NONE 0x00 216 #define NV50_DMA_V0_COMP_1 0x01 217 #define NV50_DMA_V0_COMP_2 0x02 218 #define NV50_DMA_V0_COMP_VM 0x03 219 __u8 comp; 220 #define NV50_DMA_V0_KIND_PITCH 0x00 221 #define NV50_DMA_V0_KIND_VM 0x7f 222 __u8 kind; 223 __u8 pad05[3]; 224 }; 225 226 struct gf100_dma_v0 { 227 __u8 version; 228 #define GF100_DMA_V0_PRIV_VM 0x00 229 #define GF100_DMA_V0_PRIV_US 0x01 230 #define GF100_DMA_V0_PRIV__S 0x02 231 __u8 priv; 232 #define GF100_DMA_V0_KIND_PITCH 0x00 233 #define GF100_DMA_V0_KIND_VM 0xff 234 __u8 kind; 235 __u8 pad03[5]; 236 }; 237 238 struct gf110_dma_v0 { 239 __u8 version; 240 #define GF110_DMA_V0_PAGE_LP 0x00 241 #define GF110_DMA_V0_PAGE_SP 0x01 242 __u8 page; 243 #define GF110_DMA_V0_KIND_PITCH 0x00 244 #define GF110_DMA_V0_KIND_VM 0xff 245 __u8 kind; 246 __u8 pad03[5]; 247 }; 248 249 250 /******************************************************************************* 251 * perfmon 252 ******************************************************************************/ 253 254 struct nvif_perfctr_v0 { 255 __u8 version; 256 __u8 pad01[1]; 257 __u16 logic_op; 258 __u8 pad04[4]; 259 char name[4][64]; 260 }; 261 262 #define NVIF_PERFCTR_V0_QUERY 0x00 263 #define NVIF_PERFCTR_V0_SAMPLE 0x01 264 #define NVIF_PERFCTR_V0_READ 0x02 265 266 struct nvif_perfctr_query_v0 { 267 __u8 version; 268 __u8 pad01[3]; 269 __u32 iter; 270 char name[64]; 271 }; 272 273 struct nvif_perfctr_sample { 274 }; 275 276 struct nvif_perfctr_read_v0 { 277 __u8 version; 278 __u8 pad01[7]; 279 __u32 ctr; 280 __u32 clk; 281 }; 282 283 284 /******************************************************************************* 285 * device control 286 ******************************************************************************/ 287 288 #define NVIF_CONTROL_PSTATE_INFO 0x00 289 #define NVIF_CONTROL_PSTATE_ATTR 0x01 290 #define NVIF_CONTROL_PSTATE_USER 0x02 291 292 struct nvif_control_pstate_info_v0 { 293 __u8 version; 294 __u8 count; /* out: number of power states */ 295 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) 296 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) 297 __s8 ustate_ac; /* out: target pstate index */ 298 __s8 ustate_dc; /* out: target pstate index */ 299 __s8 pwrsrc; /* out: current power source */ 300 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) 301 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) 302 __s8 pstate; /* out: current pstate index */ 303 __u8 pad06[2]; 304 }; 305 306 struct nvif_control_pstate_attr_v0 { 307 __u8 version; 308 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) 309 __s8 state; /* in: index of pstate to query 310 * out: pstate identifier 311 */ 312 __u8 index; /* in: index of attribute to query 313 * out: index of next attribute, or 0 if no more 314 */ 315 __u8 pad03[5]; 316 __u32 min; 317 __u32 max; 318 char name[32]; 319 char unit[16]; 320 }; 321 322 struct nvif_control_pstate_user_v0 { 323 __u8 version; 324 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) 325 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) 326 __s8 ustate; /* in: pstate identifier */ 327 __s8 pwrsrc; /* in: target power source */ 328 __u8 pad03[5]; 329 }; 330 331 332 /******************************************************************************* 333 * DMA FIFO channels 334 ******************************************************************************/ 335 336 struct nv03_channel_dma_v0 { 337 __u8 version; 338 __u8 chid; 339 __u8 pad02[2]; 340 __u32 pushbuf; 341 __u64 offset; 342 }; 343 344 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 345 346 /******************************************************************************* 347 * GPFIFO channels 348 ******************************************************************************/ 349 350 struct nv50_channel_gpfifo_v0 { 351 __u8 version; 352 __u8 chid; 353 __u8 pad01[6]; 354 __u32 pushbuf; 355 __u32 ilength; 356 __u64 ioffset; 357 }; 358 359 struct kepler_channel_gpfifo_a_v0 { 360 __u8 version; 361 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 362 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 363 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 364 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 365 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 366 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 367 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 368 __u8 engine; 369 __u16 chid; 370 __u8 pad04[4]; 371 __u32 pushbuf; 372 __u32 ilength; 373 __u64 ioffset; 374 }; 375 376 /******************************************************************************* 377 * legacy display 378 ******************************************************************************/ 379 380 #define NV04_DISP_NTFY_VBLANK 0x00 381 #define NV04_DISP_NTFY_CONN 0x01 382 383 struct nv04_disp_mthd_v0 { 384 __u8 version; 385 #define NV04_DISP_SCANOUTPOS 0x00 386 __u8 method; 387 __u8 head; 388 __u8 pad03[5]; 389 }; 390 391 struct nv04_disp_scanoutpos_v0 { 392 __u8 version; 393 __u8 pad01[7]; 394 __s64 time[2]; 395 __u16 vblanks; 396 __u16 vblanke; 397 __u16 vtotal; 398 __u16 vline; 399 __u16 hblanks; 400 __u16 hblanke; 401 __u16 htotal; 402 __u16 hline; 403 }; 404 405 /******************************************************************************* 406 * display 407 ******************************************************************************/ 408 409 #define NV50_DISP_MTHD 0x00 410 411 struct nv50_disp_mthd_v0 { 412 __u8 version; 413 #define NV50_DISP_SCANOUTPOS 0x00 414 __u8 method; 415 __u8 head; 416 __u8 pad03[5]; 417 }; 418 419 struct nv50_disp_mthd_v1 { 420 __u8 version; 421 #define NV50_DISP_MTHD_V1_DAC_PWR 0x10 422 #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 423 #define NV50_DISP_MTHD_V1_SOR_PWR 0x20 424 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 425 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 426 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 427 #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 428 #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 429 __u8 method; 430 __u16 hasht; 431 __u16 hashm; 432 __u8 pad06[2]; 433 }; 434 435 struct nv50_disp_dac_pwr_v0 { 436 __u8 version; 437 __u8 state; 438 __u8 data; 439 __u8 vsync; 440 __u8 hsync; 441 __u8 pad05[3]; 442 }; 443 444 struct nv50_disp_dac_load_v0 { 445 __u8 version; 446 __u8 load; 447 __u8 pad02[2]; 448 __u32 data; 449 }; 450 451 struct nv50_disp_sor_pwr_v0 { 452 __u8 version; 453 __u8 state; 454 __u8 pad02[6]; 455 }; 456 457 struct nv50_disp_sor_hda_eld_v0 { 458 __u8 version; 459 __u8 pad01[7]; 460 __u8 data[]; 461 }; 462 463 struct nv50_disp_sor_hdmi_pwr_v0 { 464 __u8 version; 465 __u8 state; 466 __u8 max_ac_packet; 467 __u8 rekey; 468 __u8 pad04[4]; 469 }; 470 471 struct nv50_disp_sor_lvds_script_v0 { 472 __u8 version; 473 __u8 pad01[1]; 474 __u16 script; 475 __u8 pad04[4]; 476 }; 477 478 struct nv50_disp_sor_dp_pwr_v0 { 479 __u8 version; 480 __u8 state; 481 __u8 pad02[6]; 482 }; 483 484 struct nv50_disp_pior_pwr_v0 { 485 __u8 version; 486 __u8 state; 487 __u8 type; 488 __u8 pad03[5]; 489 }; 490 491 /* core */ 492 struct nv50_disp_core_channel_dma_v0 { 493 __u8 version; 494 __u8 pad01[3]; 495 __u32 pushbuf; 496 }; 497 498 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 499 500 /* cursor immediate */ 501 struct nv50_disp_cursor_v0 { 502 __u8 version; 503 __u8 head; 504 __u8 pad02[6]; 505 }; 506 507 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 508 509 /* base */ 510 struct nv50_disp_base_channel_dma_v0 { 511 __u8 version; 512 __u8 pad01[2]; 513 __u8 head; 514 __u32 pushbuf; 515 }; 516 517 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 518 519 /* overlay */ 520 struct nv50_disp_overlay_channel_dma_v0 { 521 __u8 version; 522 __u8 pad01[2]; 523 __u8 head; 524 __u32 pushbuf; 525 }; 526 527 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 528 529 /* overlay immediate */ 530 struct nv50_disp_overlay_v0 { 531 __u8 version; 532 __u8 head; 533 __u8 pad02[6]; 534 }; 535 536 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 537 538 /******************************************************************************* 539 * fermi 540 ******************************************************************************/ 541 542 #define FERMI_A_ZBC_COLOR 0x00 543 #define FERMI_A_ZBC_DEPTH 0x01 544 545 struct fermi_a_zbc_color_v0 { 546 __u8 version; 547 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 548 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 549 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 550 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 551 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c 552 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 553 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 554 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 555 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 556 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c 557 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 558 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 559 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 560 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c 561 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 562 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 563 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 564 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c 565 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 566 __u8 format; 567 __u8 index; 568 __u8 pad03[5]; 569 __u32 ds[4]; 570 __u32 l2[4]; 571 }; 572 573 struct fermi_a_zbc_depth_v0 { 574 __u8 version; 575 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 576 __u8 format; 577 __u8 index; 578 __u8 pad03[5]; 579 __u32 ds; 580 __u32 l2; 581 }; 582 583 #endif 584