1 #ifndef __NVIF_CLASS_H__ 2 #define __NVIF_CLASS_H__ 3 4 /******************************************************************************* 5 * class identifiers 6 ******************************************************************************/ 7 8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 9 #define NV_DEVICE 0x00000080 10 11 #define NV_DMA_FROM_MEMORY 0x00000002 12 #define NV_DMA_TO_MEMORY 0x00000003 13 #define NV_DMA_IN_MEMORY 0x0000003d 14 15 #define NV04_DISP 0x00000046 16 17 #define NV03_CHANNEL_DMA 0x0000006b 18 #define NV10_CHANNEL_DMA 0x0000006e 19 #define NV17_CHANNEL_DMA 0x0000176e 20 #define NV40_CHANNEL_DMA 0x0000406e 21 #define NV50_CHANNEL_DMA 0x0000506e 22 #define G82_CHANNEL_DMA 0x0000826e 23 24 #define NV50_CHANNEL_GPFIFO 0x0000506f 25 #define G82_CHANNEL_GPFIFO 0x0000826f 26 #define FERMI_CHANNEL_GPFIFO 0x0000906f 27 #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f 28 29 #define NV50_DISP 0x00005070 30 #define G82_DISP 0x00008270 31 #define GT200_DISP 0x00008370 32 #define GT214_DISP 0x00008570 33 #define GT206_DISP 0x00008870 34 #define GF110_DISP 0x00009070 35 #define GK104_DISP 0x00009170 36 #define GK110_DISP 0x00009270 37 #define GM107_DISP 0x00009470 38 #define GM204_DISP 0x00009570 39 40 #define NV50_DISP_CURSOR 0x0000507a 41 #define G82_DISP_CURSOR 0x0000827a 42 #define GT214_DISP_CURSOR 0x0000857a 43 #define GF110_DISP_CURSOR 0x0000907a 44 #define GK104_DISP_CURSOR 0x0000917a 45 46 #define NV50_DISP_OVERLAY 0x0000507b 47 #define G82_DISP_OVERLAY 0x0000827b 48 #define GT214_DISP_OVERLAY 0x0000857b 49 #define GF110_DISP_OVERLAY 0x0000907b 50 #define GK104_DISP_OVERLAY 0x0000917b 51 52 #define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c 53 #define G82_DISP_BASE_CHANNEL_DMA 0x0000827c 54 #define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c 55 #define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c 56 #define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c 57 #define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c 58 #define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c 59 60 #define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d 61 #define G82_DISP_CORE_CHANNEL_DMA 0x0000827d 62 #define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d 63 #define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d 64 #define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d 65 #define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d 66 #define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d 67 #define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d 68 #define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d 69 #define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d 70 71 #define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e 72 #define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e 73 #define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e 74 #define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e 75 #define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e 76 #define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e 77 78 #define FERMI_A 0x00009097 79 #define FERMI_B 0x00009197 80 #define FERMI_C 0x00009297 81 82 #define KEPLER_A 0x0000a097 83 #define KEPLER_B 0x0000a197 84 #define KEPLER_C 0x0000a297 85 86 #define MAXWELL_A 0x0000b097 87 88 #define FERMI_COMPUTE_A 0x000090c0 89 #define FERMI_COMPUTE_B 0x000091c0 90 91 #define KEPLER_COMPUTE_A 0x0000a0c0 92 #define KEPLER_COMPUTE_B 0x0000a1c0 93 94 #define MAXWELL_COMPUTE_A 0x0000b0c0 95 96 97 /******************************************************************************* 98 * client 99 ******************************************************************************/ 100 101 #define NV_CLIENT_DEVLIST 0x00 102 103 struct nv_client_devlist_v0 { 104 __u8 version; 105 __u8 count; 106 __u8 pad02[6]; 107 __u64 device[]; 108 }; 109 110 111 /******************************************************************************* 112 * device 113 ******************************************************************************/ 114 115 struct nv_device_v0 { 116 __u8 version; 117 __u8 pad01[7]; 118 __u64 device; /* device identifier, ~0 for client default */ 119 #define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL 120 #define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL 121 #define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL 122 #define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL 123 #define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL 124 #define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL 125 #define NV_DEVICE_V0_DISABLE_GR 0x0000000100000000ULL 126 #define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL 127 #define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL 128 #define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL 129 #define NV_DEVICE_V0_DISABLE_CIPHER 0x0000001000000000ULL 130 #define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL 131 #define NV_DEVICE_V0_DISABLE_MSPPP 0x0000004000000000ULL 132 #define NV_DEVICE_V0_DISABLE_CE0 0x0000008000000000ULL 133 #define NV_DEVICE_V0_DISABLE_CE1 0x0000010000000000ULL 134 #define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL 135 #define NV_DEVICE_V0_DISABLE_MSENC 0x0000040000000000ULL 136 #define NV_DEVICE_V0_DISABLE_CE2 0x0000080000000000ULL 137 #define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL 138 #define NV_DEVICE_V0_DISABLE_SEC 0x0000200000000000ULL 139 #define NV_DEVICE_V0_DISABLE_MSPDEC 0x0000400000000000ULL 140 __u64 disable; /* disable particular subsystems */ 141 __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ 142 }; 143 144 #define NV_DEVICE_V0_INFO 0x00 145 146 struct nv_device_info_v0 { 147 __u8 version; 148 #define NV_DEVICE_INFO_V0_IGP 0x00 149 #define NV_DEVICE_INFO_V0_PCI 0x01 150 #define NV_DEVICE_INFO_V0_AGP 0x02 151 #define NV_DEVICE_INFO_V0_PCIE 0x03 152 #define NV_DEVICE_INFO_V0_SOC 0x04 153 __u8 platform; 154 __u16 chipset; /* from NV_PMC_BOOT_0 */ 155 __u8 revision; /* from NV_PMC_BOOT_0 */ 156 #define NV_DEVICE_INFO_V0_TNT 0x01 157 #define NV_DEVICE_INFO_V0_CELSIUS 0x02 158 #define NV_DEVICE_INFO_V0_KELVIN 0x03 159 #define NV_DEVICE_INFO_V0_RANKINE 0x04 160 #define NV_DEVICE_INFO_V0_CURIE 0x05 161 #define NV_DEVICE_INFO_V0_TESLA 0x06 162 #define NV_DEVICE_INFO_V0_FERMI 0x07 163 #define NV_DEVICE_INFO_V0_KEPLER 0x08 164 #define NV_DEVICE_INFO_V0_MAXWELL 0x09 165 __u8 family; 166 __u8 pad06[2]; 167 __u64 ram_size; 168 __u64 ram_user; 169 }; 170 171 172 /******************************************************************************* 173 * context dma 174 ******************************************************************************/ 175 176 struct nv_dma_v0 { 177 __u8 version; 178 #define NV_DMA_V0_TARGET_VM 0x00 179 #define NV_DMA_V0_TARGET_VRAM 0x01 180 #define NV_DMA_V0_TARGET_PCI 0x02 181 #define NV_DMA_V0_TARGET_PCI_US 0x03 182 #define NV_DMA_V0_TARGET_AGP 0x04 183 __u8 target; 184 #define NV_DMA_V0_ACCESS_VM 0x00 185 #define NV_DMA_V0_ACCESS_RD 0x01 186 #define NV_DMA_V0_ACCESS_WR 0x02 187 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 188 __u8 access; 189 __u8 pad03[5]; 190 __u64 start; 191 __u64 limit; 192 /* ... chipset-specific class data */ 193 }; 194 195 struct nv50_dma_v0 { 196 __u8 version; 197 #define NV50_DMA_V0_PRIV_VM 0x00 198 #define NV50_DMA_V0_PRIV_US 0x01 199 #define NV50_DMA_V0_PRIV__S 0x02 200 __u8 priv; 201 #define NV50_DMA_V0_PART_VM 0x00 202 #define NV50_DMA_V0_PART_256 0x01 203 #define NV50_DMA_V0_PART_1KB 0x02 204 __u8 part; 205 #define NV50_DMA_V0_COMP_NONE 0x00 206 #define NV50_DMA_V0_COMP_1 0x01 207 #define NV50_DMA_V0_COMP_2 0x02 208 #define NV50_DMA_V0_COMP_VM 0x03 209 __u8 comp; 210 #define NV50_DMA_V0_KIND_PITCH 0x00 211 #define NV50_DMA_V0_KIND_VM 0x7f 212 __u8 kind; 213 __u8 pad05[3]; 214 }; 215 216 struct gf100_dma_v0 { 217 __u8 version; 218 #define GF100_DMA_V0_PRIV_VM 0x00 219 #define GF100_DMA_V0_PRIV_US 0x01 220 #define GF100_DMA_V0_PRIV__S 0x02 221 __u8 priv; 222 #define GF100_DMA_V0_KIND_PITCH 0x00 223 #define GF100_DMA_V0_KIND_VM 0xff 224 __u8 kind; 225 __u8 pad03[5]; 226 }; 227 228 struct gf110_dma_v0 { 229 __u8 version; 230 #define GF110_DMA_V0_PAGE_LP 0x00 231 #define GF110_DMA_V0_PAGE_SP 0x01 232 __u8 page; 233 #define GF110_DMA_V0_KIND_PITCH 0x00 234 #define GF110_DMA_V0_KIND_VM 0xff 235 __u8 kind; 236 __u8 pad03[5]; 237 }; 238 239 240 /******************************************************************************* 241 * perfmon 242 ******************************************************************************/ 243 244 struct nvif_perfctr_v0 { 245 __u8 version; 246 __u8 pad01[1]; 247 __u16 logic_op; 248 __u8 pad04[4]; 249 char name[4][64]; 250 }; 251 252 #define NVIF_PERFCTR_V0_QUERY 0x00 253 #define NVIF_PERFCTR_V0_SAMPLE 0x01 254 #define NVIF_PERFCTR_V0_READ 0x02 255 256 struct nvif_perfctr_query_v0 { 257 __u8 version; 258 __u8 pad01[3]; 259 __u32 iter; 260 char name[64]; 261 }; 262 263 struct nvif_perfctr_sample { 264 }; 265 266 struct nvif_perfctr_read_v0 { 267 __u8 version; 268 __u8 pad01[7]; 269 __u32 ctr; 270 __u32 clk; 271 }; 272 273 274 /******************************************************************************* 275 * device control 276 ******************************************************************************/ 277 278 #define NVIF_CONTROL_PSTATE_INFO 0x00 279 #define NVIF_CONTROL_PSTATE_ATTR 0x01 280 #define NVIF_CONTROL_PSTATE_USER 0x02 281 282 struct nvif_control_pstate_info_v0 { 283 __u8 version; 284 __u8 count; /* out: number of power states */ 285 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) 286 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) 287 __s8 ustate_ac; /* out: target pstate index */ 288 __s8 ustate_dc; /* out: target pstate index */ 289 __s8 pwrsrc; /* out: current power source */ 290 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) 291 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) 292 __s8 pstate; /* out: current pstate index */ 293 __u8 pad06[2]; 294 }; 295 296 struct nvif_control_pstate_attr_v0 { 297 __u8 version; 298 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) 299 __s8 state; /* in: index of pstate to query 300 * out: pstate identifier 301 */ 302 __u8 index; /* in: index of attribute to query 303 * out: index of next attribute, or 0 if no more 304 */ 305 __u8 pad03[5]; 306 __u32 min; 307 __u32 max; 308 char name[32]; 309 char unit[16]; 310 }; 311 312 struct nvif_control_pstate_user_v0 { 313 __u8 version; 314 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) 315 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) 316 __s8 ustate; /* in: pstate identifier */ 317 __s8 pwrsrc; /* in: target power source */ 318 __u8 pad03[5]; 319 }; 320 321 322 /******************************************************************************* 323 * DMA FIFO channels 324 ******************************************************************************/ 325 326 struct nv03_channel_dma_v0 { 327 __u8 version; 328 __u8 chid; 329 __u8 pad02[2]; 330 __u32 pushbuf; 331 __u64 offset; 332 }; 333 334 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 335 336 /******************************************************************************* 337 * GPFIFO channels 338 ******************************************************************************/ 339 340 struct nv50_channel_gpfifo_v0 { 341 __u8 version; 342 __u8 chid; 343 __u8 pad01[6]; 344 __u32 pushbuf; 345 __u32 ilength; 346 __u64 ioffset; 347 }; 348 349 struct kepler_channel_gpfifo_a_v0 { 350 __u8 version; 351 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 352 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 353 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 354 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 355 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 356 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 357 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 358 __u8 engine; 359 __u16 chid; 360 __u8 pad04[4]; 361 __u32 pushbuf; 362 __u32 ilength; 363 __u64 ioffset; 364 }; 365 366 /******************************************************************************* 367 * legacy display 368 ******************************************************************************/ 369 370 #define NV04_DISP_NTFY_VBLANK 0x00 371 #define NV04_DISP_NTFY_CONN 0x01 372 373 struct nv04_disp_mthd_v0 { 374 __u8 version; 375 #define NV04_DISP_SCANOUTPOS 0x00 376 __u8 method; 377 __u8 head; 378 __u8 pad03[5]; 379 }; 380 381 struct nv04_disp_scanoutpos_v0 { 382 __u8 version; 383 __u8 pad01[7]; 384 __s64 time[2]; 385 __u16 vblanks; 386 __u16 vblanke; 387 __u16 vtotal; 388 __u16 vline; 389 __u16 hblanks; 390 __u16 hblanke; 391 __u16 htotal; 392 __u16 hline; 393 }; 394 395 /******************************************************************************* 396 * display 397 ******************************************************************************/ 398 399 #define NV50_DISP_MTHD 0x00 400 401 struct nv50_disp_mthd_v0 { 402 __u8 version; 403 #define NV50_DISP_SCANOUTPOS 0x00 404 __u8 method; 405 __u8 head; 406 __u8 pad03[5]; 407 }; 408 409 struct nv50_disp_mthd_v1 { 410 __u8 version; 411 #define NV50_DISP_MTHD_V1_DAC_PWR 0x10 412 #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 413 #define NV50_DISP_MTHD_V1_SOR_PWR 0x20 414 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 415 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 416 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 417 #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 418 #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 419 __u8 method; 420 __u16 hasht; 421 __u16 hashm; 422 __u8 pad06[2]; 423 }; 424 425 struct nv50_disp_dac_pwr_v0 { 426 __u8 version; 427 __u8 state; 428 __u8 data; 429 __u8 vsync; 430 __u8 hsync; 431 __u8 pad05[3]; 432 }; 433 434 struct nv50_disp_dac_load_v0 { 435 __u8 version; 436 __u8 load; 437 __u8 pad02[2]; 438 __u32 data; 439 }; 440 441 struct nv50_disp_sor_pwr_v0 { 442 __u8 version; 443 __u8 state; 444 __u8 pad02[6]; 445 }; 446 447 struct nv50_disp_sor_hda_eld_v0 { 448 __u8 version; 449 __u8 pad01[7]; 450 __u8 data[]; 451 }; 452 453 struct nv50_disp_sor_hdmi_pwr_v0 { 454 __u8 version; 455 __u8 state; 456 __u8 max_ac_packet; 457 __u8 rekey; 458 __u8 pad04[4]; 459 }; 460 461 struct nv50_disp_sor_lvds_script_v0 { 462 __u8 version; 463 __u8 pad01[1]; 464 __u16 script; 465 __u8 pad04[4]; 466 }; 467 468 struct nv50_disp_sor_dp_pwr_v0 { 469 __u8 version; 470 __u8 state; 471 __u8 pad02[6]; 472 }; 473 474 struct nv50_disp_pior_pwr_v0 { 475 __u8 version; 476 __u8 state; 477 __u8 type; 478 __u8 pad03[5]; 479 }; 480 481 /* core */ 482 struct nv50_disp_core_channel_dma_v0 { 483 __u8 version; 484 __u8 pad01[3]; 485 __u32 pushbuf; 486 }; 487 488 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 489 490 /* cursor immediate */ 491 struct nv50_disp_cursor_v0 { 492 __u8 version; 493 __u8 head; 494 __u8 pad02[6]; 495 }; 496 497 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 498 499 /* base */ 500 struct nv50_disp_base_channel_dma_v0 { 501 __u8 version; 502 __u8 pad01[2]; 503 __u8 head; 504 __u32 pushbuf; 505 }; 506 507 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 508 509 /* overlay */ 510 struct nv50_disp_overlay_channel_dma_v0 { 511 __u8 version; 512 __u8 pad01[2]; 513 __u8 head; 514 __u32 pushbuf; 515 }; 516 517 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 518 519 /* overlay immediate */ 520 struct nv50_disp_overlay_v0 { 521 __u8 version; 522 __u8 head; 523 __u8 pad02[6]; 524 }; 525 526 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 527 528 /******************************************************************************* 529 * fermi 530 ******************************************************************************/ 531 532 #define FERMI_A_ZBC_COLOR 0x00 533 #define FERMI_A_ZBC_DEPTH 0x01 534 535 struct fermi_a_zbc_color_v0 { 536 __u8 version; 537 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 538 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 539 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 540 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 541 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c 542 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 543 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 544 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 545 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 546 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c 547 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 548 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 549 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 550 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c 551 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 552 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 553 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 554 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c 555 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 556 __u8 format; 557 __u8 index; 558 __u8 pad03[5]; 559 __u32 ds[4]; 560 __u32 l2[4]; 561 }; 562 563 struct fermi_a_zbc_depth_v0 { 564 __u8 version; 565 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 566 __u8 format; 567 __u8 index; 568 __u8 pad03[5]; 569 __u32 ds; 570 __u32 l2; 571 }; 572 573 #endif 574