1 #ifndef __NVIF_CLASS_H__ 2 #define __NVIF_CLASS_H__ 3 4 /******************************************************************************* 5 * class identifiers 6 ******************************************************************************/ 7 8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 9 #define NV_DEVICE 0x00000080 10 11 #define NV_DMA_FROM_MEMORY 0x00000002 12 #define NV_DMA_TO_MEMORY 0x00000003 13 #define NV_DMA_IN_MEMORY 0x0000003d 14 15 #define FERMI_TWOD_A 0x0000902d 16 17 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 18 19 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 20 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 21 22 #define NV04_DISP 0x00000046 23 24 #define NV03_CHANNEL_DMA 0x0000006b 25 #define NV10_CHANNEL_DMA 0x0000006e 26 #define NV17_CHANNEL_DMA 0x0000176e 27 #define NV40_CHANNEL_DMA 0x0000406e 28 #define NV50_CHANNEL_DMA 0x0000506e 29 #define G82_CHANNEL_DMA 0x0000826e 30 31 #define NV50_CHANNEL_GPFIFO 0x0000506f 32 #define G82_CHANNEL_GPFIFO 0x0000826f 33 #define FERMI_CHANNEL_GPFIFO 0x0000906f 34 #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f 35 #define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f 36 37 #define NV50_DISP 0x00005070 38 #define G82_DISP 0x00008270 39 #define GT200_DISP 0x00008370 40 #define GT214_DISP 0x00008570 41 #define GT206_DISP 0x00008870 42 #define GF110_DISP 0x00009070 43 #define GK104_DISP 0x00009170 44 #define GK110_DISP 0x00009270 45 #define GM107_DISP 0x00009470 46 #define GM204_DISP 0x00009570 47 48 #define NV74_VP2 0x00007476 49 50 #define NV50_DISP_CURSOR 0x0000507a 51 #define G82_DISP_CURSOR 0x0000827a 52 #define GT214_DISP_CURSOR 0x0000857a 53 #define GF110_DISP_CURSOR 0x0000907a 54 #define GK104_DISP_CURSOR 0x0000917a 55 56 #define NV50_DISP_OVERLAY 0x0000507b 57 #define G82_DISP_OVERLAY 0x0000827b 58 #define GT214_DISP_OVERLAY 0x0000857b 59 #define GF110_DISP_OVERLAY 0x0000907b 60 #define GK104_DISP_OVERLAY 0x0000917b 61 62 #define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c 63 #define G82_DISP_BASE_CHANNEL_DMA 0x0000827c 64 #define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c 65 #define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c 66 #define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c 67 #define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c 68 #define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c 69 70 #define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d 71 #define G82_DISP_CORE_CHANNEL_DMA 0x0000827d 72 #define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d 73 #define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d 74 #define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d 75 #define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d 76 #define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d 77 #define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d 78 #define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d 79 #define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d 80 81 #define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e 82 #define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e 83 #define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e 84 #define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e 85 #define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e 86 #define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e 87 88 #define FERMI_A 0x00009097 89 #define FERMI_B 0x00009197 90 #define FERMI_C 0x00009297 91 92 #define KEPLER_A 0x0000a097 93 #define KEPLER_B 0x0000a197 94 #define KEPLER_C 0x0000a297 95 96 #define MAXWELL_A 0x0000b097 97 #define MAXWELL_B 0x0000b197 98 99 #define NV74_BSP 0x000074b0 100 101 #define GT212_MSVLD 0x000085b1 102 #define IGT21A_MSVLD 0x000086b1 103 #define G98_MSVLD 0x000088b1 104 #define GF100_MSVLD 0x000090b1 105 #define GK104_MSVLD 0x000095b1 106 107 #define GT212_MSPDEC 0x000085b2 108 #define G98_MSPDEC 0x000088b2 109 #define GF100_MSPDEC 0x000090b2 110 #define GK104_MSPDEC 0x000095b2 111 112 #define GT212_MSPPP 0x000085b3 113 #define G98_MSPPP 0x000088b3 114 #define GF100_MSPPP 0x000090b3 115 116 #define G98_SEC 0x000088b4 117 118 #define GT212_DMA 0x000085b5 119 #define FERMI_DMA 0x000090b5 120 #define KEPLER_DMA_COPY_A 0x0000a0b5 121 #define MAXWELL_DMA_COPY_A 0x0000b0b5 122 123 #define FERMI_DECOMPRESS 0x000090b8 124 125 #define FERMI_COMPUTE_A 0x000090c0 126 #define FERMI_COMPUTE_B 0x000091c0 127 #define KEPLER_COMPUTE_A 0x0000a0c0 128 #define KEPLER_COMPUTE_B 0x0000a1c0 129 #define MAXWELL_COMPUTE_A 0x0000b0c0 130 #define MAXWELL_COMPUTE_B 0x0000b1c0 131 132 #define NV74_CIPHER 0x000074c1 133 134 /******************************************************************************* 135 * client 136 ******************************************************************************/ 137 138 #define NV_CLIENT_DEVLIST 0x00 139 140 struct nv_client_devlist_v0 { 141 __u8 version; 142 __u8 count; 143 __u8 pad02[6]; 144 __u64 device[]; 145 }; 146 147 148 /******************************************************************************* 149 * device 150 ******************************************************************************/ 151 152 struct nv_device_v0 { 153 __u8 version; 154 __u8 pad01[7]; 155 __u64 device; /* device identifier, ~0 for client default */ 156 }; 157 158 #define NV_DEVICE_V0_INFO 0x00 159 #define NV_DEVICE_V0_TIME 0x01 160 161 struct nv_device_info_v0 { 162 __u8 version; 163 #define NV_DEVICE_INFO_V0_IGP 0x00 164 #define NV_DEVICE_INFO_V0_PCI 0x01 165 #define NV_DEVICE_INFO_V0_AGP 0x02 166 #define NV_DEVICE_INFO_V0_PCIE 0x03 167 #define NV_DEVICE_INFO_V0_SOC 0x04 168 __u8 platform; 169 __u16 chipset; /* from NV_PMC_BOOT_0 */ 170 __u8 revision; /* from NV_PMC_BOOT_0 */ 171 #define NV_DEVICE_INFO_V0_TNT 0x01 172 #define NV_DEVICE_INFO_V0_CELSIUS 0x02 173 #define NV_DEVICE_INFO_V0_KELVIN 0x03 174 #define NV_DEVICE_INFO_V0_RANKINE 0x04 175 #define NV_DEVICE_INFO_V0_CURIE 0x05 176 #define NV_DEVICE_INFO_V0_TESLA 0x06 177 #define NV_DEVICE_INFO_V0_FERMI 0x07 178 #define NV_DEVICE_INFO_V0_KEPLER 0x08 179 #define NV_DEVICE_INFO_V0_MAXWELL 0x09 180 __u8 family; 181 __u8 pad06[2]; 182 __u64 ram_size; 183 __u64 ram_user; 184 char chip[16]; 185 char name[64]; 186 }; 187 188 struct nv_device_time_v0 { 189 __u8 version; 190 __u8 pad01[7]; 191 __u64 time; 192 }; 193 194 195 /******************************************************************************* 196 * context dma 197 ******************************************************************************/ 198 199 struct nv_dma_v0 { 200 __u8 version; 201 #define NV_DMA_V0_TARGET_VM 0x00 202 #define NV_DMA_V0_TARGET_VRAM 0x01 203 #define NV_DMA_V0_TARGET_PCI 0x02 204 #define NV_DMA_V0_TARGET_PCI_US 0x03 205 #define NV_DMA_V0_TARGET_AGP 0x04 206 __u8 target; 207 #define NV_DMA_V0_ACCESS_VM 0x00 208 #define NV_DMA_V0_ACCESS_RD 0x01 209 #define NV_DMA_V0_ACCESS_WR 0x02 210 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 211 __u8 access; 212 __u8 pad03[5]; 213 __u64 start; 214 __u64 limit; 215 /* ... chipset-specific class data */ 216 }; 217 218 struct nv50_dma_v0 { 219 __u8 version; 220 #define NV50_DMA_V0_PRIV_VM 0x00 221 #define NV50_DMA_V0_PRIV_US 0x01 222 #define NV50_DMA_V0_PRIV__S 0x02 223 __u8 priv; 224 #define NV50_DMA_V0_PART_VM 0x00 225 #define NV50_DMA_V0_PART_256 0x01 226 #define NV50_DMA_V0_PART_1KB 0x02 227 __u8 part; 228 #define NV50_DMA_V0_COMP_NONE 0x00 229 #define NV50_DMA_V0_COMP_1 0x01 230 #define NV50_DMA_V0_COMP_2 0x02 231 #define NV50_DMA_V0_COMP_VM 0x03 232 __u8 comp; 233 #define NV50_DMA_V0_KIND_PITCH 0x00 234 #define NV50_DMA_V0_KIND_VM 0x7f 235 __u8 kind; 236 __u8 pad05[3]; 237 }; 238 239 struct gf100_dma_v0 { 240 __u8 version; 241 #define GF100_DMA_V0_PRIV_VM 0x00 242 #define GF100_DMA_V0_PRIV_US 0x01 243 #define GF100_DMA_V0_PRIV__S 0x02 244 __u8 priv; 245 #define GF100_DMA_V0_KIND_PITCH 0x00 246 #define GF100_DMA_V0_KIND_VM 0xff 247 __u8 kind; 248 __u8 pad03[5]; 249 }; 250 251 struct gf110_dma_v0 { 252 __u8 version; 253 #define GF110_DMA_V0_PAGE_LP 0x00 254 #define GF110_DMA_V0_PAGE_SP 0x01 255 __u8 page; 256 #define GF110_DMA_V0_KIND_PITCH 0x00 257 #define GF110_DMA_V0_KIND_VM 0xff 258 __u8 kind; 259 __u8 pad03[5]; 260 }; 261 262 263 /******************************************************************************* 264 * perfmon 265 ******************************************************************************/ 266 267 #define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00 268 #define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01 269 #define NVIF_PERFMON_V0_QUERY_SOURCE 0x02 270 271 struct nvif_perfmon_query_domain_v0 { 272 __u8 version; 273 __u8 id; 274 __u8 counter_nr; 275 __u8 iter; 276 __u16 signal_nr; 277 __u8 pad05[2]; 278 char name[64]; 279 }; 280 281 struct nvif_perfmon_query_signal_v0 { 282 __u8 version; 283 __u8 domain; 284 __u16 iter; 285 __u8 signal; 286 __u8 source_nr; 287 __u8 pad05[2]; 288 char name[64]; 289 }; 290 291 struct nvif_perfmon_query_source_v0 { 292 __u8 version; 293 __u8 domain; 294 __u8 signal; 295 __u8 iter; 296 __u8 pad04[4]; 297 __u32 source; 298 __u32 mask; 299 char name[64]; 300 }; 301 302 303 /******************************************************************************* 304 * perfdom 305 ******************************************************************************/ 306 307 struct nvif_perfdom_v0 { 308 __u8 version; 309 __u8 domain; 310 __u8 mode; 311 __u8 pad03[1]; 312 struct { 313 __u8 signal[4]; 314 __u64 source[4][8]; 315 __u16 logic_op; 316 } ctr[4]; 317 }; 318 319 #define NVIF_PERFDOM_V0_INIT 0x00 320 #define NVIF_PERFDOM_V0_SAMPLE 0x01 321 #define NVIF_PERFDOM_V0_READ 0x02 322 323 struct nvif_perfdom_init { 324 }; 325 326 struct nvif_perfdom_sample { 327 }; 328 329 struct nvif_perfdom_read_v0 { 330 __u8 version; 331 __u8 pad01[7]; 332 __u32 ctr[4]; 333 __u32 clk; 334 __u8 pad04[4]; 335 }; 336 337 338 /******************************************************************************* 339 * device control 340 ******************************************************************************/ 341 342 #define NVIF_CONTROL_PSTATE_INFO 0x00 343 #define NVIF_CONTROL_PSTATE_ATTR 0x01 344 #define NVIF_CONTROL_PSTATE_USER 0x02 345 346 struct nvif_control_pstate_info_v0 { 347 __u8 version; 348 __u8 count; /* out: number of power states */ 349 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) 350 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) 351 __s8 ustate_ac; /* out: target pstate index */ 352 __s8 ustate_dc; /* out: target pstate index */ 353 __s8 pwrsrc; /* out: current power source */ 354 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) 355 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) 356 __s8 pstate; /* out: current pstate index */ 357 __u8 pad06[2]; 358 }; 359 360 struct nvif_control_pstate_attr_v0 { 361 __u8 version; 362 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) 363 __s8 state; /* in: index of pstate to query 364 * out: pstate identifier 365 */ 366 __u8 index; /* in: index of attribute to query 367 * out: index of next attribute, or 0 if no more 368 */ 369 __u8 pad03[5]; 370 __u32 min; 371 __u32 max; 372 char name[32]; 373 char unit[16]; 374 }; 375 376 struct nvif_control_pstate_user_v0 { 377 __u8 version; 378 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) 379 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) 380 __s8 ustate; /* in: pstate identifier */ 381 __s8 pwrsrc; /* in: target power source */ 382 __u8 pad03[5]; 383 }; 384 385 386 /******************************************************************************* 387 * DMA FIFO channels 388 ******************************************************************************/ 389 390 struct nv03_channel_dma_v0 { 391 __u8 version; 392 __u8 chid; 393 __u8 pad02[2]; 394 __u32 offset; 395 __u64 pushbuf; 396 }; 397 398 struct nv50_channel_dma_v0 { 399 __u8 version; 400 __u8 chid; 401 __u8 pad02[6]; 402 __u64 vm; 403 __u64 pushbuf; 404 __u64 offset; 405 }; 406 407 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 408 409 /******************************************************************************* 410 * GPFIFO channels 411 ******************************************************************************/ 412 413 struct nv50_channel_gpfifo_v0 { 414 __u8 version; 415 __u8 chid; 416 __u8 pad02[2]; 417 __u32 ilength; 418 __u64 ioffset; 419 __u64 pushbuf; 420 __u64 vm; 421 }; 422 423 struct fermi_channel_gpfifo_v0 { 424 __u8 version; 425 __u8 chid; 426 __u8 pad02[2]; 427 __u32 ilength; 428 __u64 ioffset; 429 __u64 vm; 430 }; 431 432 struct kepler_channel_gpfifo_a_v0 { 433 __u8 version; 434 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 435 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 436 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 437 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 438 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 439 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 440 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 441 __u8 engine; 442 __u16 chid; 443 __u32 ilength; 444 __u64 ioffset; 445 __u64 vm; 446 }; 447 448 /******************************************************************************* 449 * legacy display 450 ******************************************************************************/ 451 452 #define NV04_DISP_NTFY_VBLANK 0x00 453 #define NV04_DISP_NTFY_CONN 0x01 454 455 struct nv04_disp_mthd_v0 { 456 __u8 version; 457 #define NV04_DISP_SCANOUTPOS 0x00 458 __u8 method; 459 __u8 head; 460 __u8 pad03[5]; 461 }; 462 463 struct nv04_disp_scanoutpos_v0 { 464 __u8 version; 465 __u8 pad01[7]; 466 __s64 time[2]; 467 __u16 vblanks; 468 __u16 vblanke; 469 __u16 vtotal; 470 __u16 vline; 471 __u16 hblanks; 472 __u16 hblanke; 473 __u16 htotal; 474 __u16 hline; 475 }; 476 477 /******************************************************************************* 478 * display 479 ******************************************************************************/ 480 481 #define NV50_DISP_MTHD 0x00 482 483 struct nv50_disp_mthd_v0 { 484 __u8 version; 485 #define NV50_DISP_SCANOUTPOS 0x00 486 __u8 method; 487 __u8 head; 488 __u8 pad03[5]; 489 }; 490 491 struct nv50_disp_mthd_v1 { 492 __u8 version; 493 #define NV50_DISP_MTHD_V1_DAC_PWR 0x10 494 #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 495 #define NV50_DISP_MTHD_V1_SOR_PWR 0x20 496 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 497 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 498 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 499 #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 500 #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 501 __u8 method; 502 __u16 hasht; 503 __u16 hashm; 504 __u8 pad06[2]; 505 }; 506 507 struct nv50_disp_dac_pwr_v0 { 508 __u8 version; 509 __u8 state; 510 __u8 data; 511 __u8 vsync; 512 __u8 hsync; 513 __u8 pad05[3]; 514 }; 515 516 struct nv50_disp_dac_load_v0 { 517 __u8 version; 518 __u8 load; 519 __u8 pad02[2]; 520 __u32 data; 521 }; 522 523 struct nv50_disp_sor_pwr_v0 { 524 __u8 version; 525 __u8 state; 526 __u8 pad02[6]; 527 }; 528 529 struct nv50_disp_sor_hda_eld_v0 { 530 __u8 version; 531 __u8 pad01[7]; 532 __u8 data[]; 533 }; 534 535 struct nv50_disp_sor_hdmi_pwr_v0 { 536 __u8 version; 537 __u8 state; 538 __u8 max_ac_packet; 539 __u8 rekey; 540 __u8 pad04[4]; 541 }; 542 543 struct nv50_disp_sor_lvds_script_v0 { 544 __u8 version; 545 __u8 pad01[1]; 546 __u16 script; 547 __u8 pad04[4]; 548 }; 549 550 struct nv50_disp_sor_dp_pwr_v0 { 551 __u8 version; 552 __u8 state; 553 __u8 pad02[6]; 554 }; 555 556 struct nv50_disp_pior_pwr_v0 { 557 __u8 version; 558 __u8 state; 559 __u8 type; 560 __u8 pad03[5]; 561 }; 562 563 /* core */ 564 struct nv50_disp_core_channel_dma_v0 { 565 __u8 version; 566 __u8 pad01[7]; 567 __u64 pushbuf; 568 }; 569 570 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 571 572 /* cursor immediate */ 573 struct nv50_disp_cursor_v0 { 574 __u8 version; 575 __u8 head; 576 __u8 pad02[6]; 577 }; 578 579 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 580 581 /* base */ 582 struct nv50_disp_base_channel_dma_v0 { 583 __u8 version; 584 __u8 head; 585 __u8 pad02[6]; 586 __u64 pushbuf; 587 }; 588 589 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 590 591 /* overlay */ 592 struct nv50_disp_overlay_channel_dma_v0 { 593 __u8 version; 594 __u8 head; 595 __u8 pad02[6]; 596 __u64 pushbuf; 597 }; 598 599 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 600 601 /* overlay immediate */ 602 struct nv50_disp_overlay_v0 { 603 __u8 version; 604 __u8 head; 605 __u8 pad02[6]; 606 }; 607 608 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 609 610 /******************************************************************************* 611 * software 612 ******************************************************************************/ 613 614 #define NVSW_NTFY_UEVENT 0x00 615 616 #define NV04_NVSW_GET_REF 0x00 617 618 struct nv04_nvsw_get_ref_v0 { 619 __u8 version; 620 __u8 pad01[3]; 621 __u32 ref; 622 }; 623 624 /******************************************************************************* 625 * fermi 626 ******************************************************************************/ 627 628 #define FERMI_A_ZBC_COLOR 0x00 629 #define FERMI_A_ZBC_DEPTH 0x01 630 631 struct fermi_a_zbc_color_v0 { 632 __u8 version; 633 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 634 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 635 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 636 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 637 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c 638 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 639 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 640 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 641 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 642 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c 643 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 644 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 645 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 646 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c 647 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 648 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 649 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 650 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c 651 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 652 __u8 format; 653 __u8 index; 654 __u8 pad03[5]; 655 __u32 ds[4]; 656 __u32 l2[4]; 657 }; 658 659 struct fermi_a_zbc_depth_v0 { 660 __u8 version; 661 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 662 __u8 format; 663 __u8 index; 664 __u8 pad03[5]; 665 __u32 ds; 666 __u32 l2; 667 }; 668 669 #endif 670