1 #ifndef __NVIF_CLASS_H__ 2 #define __NVIF_CLASS_H__ 3 4 /******************************************************************************* 5 * class identifiers 6 ******************************************************************************/ 7 8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */ 9 #define NV_DEVICE 0x00000080 10 11 #define NV_DMA_FROM_MEMORY 0x00000002 12 #define NV_DMA_TO_MEMORY 0x00000003 13 #define NV_DMA_IN_MEMORY 0x0000003d 14 15 #define FERMI_TWOD_A 0x0000902d 16 17 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 18 19 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 20 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 21 22 #define NV04_DISP 0x00000046 23 24 #define NV03_CHANNEL_DMA 0x0000006b 25 #define NV10_CHANNEL_DMA 0x0000006e 26 #define NV17_CHANNEL_DMA 0x0000176e 27 #define NV40_CHANNEL_DMA 0x0000406e 28 #define NV50_CHANNEL_DMA 0x0000506e 29 #define G82_CHANNEL_DMA 0x0000826e 30 31 #define NV50_CHANNEL_GPFIFO 0x0000506f 32 #define G82_CHANNEL_GPFIFO 0x0000826f 33 #define FERMI_CHANNEL_GPFIFO 0x0000906f 34 #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f 35 #define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f 36 37 #define NV50_DISP 0x00005070 38 #define G82_DISP 0x00008270 39 #define GT200_DISP 0x00008370 40 #define GT214_DISP 0x00008570 41 #define GT206_DISP 0x00008870 42 #define GF110_DISP 0x00009070 43 #define GK104_DISP 0x00009170 44 #define GK110_DISP 0x00009270 45 #define GM107_DISP 0x00009470 46 #define GM204_DISP 0x00009570 47 48 #define NV50_DISP_CURSOR 0x0000507a 49 #define G82_DISP_CURSOR 0x0000827a 50 #define GT214_DISP_CURSOR 0x0000857a 51 #define GF110_DISP_CURSOR 0x0000907a 52 #define GK104_DISP_CURSOR 0x0000917a 53 54 #define NV50_DISP_OVERLAY 0x0000507b 55 #define G82_DISP_OVERLAY 0x0000827b 56 #define GT214_DISP_OVERLAY 0x0000857b 57 #define GF110_DISP_OVERLAY 0x0000907b 58 #define GK104_DISP_OVERLAY 0x0000917b 59 60 #define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c 61 #define G82_DISP_BASE_CHANNEL_DMA 0x0000827c 62 #define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c 63 #define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c 64 #define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c 65 #define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c 66 #define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c 67 68 #define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d 69 #define G82_DISP_CORE_CHANNEL_DMA 0x0000827d 70 #define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d 71 #define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d 72 #define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d 73 #define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d 74 #define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d 75 #define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d 76 #define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d 77 #define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d 78 79 #define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e 80 #define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e 81 #define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e 82 #define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e 83 #define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e 84 #define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e 85 86 #define FERMI_A 0x00009097 87 #define FERMI_B 0x00009197 88 #define FERMI_C 0x00009297 89 90 #define KEPLER_A 0x0000a097 91 #define KEPLER_B 0x0000a197 92 #define KEPLER_C 0x0000a297 93 94 #define MAXWELL_A 0x0000b097 95 #define MAXWELL_B 0x0000b197 96 97 #define FERMI_COMPUTE_A 0x000090c0 98 #define FERMI_COMPUTE_B 0x000091c0 99 100 #define KEPLER_COMPUTE_A 0x0000a0c0 101 #define KEPLER_COMPUTE_B 0x0000a1c0 102 103 #define MAXWELL_COMPUTE_A 0x0000b0c0 104 #define MAXWELL_COMPUTE_B 0x0000b1c0 105 106 107 /******************************************************************************* 108 * client 109 ******************************************************************************/ 110 111 #define NV_CLIENT_DEVLIST 0x00 112 113 struct nv_client_devlist_v0 { 114 __u8 version; 115 __u8 count; 116 __u8 pad02[6]; 117 __u64 device[]; 118 }; 119 120 121 /******************************************************************************* 122 * device 123 ******************************************************************************/ 124 125 struct nv_device_v0 { 126 __u8 version; 127 __u8 pad01[7]; 128 __u64 device; /* device identifier, ~0 for client default */ 129 }; 130 131 #define NV_DEVICE_V0_INFO 0x00 132 #define NV_DEVICE_V0_TIME 0x01 133 134 struct nv_device_info_v0 { 135 __u8 version; 136 #define NV_DEVICE_INFO_V0_IGP 0x00 137 #define NV_DEVICE_INFO_V0_PCI 0x01 138 #define NV_DEVICE_INFO_V0_AGP 0x02 139 #define NV_DEVICE_INFO_V0_PCIE 0x03 140 #define NV_DEVICE_INFO_V0_SOC 0x04 141 __u8 platform; 142 __u16 chipset; /* from NV_PMC_BOOT_0 */ 143 __u8 revision; /* from NV_PMC_BOOT_0 */ 144 #define NV_DEVICE_INFO_V0_TNT 0x01 145 #define NV_DEVICE_INFO_V0_CELSIUS 0x02 146 #define NV_DEVICE_INFO_V0_KELVIN 0x03 147 #define NV_DEVICE_INFO_V0_RANKINE 0x04 148 #define NV_DEVICE_INFO_V0_CURIE 0x05 149 #define NV_DEVICE_INFO_V0_TESLA 0x06 150 #define NV_DEVICE_INFO_V0_FERMI 0x07 151 #define NV_DEVICE_INFO_V0_KEPLER 0x08 152 #define NV_DEVICE_INFO_V0_MAXWELL 0x09 153 __u8 family; 154 __u8 pad06[2]; 155 __u64 ram_size; 156 __u64 ram_user; 157 char chip[16]; 158 char name[64]; 159 }; 160 161 struct nv_device_time_v0 { 162 __u8 version; 163 __u8 pad01[7]; 164 __u64 time; 165 }; 166 167 168 /******************************************************************************* 169 * context dma 170 ******************************************************************************/ 171 172 struct nv_dma_v0 { 173 __u8 version; 174 #define NV_DMA_V0_TARGET_VM 0x00 175 #define NV_DMA_V0_TARGET_VRAM 0x01 176 #define NV_DMA_V0_TARGET_PCI 0x02 177 #define NV_DMA_V0_TARGET_PCI_US 0x03 178 #define NV_DMA_V0_TARGET_AGP 0x04 179 __u8 target; 180 #define NV_DMA_V0_ACCESS_VM 0x00 181 #define NV_DMA_V0_ACCESS_RD 0x01 182 #define NV_DMA_V0_ACCESS_WR 0x02 183 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) 184 __u8 access; 185 __u8 pad03[5]; 186 __u64 start; 187 __u64 limit; 188 /* ... chipset-specific class data */ 189 }; 190 191 struct nv50_dma_v0 { 192 __u8 version; 193 #define NV50_DMA_V0_PRIV_VM 0x00 194 #define NV50_DMA_V0_PRIV_US 0x01 195 #define NV50_DMA_V0_PRIV__S 0x02 196 __u8 priv; 197 #define NV50_DMA_V0_PART_VM 0x00 198 #define NV50_DMA_V0_PART_256 0x01 199 #define NV50_DMA_V0_PART_1KB 0x02 200 __u8 part; 201 #define NV50_DMA_V0_COMP_NONE 0x00 202 #define NV50_DMA_V0_COMP_1 0x01 203 #define NV50_DMA_V0_COMP_2 0x02 204 #define NV50_DMA_V0_COMP_VM 0x03 205 __u8 comp; 206 #define NV50_DMA_V0_KIND_PITCH 0x00 207 #define NV50_DMA_V0_KIND_VM 0x7f 208 __u8 kind; 209 __u8 pad05[3]; 210 }; 211 212 struct gf100_dma_v0 { 213 __u8 version; 214 #define GF100_DMA_V0_PRIV_VM 0x00 215 #define GF100_DMA_V0_PRIV_US 0x01 216 #define GF100_DMA_V0_PRIV__S 0x02 217 __u8 priv; 218 #define GF100_DMA_V0_KIND_PITCH 0x00 219 #define GF100_DMA_V0_KIND_VM 0xff 220 __u8 kind; 221 __u8 pad03[5]; 222 }; 223 224 struct gf110_dma_v0 { 225 __u8 version; 226 #define GF110_DMA_V0_PAGE_LP 0x00 227 #define GF110_DMA_V0_PAGE_SP 0x01 228 __u8 page; 229 #define GF110_DMA_V0_KIND_PITCH 0x00 230 #define GF110_DMA_V0_KIND_VM 0xff 231 __u8 kind; 232 __u8 pad03[5]; 233 }; 234 235 236 /******************************************************************************* 237 * perfmon 238 ******************************************************************************/ 239 240 #define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00 241 #define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01 242 #define NVIF_PERFMON_V0_QUERY_SOURCE 0x02 243 244 struct nvif_perfmon_query_domain_v0 { 245 __u8 version; 246 __u8 id; 247 __u8 counter_nr; 248 __u8 iter; 249 __u16 signal_nr; 250 __u8 pad05[2]; 251 char name[64]; 252 }; 253 254 struct nvif_perfmon_query_signal_v0 { 255 __u8 version; 256 __u8 domain; 257 __u16 iter; 258 __u8 signal; 259 __u8 source_nr; 260 __u8 pad05[2]; 261 char name[64]; 262 }; 263 264 struct nvif_perfmon_query_source_v0 { 265 __u8 version; 266 __u8 domain; 267 __u8 signal; 268 __u8 iter; 269 __u8 pad04[4]; 270 __u32 source; 271 __u32 mask; 272 char name[64]; 273 }; 274 275 276 /******************************************************************************* 277 * perfdom 278 ******************************************************************************/ 279 280 struct nvif_perfdom_v0 { 281 __u8 version; 282 __u8 domain; 283 __u8 mode; 284 __u8 pad03[1]; 285 struct { 286 __u8 signal[4]; 287 __u64 source[4][8]; 288 __u16 logic_op; 289 } ctr[4]; 290 }; 291 292 #define NVIF_PERFDOM_V0_INIT 0x00 293 #define NVIF_PERFDOM_V0_SAMPLE 0x01 294 #define NVIF_PERFDOM_V0_READ 0x02 295 296 struct nvif_perfdom_init { 297 }; 298 299 struct nvif_perfdom_sample { 300 }; 301 302 struct nvif_perfdom_read_v0 { 303 __u8 version; 304 __u8 pad01[7]; 305 __u32 ctr[4]; 306 __u32 clk; 307 __u8 pad04[4]; 308 }; 309 310 311 /******************************************************************************* 312 * device control 313 ******************************************************************************/ 314 315 #define NVIF_CONTROL_PSTATE_INFO 0x00 316 #define NVIF_CONTROL_PSTATE_ATTR 0x01 317 #define NVIF_CONTROL_PSTATE_USER 0x02 318 319 struct nvif_control_pstate_info_v0 { 320 __u8 version; 321 __u8 count; /* out: number of power states */ 322 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) 323 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) 324 __s8 ustate_ac; /* out: target pstate index */ 325 __s8 ustate_dc; /* out: target pstate index */ 326 __s8 pwrsrc; /* out: current power source */ 327 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) 328 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) 329 __s8 pstate; /* out: current pstate index */ 330 __u8 pad06[2]; 331 }; 332 333 struct nvif_control_pstate_attr_v0 { 334 __u8 version; 335 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) 336 __s8 state; /* in: index of pstate to query 337 * out: pstate identifier 338 */ 339 __u8 index; /* in: index of attribute to query 340 * out: index of next attribute, or 0 if no more 341 */ 342 __u8 pad03[5]; 343 __u32 min; 344 __u32 max; 345 char name[32]; 346 char unit[16]; 347 }; 348 349 struct nvif_control_pstate_user_v0 { 350 __u8 version; 351 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) 352 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) 353 __s8 ustate; /* in: pstate identifier */ 354 __s8 pwrsrc; /* in: target power source */ 355 __u8 pad03[5]; 356 }; 357 358 359 /******************************************************************************* 360 * DMA FIFO channels 361 ******************************************************************************/ 362 363 struct nv03_channel_dma_v0 { 364 __u8 version; 365 __u8 chid; 366 __u8 pad02[2]; 367 __u32 offset; 368 __u64 pushbuf; 369 }; 370 371 struct nv50_channel_dma_v0 { 372 __u8 version; 373 __u8 chid; 374 __u8 pad02[6]; 375 __u64 vm; 376 __u64 pushbuf; 377 __u64 offset; 378 }; 379 380 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 381 382 /******************************************************************************* 383 * GPFIFO channels 384 ******************************************************************************/ 385 386 struct nv50_channel_gpfifo_v0 { 387 __u8 version; 388 __u8 chid; 389 __u8 pad02[2]; 390 __u32 ilength; 391 __u64 ioffset; 392 __u64 pushbuf; 393 __u64 vm; 394 }; 395 396 struct fermi_channel_gpfifo_v0 { 397 __u8 version; 398 __u8 chid; 399 __u8 pad02[2]; 400 __u32 ilength; 401 __u64 ioffset; 402 __u64 vm; 403 }; 404 405 struct kepler_channel_gpfifo_a_v0 { 406 __u8 version; 407 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 408 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02 409 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04 410 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 411 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 412 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 413 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 414 __u8 engine; 415 __u16 chid; 416 __u32 ilength; 417 __u64 ioffset; 418 __u64 vm; 419 }; 420 421 /******************************************************************************* 422 * legacy display 423 ******************************************************************************/ 424 425 #define NV04_DISP_NTFY_VBLANK 0x00 426 #define NV04_DISP_NTFY_CONN 0x01 427 428 struct nv04_disp_mthd_v0 { 429 __u8 version; 430 #define NV04_DISP_SCANOUTPOS 0x00 431 __u8 method; 432 __u8 head; 433 __u8 pad03[5]; 434 }; 435 436 struct nv04_disp_scanoutpos_v0 { 437 __u8 version; 438 __u8 pad01[7]; 439 __s64 time[2]; 440 __u16 vblanks; 441 __u16 vblanke; 442 __u16 vtotal; 443 __u16 vline; 444 __u16 hblanks; 445 __u16 hblanke; 446 __u16 htotal; 447 __u16 hline; 448 }; 449 450 /******************************************************************************* 451 * display 452 ******************************************************************************/ 453 454 #define NV50_DISP_MTHD 0x00 455 456 struct nv50_disp_mthd_v0 { 457 __u8 version; 458 #define NV50_DISP_SCANOUTPOS 0x00 459 __u8 method; 460 __u8 head; 461 __u8 pad03[5]; 462 }; 463 464 struct nv50_disp_mthd_v1 { 465 __u8 version; 466 #define NV50_DISP_MTHD_V1_DAC_PWR 0x10 467 #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 468 #define NV50_DISP_MTHD_V1_SOR_PWR 0x20 469 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 470 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 471 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 472 #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 473 #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 474 __u8 method; 475 __u16 hasht; 476 __u16 hashm; 477 __u8 pad06[2]; 478 }; 479 480 struct nv50_disp_dac_pwr_v0 { 481 __u8 version; 482 __u8 state; 483 __u8 data; 484 __u8 vsync; 485 __u8 hsync; 486 __u8 pad05[3]; 487 }; 488 489 struct nv50_disp_dac_load_v0 { 490 __u8 version; 491 __u8 load; 492 __u8 pad02[2]; 493 __u32 data; 494 }; 495 496 struct nv50_disp_sor_pwr_v0 { 497 __u8 version; 498 __u8 state; 499 __u8 pad02[6]; 500 }; 501 502 struct nv50_disp_sor_hda_eld_v0 { 503 __u8 version; 504 __u8 pad01[7]; 505 __u8 data[]; 506 }; 507 508 struct nv50_disp_sor_hdmi_pwr_v0 { 509 __u8 version; 510 __u8 state; 511 __u8 max_ac_packet; 512 __u8 rekey; 513 __u8 pad04[4]; 514 }; 515 516 struct nv50_disp_sor_lvds_script_v0 { 517 __u8 version; 518 __u8 pad01[1]; 519 __u16 script; 520 __u8 pad04[4]; 521 }; 522 523 struct nv50_disp_sor_dp_pwr_v0 { 524 __u8 version; 525 __u8 state; 526 __u8 pad02[6]; 527 }; 528 529 struct nv50_disp_pior_pwr_v0 { 530 __u8 version; 531 __u8 state; 532 __u8 type; 533 __u8 pad03[5]; 534 }; 535 536 /* core */ 537 struct nv50_disp_core_channel_dma_v0 { 538 __u8 version; 539 __u8 pad01[7]; 540 __u64 pushbuf; 541 }; 542 543 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 544 545 /* cursor immediate */ 546 struct nv50_disp_cursor_v0 { 547 __u8 version; 548 __u8 head; 549 __u8 pad02[6]; 550 }; 551 552 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 553 554 /* base */ 555 struct nv50_disp_base_channel_dma_v0 { 556 __u8 version; 557 __u8 head; 558 __u8 pad02[6]; 559 __u64 pushbuf; 560 }; 561 562 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 563 564 /* overlay */ 565 struct nv50_disp_overlay_channel_dma_v0 { 566 __u8 version; 567 __u8 head; 568 __u8 pad02[6]; 569 __u64 pushbuf; 570 }; 571 572 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 573 574 /* overlay immediate */ 575 struct nv50_disp_overlay_v0 { 576 __u8 version; 577 __u8 head; 578 __u8 pad02[6]; 579 }; 580 581 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 582 583 /******************************************************************************* 584 * fermi 585 ******************************************************************************/ 586 587 #define FERMI_A_ZBC_COLOR 0x00 588 #define FERMI_A_ZBC_DEPTH 0x01 589 590 struct fermi_a_zbc_color_v0 { 591 __u8 version; 592 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 593 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 594 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 595 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 596 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c 597 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 598 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 599 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 600 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 601 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c 602 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 603 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 604 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 605 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c 606 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 607 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 608 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 609 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c 610 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 611 __u8 format; 612 __u8 index; 613 __u8 pad03[5]; 614 __u32 ds[4]; 615 __u32 l2[4]; 616 }; 617 618 struct fermi_a_zbc_depth_v0 { 619 __u8 version; 620 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 621 __u8 format; 622 __u8 index; 623 __u8 pad03[5]; 624 __u32 ds; 625 __u32 l2; 626 }; 627 628 #endif 629