1 /* SPDX-License-Identifier: MIT */
2 #ifndef __NVIF_CLASS_H__
3 #define __NVIF_CLASS_H__
4 
5 /* these class numbers are made up by us, and not nvidia-assigned */
6 #define NVIF_CLASS_CLIENT                            /* if0000.h */ -0x00000000
7 
8 #define NVIF_CLASS_CONTROL                           /* if0001.h */ -0x00000001
9 
10 #define NVIF_CLASS_PERFMON                           /* if0002.h */ -0x00000002
11 #define NVIF_CLASS_PERFDOM                           /* if0003.h */ -0x00000003
12 
13 #define NVIF_CLASS_SW_NV04                           /* if0004.h */ -0x00000004
14 #define NVIF_CLASS_SW_NV10                           /* if0005.h */ -0x00000005
15 #define NVIF_CLASS_SW_NV50                           /* if0005.h */ -0x00000006
16 #define NVIF_CLASS_SW_GF100                          /* if0005.h */ -0x00000007
17 
18 #define NVIF_CLASS_MMU                               /* if0008.h */  0x80000008
19 #define NVIF_CLASS_MMU_NV04                          /* if0008.h */  0x80000009
20 #define NVIF_CLASS_MMU_NV50                          /* if0008.h */  0x80005009
21 #define NVIF_CLASS_MMU_GF100                         /* if0008.h */  0x80009009
22 
23 #define NVIF_CLASS_MEM                               /* if000a.h */  0x8000000a
24 #define NVIF_CLASS_MEM_NV04                          /* if000b.h */  0x8000000b
25 #define NVIF_CLASS_MEM_NV50                          /* if500b.h */  0x8000500b
26 #define NVIF_CLASS_MEM_GF100                         /* if900b.h */  0x8000900b
27 
28 #define NVIF_CLASS_VMM                               /* if000c.h */  0x8000000c
29 #define NVIF_CLASS_VMM_NV04                          /* if000d.h */  0x8000000d
30 #define NVIF_CLASS_VMM_NV50                          /* if500d.h */  0x8000500d
31 #define NVIF_CLASS_VMM_GF100                         /* if900d.h */  0x8000900d
32 #define NVIF_CLASS_VMM_GM200                         /* ifb00d.h */  0x8000b00d
33 #define NVIF_CLASS_VMM_GP100                         /* ifc00d.h */  0x8000c00d
34 
35 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
36 #define NV_NULL_CLASS                                                0x00000030
37 
38 #define NV_DEVICE                                     /* cl0080.h */ 0x00000080
39 
40 #define NV_DMA_FROM_MEMORY                            /* cl0002.h */ 0x00000002
41 #define NV_DMA_TO_MEMORY                              /* cl0002.h */ 0x00000003
42 #define NV_DMA_IN_MEMORY                              /* cl0002.h */ 0x0000003d
43 
44 #define NV50_TWOD                                                    0x0000502d
45 #define FERMI_TWOD_A                                                 0x0000902d
46 
47 #define NV50_MEMORY_TO_MEMORY_FORMAT                                 0x00005039
48 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039
49 
50 #define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
51 #define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140
52 
53 #define NV04_DISP                                     /* cl0046.h */ 0x00000046
54 
55 #define VOLTA_USERMODE_A                                             0x0000c361
56 
57 #define MAXWELL_FAULT_BUFFER_A                        /* clb069.h */ 0x0000b069
58 #define VOLTA_FAULT_BUFFER_A                          /* clb069.h */ 0x0000c369
59 
60 #define NV03_CHANNEL_DMA                              /* cl506b.h */ 0x0000006b
61 #define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e
62 #define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e
63 #define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e
64 #define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e
65 #define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e
66 
67 #define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f
68 #define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f
69 #define FERMI_CHANNEL_GPFIFO                          /* cl906f.h */ 0x0000906f
70 #define KEPLER_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000a06f
71 #define KEPLER_CHANNEL_GPFIFO_B                       /* cla06f.h */ 0x0000a16f
72 #define MAXWELL_CHANNEL_GPFIFO_A                      /* cla06f.h */ 0x0000b06f
73 #define PASCAL_CHANNEL_GPFIFO_A                       /* cla06f.h */ 0x0000c06f
74 #define VOLTA_CHANNEL_GPFIFO_A                        /* clc36f.h */ 0x0000c36f
75 #define TURING_CHANNEL_GPFIFO_A                       /* clc36f.h */ 0x0000c46f
76 
77 #define NV50_DISP                                     /* cl5070.h */ 0x00005070
78 #define G82_DISP                                      /* cl5070.h */ 0x00008270
79 #define GT200_DISP                                    /* cl5070.h */ 0x00008370
80 #define GT214_DISP                                    /* cl5070.h */ 0x00008570
81 #define GT206_DISP                                    /* cl5070.h */ 0x00008870
82 #define GF110_DISP                                    /* cl5070.h */ 0x00009070
83 #define GK104_DISP                                    /* cl5070.h */ 0x00009170
84 #define GK110_DISP                                    /* cl5070.h */ 0x00009270
85 #define GM107_DISP                                    /* cl5070.h */ 0x00009470
86 #define GM200_DISP                                    /* cl5070.h */ 0x00009570
87 #define GP100_DISP                                    /* cl5070.h */ 0x00009770
88 #define GP102_DISP                                    /* cl5070.h */ 0x00009870
89 #define GV100_DISP                                    /* cl5070.h */ 0x0000c370
90 #define TU102_DISP                                    /* cl5070.h */ 0x0000c570
91 
92 #define NV31_MPEG                                                    0x00003174
93 #define G82_MPEG                                                     0x00008274
94 
95 #define NV74_VP2                                                     0x00007476
96 
97 #define NV50_DISP_CURSOR                              /* cl507a.h */ 0x0000507a
98 #define G82_DISP_CURSOR                               /* cl507a.h */ 0x0000827a
99 #define GT214_DISP_CURSOR                             /* cl507a.h */ 0x0000857a
100 #define GF110_DISP_CURSOR                             /* cl507a.h */ 0x0000907a
101 #define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a
102 #define GV100_DISP_CURSOR                             /* cl507a.h */ 0x0000c37a
103 #define TU102_DISP_CURSOR                             /* cl507a.h */ 0x0000c57a
104 
105 #define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
106 #define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
107 #define GT214_DISP_OVERLAY                            /* cl507b.h */ 0x0000857b
108 #define GF110_DISP_OVERLAY                            /* cl507b.h */ 0x0000907b
109 #define GK104_DISP_OVERLAY                            /* cl507b.h */ 0x0000917b
110 
111 #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c37b
112 #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c57b
113 
114 #define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
115 #define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
116 #define GT200_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000837c
117 #define GT214_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000857c
118 #define GF110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000907c
119 #define GK104_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000917c
120 #define GK110_DISP_BASE_CHANNEL_DMA                   /* cl507c.h */ 0x0000927c
121 
122 #define NV50_DISP_CORE_CHANNEL_DMA                    /* cl507d.h */ 0x0000507d
123 #define G82_DISP_CORE_CHANNEL_DMA                     /* cl507d.h */ 0x0000827d
124 #define GT200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000837d
125 #define GT214_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000857d
126 #define GT206_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000887d
127 #define GF110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000907d
128 #define GK104_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000917d
129 #define GK110_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000927d
130 #define GM107_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000947d
131 #define GM200_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000957d
132 #define GP100_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000977d
133 #define GP102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000987d
134 #define GV100_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c37d
135 #define TU102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c57d
136 
137 #define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
138 #define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
139 #define GT200_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000837e
140 #define GT214_DISP_OVERLAY_CHANNEL_DMA                /* cl507e.h */ 0x0000857e
141 #define GF110_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000907e
142 #define GK104_DISP_OVERLAY_CONTROL_DMA                /* cl507e.h */ 0x0000917e
143 
144 #define GV100_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c37e
145 #define TU102_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c57e
146 
147 #define NV50_TESLA                                                   0x00005097
148 #define G82_TESLA                                                    0x00008297
149 #define GT200_TESLA                                                  0x00008397
150 #define GT214_TESLA                                                  0x00008597
151 #define GT21A_TESLA                                                  0x00008697
152 
153 #define FERMI_A                                       /* cl9097.h */ 0x00009097
154 #define FERMI_B                                       /* cl9097.h */ 0x00009197
155 #define FERMI_C                                       /* cl9097.h */ 0x00009297
156 
157 #define KEPLER_A                                      /* cl9097.h */ 0x0000a097
158 #define KEPLER_B                                      /* cl9097.h */ 0x0000a197
159 #define KEPLER_C                                      /* cl9097.h */ 0x0000a297
160 
161 #define MAXWELL_A                                     /* cl9097.h */ 0x0000b097
162 #define MAXWELL_B                                     /* cl9097.h */ 0x0000b197
163 
164 #define PASCAL_A                                      /* cl9097.h */ 0x0000c097
165 #define PASCAL_B                                      /* cl9097.h */ 0x0000c197
166 
167 #define VOLTA_A                                       /* cl9097.h */ 0x0000c397
168 
169 #define TURING_A                                      /* cl9097.h */ 0x0000c597
170 
171 #define NV74_BSP                                                     0x000074b0
172 
173 #define GT212_MSVLD                                                  0x000085b1
174 #define IGT21A_MSVLD                                                 0x000086b1
175 #define G98_MSVLD                                                    0x000088b1
176 #define GF100_MSVLD                                                  0x000090b1
177 #define GK104_MSVLD                                                  0x000095b1
178 
179 #define GT212_MSPDEC                                                 0x000085b2
180 #define G98_MSPDEC                                                   0x000088b2
181 #define GF100_MSPDEC                                                 0x000090b2
182 #define GK104_MSPDEC                                                 0x000095b2
183 
184 #define GT212_MSPPP                                                  0x000085b3
185 #define G98_MSPPP                                                    0x000088b3
186 #define GF100_MSPPP                                                  0x000090b3
187 
188 #define G98_SEC                                                      0x000088b4
189 
190 #define GT212_DMA                                                    0x000085b5
191 #define FERMI_DMA                                                    0x000090b5
192 #define KEPLER_DMA_COPY_A                                            0x0000a0b5
193 #define MAXWELL_DMA_COPY_A                                           0x0000b0b5
194 #define PASCAL_DMA_COPY_A                                            0x0000c0b5
195 #define PASCAL_DMA_COPY_B                                            0x0000c1b5
196 #define VOLTA_DMA_COPY_A                                             0x0000c3b5
197 #define TURING_DMA_COPY_A                                            0x0000c5b5
198 
199 #define FERMI_DECOMPRESS                                             0x000090b8
200 
201 #define NV50_COMPUTE                                                 0x000050c0
202 #define GT214_COMPUTE                                                0x000085c0
203 #define FERMI_COMPUTE_A                                              0x000090c0
204 #define FERMI_COMPUTE_B                                              0x000091c0
205 #define KEPLER_COMPUTE_A                                             0x0000a0c0
206 #define KEPLER_COMPUTE_B                                             0x0000a1c0
207 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
208 #define MAXWELL_COMPUTE_B                                            0x0000b1c0
209 #define PASCAL_COMPUTE_A                                             0x0000c0c0
210 #define PASCAL_COMPUTE_B                                             0x0000c1c0
211 #define VOLTA_COMPUTE_A                                              0x0000c3c0
212 #define TURING_COMPUTE_A                                             0x0000c5c0
213 
214 #define NV74_CIPHER                                                  0x000074c1
215 #endif
216