1 #ifndef __NVIF_CLASS_H__
2 #define __NVIF_CLASS_H__
3 
4 /*******************************************************************************
5  * class identifiers
6  ******************************************************************************/
7 
8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
9 #define NV_DEVICE                                                    0x00000080
10 
11 #define NV_DMA_FROM_MEMORY                                           0x00000002
12 #define NV_DMA_TO_MEMORY                                             0x00000003
13 #define NV_DMA_IN_MEMORY                                             0x0000003d
14 
15 #define FERMI_TWOD_A                                                 0x0000902d
16 
17 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A                              0x00009039
18 
19 #define KEPLER_INLINE_TO_MEMORY_A                                    0x0000a040
20 #define KEPLER_INLINE_TO_MEMORY_B                                    0x0000a140
21 
22 #define NV04_DISP                                                    0x00000046
23 
24 #define NV03_CHANNEL_DMA                                             0x0000006b
25 #define NV10_CHANNEL_DMA                                             0x0000006e
26 #define NV17_CHANNEL_DMA                                             0x0000176e
27 #define NV40_CHANNEL_DMA                                             0x0000406e
28 #define NV50_CHANNEL_DMA                                             0x0000506e
29 #define G82_CHANNEL_DMA                                              0x0000826e
30 
31 #define NV50_CHANNEL_GPFIFO                                          0x0000506f
32 #define G82_CHANNEL_GPFIFO                                           0x0000826f
33 #define FERMI_CHANNEL_GPFIFO                                         0x0000906f
34 #define KEPLER_CHANNEL_GPFIFO_A                                      0x0000a06f
35 #define MAXWELL_CHANNEL_GPFIFO_A                                     0x0000b06f
36 
37 #define NV50_DISP                                                    0x00005070
38 #define G82_DISP                                                     0x00008270
39 #define GT200_DISP                                                   0x00008370
40 #define GT214_DISP                                                   0x00008570
41 #define GT206_DISP                                                   0x00008870
42 #define GF110_DISP                                                   0x00009070
43 #define GK104_DISP                                                   0x00009170
44 #define GK110_DISP                                                   0x00009270
45 #define GM107_DISP                                                   0x00009470
46 #define GM204_DISP                                                   0x00009570
47 
48 #define NV31_MPEG                                                    0x00003174
49 #define G82_MPEG                                                     0x00008274
50 
51 #define NV74_VP2                                                     0x00007476
52 
53 #define NV50_DISP_CURSOR                                             0x0000507a
54 #define G82_DISP_CURSOR                                              0x0000827a
55 #define GT214_DISP_CURSOR                                            0x0000857a
56 #define GF110_DISP_CURSOR                                            0x0000907a
57 #define GK104_DISP_CURSOR                                            0x0000917a
58 
59 #define NV50_DISP_OVERLAY                                            0x0000507b
60 #define G82_DISP_OVERLAY                                             0x0000827b
61 #define GT214_DISP_OVERLAY                                           0x0000857b
62 #define GF110_DISP_OVERLAY                                           0x0000907b
63 #define GK104_DISP_OVERLAY                                           0x0000917b
64 
65 #define NV50_DISP_BASE_CHANNEL_DMA                                   0x0000507c
66 #define G82_DISP_BASE_CHANNEL_DMA                                    0x0000827c
67 #define GT200_DISP_BASE_CHANNEL_DMA                                  0x0000837c
68 #define GT214_DISP_BASE_CHANNEL_DMA                                  0x0000857c
69 #define GF110_DISP_BASE_CHANNEL_DMA                                  0x0000907c
70 #define GK104_DISP_BASE_CHANNEL_DMA                                  0x0000917c
71 #define GK110_DISP_BASE_CHANNEL_DMA                                  0x0000927c
72 
73 #define NV50_DISP_CORE_CHANNEL_DMA                                   0x0000507d
74 #define G82_DISP_CORE_CHANNEL_DMA                                    0x0000827d
75 #define GT200_DISP_CORE_CHANNEL_DMA                                  0x0000837d
76 #define GT214_DISP_CORE_CHANNEL_DMA                                  0x0000857d
77 #define GT206_DISP_CORE_CHANNEL_DMA                                  0x0000887d
78 #define GF110_DISP_CORE_CHANNEL_DMA                                  0x0000907d
79 #define GK104_DISP_CORE_CHANNEL_DMA                                  0x0000917d
80 #define GK110_DISP_CORE_CHANNEL_DMA                                  0x0000927d
81 #define GM107_DISP_CORE_CHANNEL_DMA                                  0x0000947d
82 #define GM204_DISP_CORE_CHANNEL_DMA                                  0x0000957d
83 
84 #define NV50_DISP_OVERLAY_CHANNEL_DMA                                0x0000507e
85 #define G82_DISP_OVERLAY_CHANNEL_DMA                                 0x0000827e
86 #define GT200_DISP_OVERLAY_CHANNEL_DMA                               0x0000837e
87 #define GT214_DISP_OVERLAY_CHANNEL_DMA                               0x0000857e
88 #define GF110_DISP_OVERLAY_CONTROL_DMA                               0x0000907e
89 #define GK104_DISP_OVERLAY_CONTROL_DMA                               0x0000917e
90 
91 #define FERMI_A                                                      0x00009097
92 #define FERMI_B                                                      0x00009197
93 #define FERMI_C                                                      0x00009297
94 
95 #define KEPLER_A                                                     0x0000a097
96 #define KEPLER_B                                                     0x0000a197
97 #define KEPLER_C                                                     0x0000a297
98 
99 #define MAXWELL_A                                                    0x0000b097
100 #define MAXWELL_B                                                    0x0000b197
101 
102 #define NV74_BSP                                                     0x000074b0
103 
104 #define GT212_MSVLD                                                  0x000085b1
105 #define IGT21A_MSVLD                                                 0x000086b1
106 #define G98_MSVLD                                                    0x000088b1
107 #define GF100_MSVLD                                                  0x000090b1
108 #define GK104_MSVLD                                                  0x000095b1
109 
110 #define GT212_MSPDEC                                                 0x000085b2
111 #define G98_MSPDEC                                                   0x000088b2
112 #define GF100_MSPDEC                                                 0x000090b2
113 #define GK104_MSPDEC                                                 0x000095b2
114 
115 #define GT212_MSPPP                                                  0x000085b3
116 #define G98_MSPPP                                                    0x000088b3
117 #define GF100_MSPPP                                                  0x000090b3
118 
119 #define G98_SEC                                                      0x000088b4
120 
121 #define GT212_DMA                                                    0x000085b5
122 #define FERMI_DMA                                                    0x000090b5
123 #define KEPLER_DMA_COPY_A                                            0x0000a0b5
124 #define MAXWELL_DMA_COPY_A                                           0x0000b0b5
125 
126 #define FERMI_DECOMPRESS                                             0x000090b8
127 
128 #define FERMI_COMPUTE_A                                              0x000090c0
129 #define FERMI_COMPUTE_B                                              0x000091c0
130 #define KEPLER_COMPUTE_A                                             0x0000a0c0
131 #define KEPLER_COMPUTE_B                                             0x0000a1c0
132 #define MAXWELL_COMPUTE_A                                            0x0000b0c0
133 #define MAXWELL_COMPUTE_B                                            0x0000b1c0
134 
135 #define NV74_CIPHER                                                  0x000074c1
136 
137 /*******************************************************************************
138  * client
139  ******************************************************************************/
140 
141 #define NV_CLIENT_DEVLIST                                                  0x00
142 
143 struct nv_client_devlist_v0 {
144 	__u8  version;
145 	__u8  count;
146 	__u8  pad02[6];
147 	__u64 device[];
148 };
149 
150 
151 /*******************************************************************************
152  * device
153  ******************************************************************************/
154 
155 struct nv_device_v0 {
156 	__u8  version;
157 	__u8  pad01[7];
158 	__u64 device;	/* device identifier, ~0 for client default */
159 };
160 
161 #define NV_DEVICE_V0_INFO                                                  0x00
162 #define NV_DEVICE_V0_TIME                                                  0x01
163 
164 struct nv_device_info_v0 {
165 	__u8  version;
166 #define NV_DEVICE_INFO_V0_IGP                                              0x00
167 #define NV_DEVICE_INFO_V0_PCI                                              0x01
168 #define NV_DEVICE_INFO_V0_AGP                                              0x02
169 #define NV_DEVICE_INFO_V0_PCIE                                             0x03
170 #define NV_DEVICE_INFO_V0_SOC                                              0x04
171 	__u8  platform;
172 	__u16 chipset;	/* from NV_PMC_BOOT_0 */
173 	__u8  revision;	/* from NV_PMC_BOOT_0 */
174 #define NV_DEVICE_INFO_V0_TNT                                              0x01
175 #define NV_DEVICE_INFO_V0_CELSIUS                                          0x02
176 #define NV_DEVICE_INFO_V0_KELVIN                                           0x03
177 #define NV_DEVICE_INFO_V0_RANKINE                                          0x04
178 #define NV_DEVICE_INFO_V0_CURIE                                            0x05
179 #define NV_DEVICE_INFO_V0_TESLA                                            0x06
180 #define NV_DEVICE_INFO_V0_FERMI                                            0x07
181 #define NV_DEVICE_INFO_V0_KEPLER                                           0x08
182 #define NV_DEVICE_INFO_V0_MAXWELL                                          0x09
183 	__u8  family;
184 	__u8  pad06[2];
185 	__u64 ram_size;
186 	__u64 ram_user;
187 	char  chip[16];
188 	char  name[64];
189 };
190 
191 struct nv_device_time_v0 {
192 	__u8  version;
193 	__u8  pad01[7];
194 	__u64 time;
195 };
196 
197 
198 /*******************************************************************************
199  * context dma
200  ******************************************************************************/
201 
202 struct nv_dma_v0 {
203 	__u8  version;
204 #define NV_DMA_V0_TARGET_VM                                                0x00
205 #define NV_DMA_V0_TARGET_VRAM                                              0x01
206 #define NV_DMA_V0_TARGET_PCI                                               0x02
207 #define NV_DMA_V0_TARGET_PCI_US                                            0x03
208 #define NV_DMA_V0_TARGET_AGP                                               0x04
209 	__u8  target;
210 #define NV_DMA_V0_ACCESS_VM                                                0x00
211 #define NV_DMA_V0_ACCESS_RD                                                0x01
212 #define NV_DMA_V0_ACCESS_WR                                                0x02
213 #define NV_DMA_V0_ACCESS_RDWR                 (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
214 	__u8  access;
215 	__u8  pad03[5];
216 	__u64 start;
217 	__u64 limit;
218 	/* ... chipset-specific class data */
219 };
220 
221 struct nv50_dma_v0 {
222 	__u8  version;
223 #define NV50_DMA_V0_PRIV_VM                                                0x00
224 #define NV50_DMA_V0_PRIV_US                                                0x01
225 #define NV50_DMA_V0_PRIV__S                                                0x02
226 	__u8  priv;
227 #define NV50_DMA_V0_PART_VM                                                0x00
228 #define NV50_DMA_V0_PART_256                                               0x01
229 #define NV50_DMA_V0_PART_1KB                                               0x02
230 	__u8  part;
231 #define NV50_DMA_V0_COMP_NONE                                              0x00
232 #define NV50_DMA_V0_COMP_1                                                 0x01
233 #define NV50_DMA_V0_COMP_2                                                 0x02
234 #define NV50_DMA_V0_COMP_VM                                                0x03
235 	__u8  comp;
236 #define NV50_DMA_V0_KIND_PITCH                                             0x00
237 #define NV50_DMA_V0_KIND_VM                                                0x7f
238 	__u8  kind;
239 	__u8  pad05[3];
240 };
241 
242 struct gf100_dma_v0 {
243 	__u8  version;
244 #define GF100_DMA_V0_PRIV_VM                                               0x00
245 #define GF100_DMA_V0_PRIV_US                                               0x01
246 #define GF100_DMA_V0_PRIV__S                                               0x02
247 	__u8  priv;
248 #define GF100_DMA_V0_KIND_PITCH                                            0x00
249 #define GF100_DMA_V0_KIND_VM                                               0xff
250 	__u8  kind;
251 	__u8  pad03[5];
252 };
253 
254 struct gf110_dma_v0 {
255 	__u8  version;
256 #define GF110_DMA_V0_PAGE_LP                                               0x00
257 #define GF110_DMA_V0_PAGE_SP                                               0x01
258 	__u8  page;
259 #define GF110_DMA_V0_KIND_PITCH                                            0x00
260 #define GF110_DMA_V0_KIND_VM                                               0xff
261 	__u8  kind;
262 	__u8  pad03[5];
263 };
264 
265 
266 /*******************************************************************************
267  * perfmon
268  ******************************************************************************/
269 
270 #define NVIF_PERFMON_V0_QUERY_DOMAIN                                       0x00
271 #define NVIF_PERFMON_V0_QUERY_SIGNAL                                       0x01
272 #define NVIF_PERFMON_V0_QUERY_SOURCE                                       0x02
273 
274 struct nvif_perfmon_query_domain_v0 {
275 	__u8  version;
276 	__u8  id;
277 	__u8  counter_nr;
278 	__u8  iter;
279 	__u16 signal_nr;
280 	__u8  pad05[2];
281 	char  name[64];
282 };
283 
284 struct nvif_perfmon_query_signal_v0 {
285 	__u8  version;
286 	__u8  domain;
287 	__u16 iter;
288 	__u8  signal;
289 	__u8  source_nr;
290 	__u8  pad05[2];
291 	char  name[64];
292 };
293 
294 struct nvif_perfmon_query_source_v0 {
295 	__u8  version;
296 	__u8  domain;
297 	__u8  signal;
298 	__u8  iter;
299 	__u8  pad04[4];
300 	__u32 source;
301 	__u32 mask;
302 	char  name[64];
303 };
304 
305 
306 /*******************************************************************************
307  * perfdom
308  ******************************************************************************/
309 
310 struct nvif_perfdom_v0 {
311 	__u8  version;
312 	__u8  domain;
313 	__u8  mode;
314 	__u8  pad03[1];
315 	struct {
316 		__u8  signal[4];
317 		__u64 source[4][8];
318 		__u16 logic_op;
319 	} ctr[4];
320 };
321 
322 #define NVIF_PERFDOM_V0_INIT                                               0x00
323 #define NVIF_PERFDOM_V0_SAMPLE                                             0x01
324 #define NVIF_PERFDOM_V0_READ                                               0x02
325 
326 struct nvif_perfdom_init {
327 };
328 
329 struct nvif_perfdom_sample {
330 };
331 
332 struct nvif_perfdom_read_v0 {
333 	__u8  version;
334 	__u8  pad01[7];
335 	__u32 ctr[4];
336 	__u32 clk;
337 	__u8  pad04[4];
338 };
339 
340 
341 /*******************************************************************************
342  * device control
343  ******************************************************************************/
344 
345 #define NVIF_CONTROL_PSTATE_INFO                                           0x00
346 #define NVIF_CONTROL_PSTATE_ATTR                                           0x01
347 #define NVIF_CONTROL_PSTATE_USER                                           0x02
348 
349 struct nvif_control_pstate_info_v0 {
350 	__u8  version;
351 	__u8  count; /* out: number of power states */
352 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE                         (-1)
353 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON                         (-2)
354 	__s8  ustate_ac; /* out: target pstate index */
355 	__s8  ustate_dc; /* out: target pstate index */
356 	__s8  pwrsrc; /* out: current power source */
357 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN                         (-1)
358 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON                         (-2)
359 	__s8  pstate; /* out: current pstate index */
360 	__u8  pad06[2];
361 };
362 
363 struct nvif_control_pstate_attr_v0 {
364 	__u8  version;
365 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT                          (-1)
366 	__s8  state; /*  in: index of pstate to query
367 		      * out: pstate identifier
368 		      */
369 	__u8  index; /*  in: index of attribute to query
370 		      * out: index of next attribute, or 0 if no more
371 		      */
372 	__u8  pad03[5];
373 	__u32 min;
374 	__u32 max;
375 	char  name[32];
376 	char  unit[16];
377 };
378 
379 struct nvif_control_pstate_user_v0 {
380 	__u8  version;
381 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN                          (-1)
382 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON                          (-2)
383 	__s8  ustate; /*  in: pstate identifier */
384 	__s8  pwrsrc; /*  in: target power source */
385 	__u8  pad03[5];
386 };
387 
388 
389 /*******************************************************************************
390  * DMA FIFO channels
391  ******************************************************************************/
392 
393 struct nv03_channel_dma_v0 {
394 	__u8  version;
395 	__u8  chid;
396 	__u8  pad02[2];
397 	__u32 offset;
398 	__u64 pushbuf;
399 };
400 
401 struct nv50_channel_dma_v0 {
402 	__u8  version;
403 	__u8  chid;
404 	__u8  pad02[6];
405 	__u64 vm;
406 	__u64 pushbuf;
407 	__u64 offset;
408 };
409 
410 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT                                     0x00
411 
412 /*******************************************************************************
413  * GPFIFO channels
414  ******************************************************************************/
415 
416 struct nv50_channel_gpfifo_v0 {
417 	__u8  version;
418 	__u8  chid;
419 	__u8  pad02[2];
420 	__u32 ilength;
421 	__u64 ioffset;
422 	__u64 pushbuf;
423 	__u64 vm;
424 };
425 
426 struct fermi_channel_gpfifo_v0 {
427 	__u8  version;
428 	__u8  chid;
429 	__u8  pad02[2];
430 	__u32 ilength;
431 	__u64 ioffset;
432 	__u64 vm;
433 };
434 
435 struct kepler_channel_gpfifo_a_v0 {
436 	__u8  version;
437 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
438 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC                           0x02
439 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
440 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
441 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
442 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20
443 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC                              0x40
444 	__u8  engine;
445 	__u16 chid;
446 	__u32 ilength;
447 	__u64 ioffset;
448 	__u64 vm;
449 };
450 
451 /*******************************************************************************
452  * legacy display
453  ******************************************************************************/
454 
455 #define NV04_DISP_NTFY_VBLANK                                              0x00
456 #define NV04_DISP_NTFY_CONN                                                0x01
457 
458 struct nv04_disp_mthd_v0 {
459 	__u8  version;
460 #define NV04_DISP_SCANOUTPOS                                               0x00
461 	__u8  method;
462 	__u8  head;
463 	__u8  pad03[5];
464 };
465 
466 struct nv04_disp_scanoutpos_v0 {
467 	__u8  version;
468 	__u8  pad01[7];
469 	__s64 time[2];
470 	__u16 vblanks;
471 	__u16 vblanke;
472 	__u16 vtotal;
473 	__u16 vline;
474 	__u16 hblanks;
475 	__u16 hblanke;
476 	__u16 htotal;
477 	__u16 hline;
478 };
479 
480 /*******************************************************************************
481  * display
482  ******************************************************************************/
483 
484 #define NV50_DISP_MTHD                                                     0x00
485 
486 struct nv50_disp_mthd_v0 {
487 	__u8  version;
488 #define NV50_DISP_SCANOUTPOS                                               0x00
489 	__u8  method;
490 	__u8  head;
491 	__u8  pad03[5];
492 };
493 
494 struct nv50_disp_mthd_v1 {
495 	__u8  version;
496 #define NV50_DISP_MTHD_V1_DAC_PWR                                          0x10
497 #define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
498 #define NV50_DISP_MTHD_V1_SOR_PWR                                          0x20
499 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
500 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
501 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
502 #define NV50_DISP_MTHD_V1_SOR_DP_PWR                                       0x24
503 #define NV50_DISP_MTHD_V1_PIOR_PWR                                         0x30
504 	__u8  method;
505 	__u16 hasht;
506 	__u16 hashm;
507 	__u8  pad06[2];
508 };
509 
510 struct nv50_disp_dac_pwr_v0 {
511 	__u8  version;
512 	__u8  state;
513 	__u8  data;
514 	__u8  vsync;
515 	__u8  hsync;
516 	__u8  pad05[3];
517 };
518 
519 struct nv50_disp_dac_load_v0 {
520 	__u8  version;
521 	__u8  load;
522 	__u8  pad02[2];
523 	__u32 data;
524 };
525 
526 struct nv50_disp_sor_pwr_v0 {
527 	__u8  version;
528 	__u8  state;
529 	__u8  pad02[6];
530 };
531 
532 struct nv50_disp_sor_hda_eld_v0 {
533 	__u8  version;
534 	__u8  pad01[7];
535 	__u8  data[];
536 };
537 
538 struct nv50_disp_sor_hdmi_pwr_v0 {
539 	__u8  version;
540 	__u8  state;
541 	__u8  max_ac_packet;
542 	__u8  rekey;
543 	__u8  pad04[4];
544 };
545 
546 struct nv50_disp_sor_lvds_script_v0 {
547 	__u8  version;
548 	__u8  pad01[1];
549 	__u16 script;
550 	__u8  pad04[4];
551 };
552 
553 struct nv50_disp_sor_dp_pwr_v0 {
554 	__u8  version;
555 	__u8  state;
556 	__u8  pad02[6];
557 };
558 
559 struct nv50_disp_pior_pwr_v0 {
560 	__u8  version;
561 	__u8  state;
562 	__u8  type;
563 	__u8  pad03[5];
564 };
565 
566 /* core */
567 struct nv50_disp_core_channel_dma_v0 {
568 	__u8  version;
569 	__u8  pad01[7];
570 	__u64 pushbuf;
571 };
572 
573 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
574 
575 /* cursor immediate */
576 struct nv50_disp_cursor_v0 {
577 	__u8  version;
578 	__u8  head;
579 	__u8  pad02[6];
580 };
581 
582 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT                                    0x00
583 
584 /* base */
585 struct nv50_disp_base_channel_dma_v0 {
586 	__u8  version;
587 	__u8  head;
588 	__u8  pad02[6];
589 	__u64 pushbuf;
590 };
591 
592 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT                          0x00
593 
594 /* overlay */
595 struct nv50_disp_overlay_channel_dma_v0 {
596 	__u8  version;
597 	__u8  head;
598 	__u8  pad02[6];
599 	__u64 pushbuf;
600 };
601 
602 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT                       0x00
603 
604 /* overlay immediate */
605 struct nv50_disp_overlay_v0 {
606 	__u8  version;
607 	__u8  head;
608 	__u8  pad02[6];
609 };
610 
611 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT                                   0x00
612 
613 /*******************************************************************************
614  * software
615  ******************************************************************************/
616 
617 #define NVSW_NTFY_UEVENT                                                   0x00
618 
619 #define NV04_NVSW_GET_REF                                                  0x00
620 
621 struct nv04_nvsw_get_ref_v0 {
622 	__u8  version;
623 	__u8  pad01[3];
624 	__u32 ref;
625 };
626 
627 /*******************************************************************************
628  * fermi
629  ******************************************************************************/
630 
631 #define FERMI_A_ZBC_COLOR                                                  0x00
632 #define FERMI_A_ZBC_DEPTH                                                  0x01
633 
634 struct fermi_a_zbc_color_v0 {
635 	__u8  version;
636 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO                                      0x01
637 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE                                 0x02
638 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32                       0x04
639 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16                           0x08
640 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16                       0x0c
641 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16                       0x10
642 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16                       0x14
643 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16                       0x16
644 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8                                  0x18
645 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8                               0x1c
646 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10                               0x20
647 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10                           0x24
648 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8                                  0x28
649 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8                               0x2c
650 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8                              0x30
651 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8                              0x34
652 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8                              0x38
653 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10                               0x3c
654 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11                              0x40
655 	__u8  format;
656 	__u8  index;
657 	__u8  pad03[5];
658 	__u32 ds[4];
659 	__u32 l2[4];
660 };
661 
662 struct fermi_a_zbc_depth_v0 {
663 	__u8  version;
664 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32                                      0x01
665 	__u8  format;
666 	__u8  index;
667 	__u8  pad03[5];
668 	__u32 ds;
669 	__u32 l2;
670 };
671 
672 #endif
673