1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "wndw.h" 23 #include "wimm.h" 24 25 #include <nvif/class.h> 26 #include <nvif/cl0002.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_fourcc.h> 30 31 #include "nouveau_bo.h" 32 #include "nouveau_gem.h" 33 34 static void 35 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma) 36 { 37 nvif_object_fini(&ctxdma->object); 38 list_del(&ctxdma->head); 39 kfree(ctxdma); 40 } 41 42 static struct nv50_wndw_ctxdma * 43 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct drm_framebuffer *fb) 44 { 45 struct nouveau_drm *drm = nouveau_drm(fb->dev); 46 struct nv50_wndw_ctxdma *ctxdma; 47 u32 handle; 48 u32 unused; 49 u8 kind; 50 struct { 51 struct nv_dma_v0 base; 52 union { 53 struct nv50_dma_v0 nv50; 54 struct gf100_dma_v0 gf100; 55 struct gf119_dma_v0 gf119; 56 }; 57 } args = {}; 58 u32 argc = sizeof(args.base); 59 int ret; 60 61 nouveau_framebuffer_get_layout(fb, &unused, &kind); 62 handle = 0xfb000000 | kind; 63 64 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) { 65 if (ctxdma->object.handle == handle) 66 return ctxdma; 67 } 68 69 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL))) 70 return ERR_PTR(-ENOMEM); 71 list_add(&ctxdma->head, &wndw->ctxdma.list); 72 73 args.base.target = NV_DMA_V0_TARGET_VRAM; 74 args.base.access = NV_DMA_V0_ACCESS_RDWR; 75 args.base.start = 0; 76 args.base.limit = drm->client.device.info.ram_user - 1; 77 78 if (drm->client.device.info.chipset < 0x80) { 79 args.nv50.part = NV50_DMA_V0_PART_256; 80 argc += sizeof(args.nv50); 81 } else 82 if (drm->client.device.info.chipset < 0xc0) { 83 args.nv50.part = NV50_DMA_V0_PART_256; 84 args.nv50.kind = kind; 85 argc += sizeof(args.nv50); 86 } else 87 if (drm->client.device.info.chipset < 0xd0) { 88 args.gf100.kind = kind; 89 argc += sizeof(args.gf100); 90 } else { 91 args.gf119.page = GF119_DMA_V0_PAGE_LP; 92 args.gf119.kind = kind; 93 argc += sizeof(args.gf119); 94 } 95 96 ret = nvif_object_init(wndw->ctxdma.parent, handle, NV_DMA_IN_MEMORY, 97 &args, argc, &ctxdma->object); 98 if (ret) { 99 nv50_wndw_ctxdma_del(ctxdma); 100 return ERR_PTR(ret); 101 } 102 103 return ctxdma; 104 } 105 106 int 107 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 108 { 109 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 110 if (asyw->set.ntfy) { 111 return wndw->func->ntfy_wait_begun(disp->sync, 112 asyw->ntfy.offset, 113 wndw->wndw.base.device); 114 } 115 return 0; 116 } 117 118 void 119 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush, 120 struct nv50_wndw_atom *asyw) 121 { 122 union nv50_wndw_atom_mask clr = { 123 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), 124 }; 125 if (clr.sema ) wndw->func-> sema_clr(wndw); 126 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); 127 if (clr.xlut ) wndw->func-> xlut_clr(wndw); 128 if (clr.csc ) wndw->func-> csc_clr(wndw); 129 if (clr.image) wndw->func->image_clr(wndw); 130 131 interlock[wndw->interlock.type] |= wndw->interlock.data; 132 } 133 134 void 135 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, 136 struct nv50_wndw_atom *asyw) 137 { 138 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 139 asyw->image.mode = 0; 140 asyw->image.interval = 1; 141 } 142 143 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); 144 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); 145 if (asyw->set.image) wndw->func->image_set(wndw, asyw); 146 147 if (asyw->set.xlut ) { 148 if (asyw->ilut) { 149 asyw->xlut.i.offset = 150 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer, 151 asyw->ilut, asyw->xlut.i.load); 152 } 153 wndw->func->xlut_set(wndw, asyw); 154 } 155 156 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); 157 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); 158 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw); 159 if (asyw->set.point) { 160 if (asyw->set.point = false, asyw->set.mask) 161 interlock[wndw->interlock.type] |= wndw->interlock.data; 162 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm; 163 164 wndw->immd->point(wndw, asyw); 165 wndw->immd->update(wndw, interlock); 166 } else { 167 interlock[wndw->interlock.type] |= wndw->interlock.data; 168 } 169 } 170 171 void 172 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 173 { 174 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 175 176 asyw->ntfy.handle = wndw->wndw.sync.handle; 177 asyw->ntfy.offset = wndw->ntfy; 178 asyw->ntfy.awaken = false; 179 asyw->set.ntfy = true; 180 181 wndw->func->ntfy_reset(disp->sync, wndw->ntfy); 182 wndw->ntfy ^= 0x10; 183 } 184 185 static void 186 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw, 187 struct nv50_wndw_atom *asyw, 188 struct nv50_head_atom *asyh) 189 { 190 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 191 NV_ATOMIC(drm, "%s release\n", wndw->plane.name); 192 wndw->func->release(wndw, asyw, asyh); 193 asyw->ntfy.handle = 0; 194 asyw->sema.handle = 0; 195 asyw->xlut.handle = 0; 196 memset(asyw->image.handle, 0x00, sizeof(asyw->image.handle)); 197 } 198 199 static int 200 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw) 201 { 202 switch (asyw->state.fb->format->format) { 203 case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break; 204 case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break; 205 default: 206 WARN_ON(1); 207 return -EINVAL; 208 } 209 asyw->image.colorspace = 1; 210 return 0; 211 } 212 213 static int 214 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) 215 { 216 switch (asyw->state.fb->format->format) { 217 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; 218 case DRM_FORMAT_XRGB8888 : 219 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; 220 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; 221 case DRM_FORMAT_XRGB1555 : 222 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; 223 case DRM_FORMAT_XBGR2101010 : 224 case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break; 225 case DRM_FORMAT_XBGR8888 : 226 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; 227 case DRM_FORMAT_XRGB2101010 : 228 case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break; 229 case DRM_FORMAT_XBGR16161616F: 230 case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break; 231 default: 232 return -EINVAL; 233 } 234 asyw->image.colorspace = 0; 235 return 0; 236 } 237 238 static int 239 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, 240 struct nv50_wndw_atom *armw, 241 struct nv50_wndw_atom *asyw, 242 struct nv50_head_atom *asyh) 243 { 244 struct drm_framebuffer *fb = asyw->state.fb; 245 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 246 uint8_t kind; 247 uint32_t tile_mode; 248 int ret; 249 250 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); 251 252 if (fb != armw->state.fb || !armw->visible || modeset) { 253 nouveau_framebuffer_get_layout(fb, &tile_mode, &kind); 254 255 asyw->image.w = fb->width; 256 asyw->image.h = fb->height; 257 asyw->image.kind = kind; 258 259 ret = nv50_wndw_atomic_check_acquire_rgb(asyw); 260 if (ret) { 261 ret = nv50_wndw_atomic_check_acquire_yuv(asyw); 262 if (ret) 263 return ret; 264 } 265 266 if (asyw->image.kind) { 267 asyw->image.layout = 0; 268 if (drm->client.device.info.chipset >= 0xc0) 269 asyw->image.blockh = tile_mode >> 4; 270 else 271 asyw->image.blockh = tile_mode; 272 asyw->image.blocks[0] = fb->pitches[0] / 64; 273 asyw->image.pitch[0] = 0; 274 } else { 275 asyw->image.layout = 1; 276 asyw->image.blockh = 0; 277 asyw->image.blocks[0] = 0; 278 asyw->image.pitch[0] = fb->pitches[0]; 279 } 280 281 if (!asyh->state.async_flip) 282 asyw->image.interval = 1; 283 else 284 asyw->image.interval = 0; 285 asyw->image.mode = asyw->image.interval ? 0 : 1; 286 asyw->set.image = wndw->func->image_set != NULL; 287 } 288 289 if (wndw->func->scale_set) { 290 asyw->scale.sx = asyw->state.src_x >> 16; 291 asyw->scale.sy = asyw->state.src_y >> 16; 292 asyw->scale.sw = asyw->state.src_w >> 16; 293 asyw->scale.sh = asyw->state.src_h >> 16; 294 asyw->scale.dw = asyw->state.crtc_w; 295 asyw->scale.dh = asyw->state.crtc_h; 296 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale))) 297 asyw->set.scale = true; 298 } 299 300 if (wndw->func->blend_set) { 301 asyw->blend.depth = 255 - asyw->state.normalized_zpos; 302 asyw->blend.k1 = asyw->state.alpha >> 8; 303 switch (asyw->state.pixel_blend_mode) { 304 case DRM_MODE_BLEND_PREMULTI: 305 asyw->blend.src_color = 2; /* K1 */ 306 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ 307 break; 308 case DRM_MODE_BLEND_COVERAGE: 309 asyw->blend.src_color = 5; /* K1_TIMES_SRC */ 310 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ 311 break; 312 case DRM_MODE_BLEND_PIXEL_NONE: 313 default: 314 asyw->blend.src_color = 2; /* K1 */ 315 asyw->blend.dst_color = 4; /* NEG_K1 */ 316 break; 317 } 318 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) 319 asyw->set.blend = true; 320 } 321 322 if (wndw->immd) { 323 asyw->point.x = asyw->state.crtc_x; 324 asyw->point.y = asyw->state.crtc_y; 325 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) 326 asyw->set.point = true; 327 } 328 329 return wndw->func->acquire(wndw, asyw, asyh); 330 } 331 332 static int 333 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, 334 struct nv50_wndw_atom *armw, 335 struct nv50_wndw_atom *asyw, 336 struct nv50_head_atom *asyh) 337 { 338 struct drm_property_blob *ilut = asyh->state.degamma_lut; 339 340 /* I8 format without an input LUT makes no sense, and the 341 * HW error-checks for this. 342 * 343 * In order to handle legacy gamma, when there's no input 344 * LUT we need to steal the output LUT and use it instead. 345 */ 346 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) { 347 /* This should be an error, but there's legacy clients 348 * that do a modeset before providing a gamma table. 349 * 350 * We keep the window disabled to avoid angering HW. 351 */ 352 if (!(ilut = asyh->state.gamma_lut)) { 353 asyw->visible = false; 354 return 0; 355 } 356 357 if (wndw->func->ilut) 358 asyh->wndw.olut |= BIT(wndw->id); 359 } else { 360 asyh->wndw.olut &= ~BIT(wndw->id); 361 } 362 363 if (!ilut && wndw->func->ilut_identity && 364 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F && 365 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) { 366 static struct drm_property_blob dummy = {}; 367 ilut = &dummy; 368 } 369 370 /* Recalculate LUT state. */ 371 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut)); 372 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) { 373 if (!wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut))) { 374 DRM_DEBUG_KMS("Invalid ilut\n"); 375 return -EINVAL; 376 } 377 asyw->xlut.handle = wndw->wndw.vram.handle; 378 asyw->xlut.i.buffer = !asyw->xlut.i.buffer; 379 asyw->set.xlut = true; 380 } else { 381 asyw->clr.xlut = armw->xlut.handle != 0; 382 } 383 384 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */ 385 if (wndw->func->olut_core && 386 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle))) 387 asyw->set.xlut = true; 388 389 if (wndw->func->csc && asyh->state.ctm) { 390 const struct drm_color_ctm *ctm = asyh->state.ctm->data; 391 wndw->func->csc(wndw, asyw, ctm); 392 asyw->csc.valid = true; 393 asyw->set.csc = true; 394 } else { 395 asyw->csc.valid = false; 396 asyw->clr.csc = armw->csc.valid; 397 } 398 399 /* Can't do an immediate flip while changing the LUT. */ 400 asyh->state.async_flip = false; 401 return 0; 402 } 403 404 static int 405 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) 406 { 407 struct nouveau_drm *drm = nouveau_drm(plane->dev); 408 struct nv50_wndw *wndw = nv50_wndw(plane); 409 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); 410 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 411 struct nv50_head_atom *harm = NULL, *asyh = NULL; 412 bool modeset = false; 413 int ret; 414 415 NV_ATOMIC(drm, "%s atomic_check\n", plane->name); 416 417 /* Fetch the assembly state for the head the window will belong to, 418 * and determine whether the window will be visible. 419 */ 420 if (asyw->state.crtc) { 421 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 422 if (IS_ERR(asyh)) 423 return PTR_ERR(asyh); 424 modeset = drm_atomic_crtc_needs_modeset(&asyh->state); 425 asyw->visible = asyh->state.active; 426 } else { 427 asyw->visible = false; 428 } 429 430 /* Fetch assembly state for the head the window used to belong to. */ 431 if (armw->state.crtc) { 432 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); 433 if (IS_ERR(harm)) 434 return PTR_ERR(harm); 435 } 436 437 /* LUT configuration can potentially cause the window to be disabled. */ 438 if (asyw->visible && wndw->func->xlut_set && 439 (!armw->visible || 440 asyh->state.color_mgmt_changed || 441 asyw->state.fb->format->format != 442 armw->state.fb->format->format)) { 443 ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh); 444 if (ret) 445 return ret; 446 } 447 448 /* Calculate new window state. */ 449 if (asyw->visible) { 450 ret = nv50_wndw_atomic_check_acquire(wndw, modeset, 451 armw, asyw, asyh); 452 if (ret) 453 return ret; 454 455 asyh->wndw.mask |= BIT(wndw->id); 456 } else 457 if (armw->visible) { 458 nv50_wndw_atomic_check_release(wndw, asyw, harm); 459 harm->wndw.mask &= ~BIT(wndw->id); 460 } else { 461 return 0; 462 } 463 464 /* Aside from the obvious case where the window is actively being 465 * disabled, we might also need to temporarily disable the window 466 * when performing certain modeset operations. 467 */ 468 if (!asyw->visible || modeset) { 469 asyw->clr.ntfy = armw->ntfy.handle != 0; 470 asyw->clr.sema = armw->sema.handle != 0; 471 asyw->clr.xlut = armw->xlut.handle != 0; 472 if (asyw->clr.xlut && asyw->visible) 473 asyw->set.xlut = asyw->xlut.handle != 0; 474 asyw->clr.csc = armw->csc.valid; 475 if (wndw->func->image_clr) 476 asyw->clr.image = armw->image.handle[0] != 0; 477 } 478 479 return 0; 480 } 481 482 static void 483 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) 484 { 485 struct nouveau_drm *drm = nouveau_drm(plane->dev); 486 struct nouveau_bo *nvbo; 487 488 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); 489 if (!old_state->fb) 490 return; 491 492 nvbo = nouveau_gem_object(old_state->fb->obj[0]); 493 nouveau_bo_unpin(nvbo); 494 } 495 496 static int 497 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) 498 { 499 struct drm_framebuffer *fb = state->fb; 500 struct nouveau_drm *drm = nouveau_drm(plane->dev); 501 struct nv50_wndw *wndw = nv50_wndw(plane); 502 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 503 struct nouveau_bo *nvbo; 504 struct nv50_head_atom *asyh; 505 struct nv50_wndw_ctxdma *ctxdma; 506 int ret; 507 508 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb); 509 if (!asyw->state.fb) 510 return 0; 511 512 nvbo = nouveau_gem_object(fb->obj[0]); 513 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true); 514 if (ret) 515 return ret; 516 517 if (wndw->ctxdma.parent) { 518 ctxdma = nv50_wndw_ctxdma_new(wndw, fb); 519 if (IS_ERR(ctxdma)) { 520 nouveau_bo_unpin(nvbo); 521 return PTR_ERR(ctxdma); 522 } 523 524 if (asyw->visible) 525 asyw->image.handle[0] = ctxdma->object.handle; 526 } 527 528 asyw->state.fence = dma_resv_get_excl_rcu(nvbo->bo.base.resv); 529 asyw->image.offset[0] = nvbo->bo.offset; 530 531 if (wndw->func->prepare) { 532 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 533 if (IS_ERR(asyh)) 534 return PTR_ERR(asyh); 535 536 wndw->func->prepare(wndw, asyh, asyw); 537 } 538 539 return 0; 540 } 541 542 static const struct drm_plane_helper_funcs 543 nv50_wndw_helper = { 544 .prepare_fb = nv50_wndw_prepare_fb, 545 .cleanup_fb = nv50_wndw_cleanup_fb, 546 .atomic_check = nv50_wndw_atomic_check, 547 }; 548 549 static void 550 nv50_wndw_atomic_destroy_state(struct drm_plane *plane, 551 struct drm_plane_state *state) 552 { 553 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 554 __drm_atomic_helper_plane_destroy_state(&asyw->state); 555 kfree(asyw); 556 } 557 558 static struct drm_plane_state * 559 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) 560 { 561 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); 562 struct nv50_wndw_atom *asyw; 563 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) 564 return NULL; 565 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); 566 asyw->sema = armw->sema; 567 asyw->ntfy = armw->ntfy; 568 asyw->ilut = NULL; 569 asyw->xlut = armw->xlut; 570 asyw->csc = armw->csc; 571 asyw->image = armw->image; 572 asyw->point = armw->point; 573 asyw->clr.mask = 0; 574 asyw->set.mask = 0; 575 return &asyw->state; 576 } 577 578 static int 579 nv50_wndw_zpos_default(struct drm_plane *plane) 580 { 581 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 582 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255; 583 } 584 585 static void 586 nv50_wndw_reset(struct drm_plane *plane) 587 { 588 struct nv50_wndw_atom *asyw; 589 590 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL)))) 591 return; 592 593 if (plane->state) 594 plane->funcs->atomic_destroy_state(plane, plane->state); 595 596 __drm_atomic_helper_plane_reset(plane, &asyw->state); 597 plane->state->zpos = nv50_wndw_zpos_default(plane); 598 plane->state->normalized_zpos = nv50_wndw_zpos_default(plane); 599 } 600 601 static void 602 nv50_wndw_destroy(struct drm_plane *plane) 603 { 604 struct nv50_wndw *wndw = nv50_wndw(plane); 605 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp; 606 607 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) { 608 nv50_wndw_ctxdma_del(ctxdma); 609 } 610 611 nvif_notify_fini(&wndw->notify); 612 nv50_dmac_destroy(&wndw->wimm); 613 nv50_dmac_destroy(&wndw->wndw); 614 615 nv50_lut_fini(&wndw->ilut); 616 617 drm_plane_cleanup(&wndw->plane); 618 kfree(wndw); 619 } 620 621 /* This function assumes the format has already been validated against the plane 622 * and the modifier was validated against the device-wides modifier list at FB 623 * creation time. 624 */ 625 static bool nv50_plane_format_mod_supported(struct drm_plane *plane, 626 u32 format, u64 modifier) 627 { 628 struct nouveau_drm *drm = nouveau_drm(plane->dev); 629 uint8_t i; 630 631 if (drm->client.device.info.chipset < 0xc0) { 632 const struct drm_format_info *info = drm_format_info(format); 633 const uint8_t kind = (modifier >> 12) & 0xff; 634 635 if (!format) return false; 636 637 for (i = 0; i < info->num_planes; i++) 638 if ((info->cpp[i] != 4) && kind != 0x70) return false; 639 } 640 641 return true; 642 } 643 644 const struct drm_plane_funcs 645 nv50_wndw = { 646 .update_plane = drm_atomic_helper_update_plane, 647 .disable_plane = drm_atomic_helper_disable_plane, 648 .destroy = nv50_wndw_destroy, 649 .reset = nv50_wndw_reset, 650 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state, 651 .atomic_destroy_state = nv50_wndw_atomic_destroy_state, 652 .format_mod_supported = nv50_plane_format_mod_supported, 653 }; 654 655 static int 656 nv50_wndw_notify(struct nvif_notify *notify) 657 { 658 return NVIF_NOTIFY_KEEP; 659 } 660 661 void 662 nv50_wndw_fini(struct nv50_wndw *wndw) 663 { 664 nvif_notify_put(&wndw->notify); 665 } 666 667 void 668 nv50_wndw_init(struct nv50_wndw *wndw) 669 { 670 nvif_notify_get(&wndw->notify); 671 } 672 673 int 674 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, 675 enum drm_plane_type type, const char *name, int index, 676 const u32 *format, u32 heads, 677 enum nv50_disp_interlock_type interlock_type, u32 interlock_data, 678 struct nv50_wndw **pwndw) 679 { 680 struct nouveau_drm *drm = nouveau_drm(dev); 681 struct nvif_mmu *mmu = &drm->client.mmu; 682 struct nv50_disp *disp = nv50_disp(dev); 683 struct nv50_wndw *wndw; 684 int nformat; 685 int ret; 686 687 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL))) 688 return -ENOMEM; 689 wndw->func = func; 690 wndw->id = index; 691 wndw->interlock.type = interlock_type; 692 wndw->interlock.data = interlock_data; 693 694 wndw->ctxdma.parent = &wndw->wndw.base.user; 695 INIT_LIST_HEAD(&wndw->ctxdma.list); 696 697 for (nformat = 0; format[nformat]; nformat++); 698 699 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, 700 format, nformat, 701 nouveau_display(dev)->format_modifiers, 702 type, "%s-%d", name, index); 703 if (ret) { 704 kfree(*pwndw); 705 *pwndw = NULL; 706 return ret; 707 } 708 709 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); 710 711 if (wndw->func->ilut) { 712 ret = nv50_lut_init(disp, mmu, &wndw->ilut); 713 if (ret) 714 return ret; 715 } 716 717 wndw->notify.func = nv50_wndw_notify; 718 719 if (wndw->func->blend_set) { 720 ret = drm_plane_create_zpos_property(&wndw->plane, 721 nv50_wndw_zpos_default(&wndw->plane), 0, 254); 722 if (ret) 723 return ret; 724 725 ret = drm_plane_create_alpha_property(&wndw->plane); 726 if (ret) 727 return ret; 728 729 ret = drm_plane_create_blend_mode_property(&wndw->plane, 730 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 731 BIT(DRM_MODE_BLEND_PREMULTI) | 732 BIT(DRM_MODE_BLEND_COVERAGE)); 733 if (ret) 734 return ret; 735 } else { 736 ret = drm_plane_create_zpos_immutable_property(&wndw->plane, 737 nv50_wndw_zpos_default(&wndw->plane)); 738 if (ret) 739 return ret; 740 } 741 742 return 0; 743 } 744 745 int 746 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, 747 struct nv50_wndw **pwndw) 748 { 749 struct { 750 s32 oclass; 751 int version; 752 int (*new)(struct nouveau_drm *, enum drm_plane_type, 753 int, s32, struct nv50_wndw **); 754 } wndws[] = { 755 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new }, 756 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new }, 757 {} 758 }; 759 struct nv50_disp *disp = nv50_disp(drm->dev); 760 int cid, ret; 761 762 cid = nvif_mclass(&disp->disp->object, wndws); 763 if (cid < 0) { 764 NV_ERROR(drm, "No supported window class\n"); 765 return cid; 766 } 767 768 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw); 769 if (ret) 770 return ret; 771 772 return nv50_wimm_init(drm, *pwndw); 773 } 774