1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "wndw.h" 23 #include "wimm.h" 24 25 #include <nvif/class.h> 26 #include <nvif/cl0002.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_fourcc.h> 30 31 #include "nouveau_bo.h" 32 #include "nouveau_gem.h" 33 34 static void 35 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma) 36 { 37 nvif_object_fini(&ctxdma->object); 38 list_del(&ctxdma->head); 39 kfree(ctxdma); 40 } 41 42 static struct nv50_wndw_ctxdma * 43 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct drm_framebuffer *fb) 44 { 45 struct nouveau_drm *drm = nouveau_drm(fb->dev); 46 struct nv50_wndw_ctxdma *ctxdma; 47 u32 handle; 48 u32 unused; 49 u8 kind; 50 struct { 51 struct nv_dma_v0 base; 52 union { 53 struct nv50_dma_v0 nv50; 54 struct gf100_dma_v0 gf100; 55 struct gf119_dma_v0 gf119; 56 }; 57 } args = {}; 58 u32 argc = sizeof(args.base); 59 int ret; 60 61 nouveau_framebuffer_get_layout(fb, &unused, &kind); 62 handle = 0xfb000000 | kind; 63 64 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) { 65 if (ctxdma->object.handle == handle) 66 return ctxdma; 67 } 68 69 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL))) 70 return ERR_PTR(-ENOMEM); 71 list_add(&ctxdma->head, &wndw->ctxdma.list); 72 73 args.base.target = NV_DMA_V0_TARGET_VRAM; 74 args.base.access = NV_DMA_V0_ACCESS_RDWR; 75 args.base.start = 0; 76 args.base.limit = drm->client.device.info.ram_user - 1; 77 78 if (drm->client.device.info.chipset < 0x80) { 79 args.nv50.part = NV50_DMA_V0_PART_256; 80 argc += sizeof(args.nv50); 81 } else 82 if (drm->client.device.info.chipset < 0xc0) { 83 args.nv50.part = NV50_DMA_V0_PART_256; 84 args.nv50.kind = kind; 85 argc += sizeof(args.nv50); 86 } else 87 if (drm->client.device.info.chipset < 0xd0) { 88 args.gf100.kind = kind; 89 argc += sizeof(args.gf100); 90 } else { 91 args.gf119.page = GF119_DMA_V0_PAGE_LP; 92 args.gf119.kind = kind; 93 argc += sizeof(args.gf119); 94 } 95 96 ret = nvif_object_init(wndw->ctxdma.parent, handle, NV_DMA_IN_MEMORY, 97 &args, argc, &ctxdma->object); 98 if (ret) { 99 nv50_wndw_ctxdma_del(ctxdma); 100 return ERR_PTR(ret); 101 } 102 103 return ctxdma; 104 } 105 106 int 107 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 108 { 109 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 110 if (asyw->set.ntfy) { 111 return wndw->func->ntfy_wait_begun(disp->sync, 112 asyw->ntfy.offset, 113 wndw->wndw.base.device); 114 } 115 return 0; 116 } 117 118 void 119 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush, 120 struct nv50_wndw_atom *asyw) 121 { 122 union nv50_wndw_atom_mask clr = { 123 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), 124 }; 125 if (clr.sema ) wndw->func-> sema_clr(wndw); 126 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); 127 if (clr.xlut ) wndw->func-> xlut_clr(wndw); 128 if (clr.csc ) wndw->func-> csc_clr(wndw); 129 if (clr.image) wndw->func->image_clr(wndw); 130 131 interlock[wndw->interlock.type] |= wndw->interlock.data; 132 } 133 134 void 135 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, 136 struct nv50_wndw_atom *asyw) 137 { 138 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 139 asyw->image.mode = 0; 140 asyw->image.interval = 1; 141 } 142 143 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); 144 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); 145 if (asyw->set.image) wndw->func->image_set(wndw, asyw); 146 147 if (asyw->set.xlut ) { 148 if (asyw->ilut) { 149 asyw->xlut.i.offset = 150 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer, 151 asyw->ilut, asyw->xlut.i.load); 152 } 153 wndw->func->xlut_set(wndw, asyw); 154 } 155 156 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); 157 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); 158 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw); 159 if (asyw->set.point) { 160 if (asyw->set.point = false, asyw->set.mask) 161 interlock[wndw->interlock.type] |= wndw->interlock.data; 162 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm; 163 164 wndw->immd->point(wndw, asyw); 165 wndw->immd->update(wndw, interlock); 166 } else { 167 interlock[wndw->interlock.type] |= wndw->interlock.data; 168 } 169 } 170 171 void 172 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 173 { 174 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 175 176 asyw->ntfy.handle = wndw->wndw.sync.handle; 177 asyw->ntfy.offset = wndw->ntfy; 178 asyw->ntfy.awaken = false; 179 asyw->set.ntfy = true; 180 181 wndw->func->ntfy_reset(disp->sync, wndw->ntfy); 182 wndw->ntfy ^= 0x10; 183 } 184 185 static void 186 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw, 187 struct nv50_wndw_atom *asyw, 188 struct nv50_head_atom *asyh) 189 { 190 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 191 NV_ATOMIC(drm, "%s release\n", wndw->plane.name); 192 wndw->func->release(wndw, asyw, asyh); 193 asyw->ntfy.handle = 0; 194 asyw->sema.handle = 0; 195 } 196 197 static int 198 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw) 199 { 200 switch (asyw->state.fb->format->format) { 201 case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break; 202 case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break; 203 default: 204 WARN_ON(1); 205 return -EINVAL; 206 } 207 asyw->image.colorspace = 1; 208 return 0; 209 } 210 211 static int 212 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) 213 { 214 switch (asyw->state.fb->format->format) { 215 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; 216 case DRM_FORMAT_XRGB8888 : 217 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; 218 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; 219 case DRM_FORMAT_XRGB1555 : 220 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; 221 case DRM_FORMAT_XBGR2101010 : 222 case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break; 223 case DRM_FORMAT_XBGR8888 : 224 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; 225 case DRM_FORMAT_XRGB2101010 : 226 case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break; 227 case DRM_FORMAT_XBGR16161616F: 228 case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break; 229 default: 230 return -EINVAL; 231 } 232 asyw->image.colorspace = 0; 233 return 0; 234 } 235 236 static int 237 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, 238 struct nv50_wndw_atom *armw, 239 struct nv50_wndw_atom *asyw, 240 struct nv50_head_atom *asyh) 241 { 242 struct drm_framebuffer *fb = asyw->state.fb; 243 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 244 uint8_t kind; 245 uint32_t tile_mode; 246 int ret; 247 248 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); 249 250 if (fb != armw->state.fb || !armw->visible || modeset) { 251 nouveau_framebuffer_get_layout(fb, &tile_mode, &kind); 252 253 asyw->image.w = fb->width; 254 asyw->image.h = fb->height; 255 asyw->image.kind = kind; 256 257 ret = nv50_wndw_atomic_check_acquire_rgb(asyw); 258 if (ret) { 259 ret = nv50_wndw_atomic_check_acquire_yuv(asyw); 260 if (ret) 261 return ret; 262 } 263 264 if (asyw->image.kind) { 265 asyw->image.layout = 0; 266 if (drm->client.device.info.chipset >= 0xc0) 267 asyw->image.blockh = tile_mode >> 4; 268 else 269 asyw->image.blockh = tile_mode; 270 asyw->image.blocks[0] = fb->pitches[0] / 64; 271 asyw->image.pitch[0] = 0; 272 } else { 273 asyw->image.layout = 1; 274 asyw->image.blockh = 0; 275 asyw->image.blocks[0] = 0; 276 asyw->image.pitch[0] = fb->pitches[0]; 277 } 278 279 if (!asyh->state.async_flip) 280 asyw->image.interval = 1; 281 else 282 asyw->image.interval = 0; 283 asyw->image.mode = asyw->image.interval ? 0 : 1; 284 asyw->set.image = wndw->func->image_set != NULL; 285 } 286 287 if (wndw->func->scale_set) { 288 asyw->scale.sx = asyw->state.src_x >> 16; 289 asyw->scale.sy = asyw->state.src_y >> 16; 290 asyw->scale.sw = asyw->state.src_w >> 16; 291 asyw->scale.sh = asyw->state.src_h >> 16; 292 asyw->scale.dw = asyw->state.crtc_w; 293 asyw->scale.dh = asyw->state.crtc_h; 294 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale))) 295 asyw->set.scale = true; 296 } 297 298 if (wndw->func->blend_set) { 299 asyw->blend.depth = 255 - asyw->state.normalized_zpos; 300 asyw->blend.k1 = asyw->state.alpha >> 8; 301 switch (asyw->state.pixel_blend_mode) { 302 case DRM_MODE_BLEND_PREMULTI: 303 asyw->blend.src_color = 2; /* K1 */ 304 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ 305 break; 306 case DRM_MODE_BLEND_COVERAGE: 307 asyw->blend.src_color = 5; /* K1_TIMES_SRC */ 308 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ 309 break; 310 case DRM_MODE_BLEND_PIXEL_NONE: 311 default: 312 asyw->blend.src_color = 2; /* K1 */ 313 asyw->blend.dst_color = 4; /* NEG_K1 */ 314 break; 315 } 316 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) 317 asyw->set.blend = true; 318 } 319 320 if (wndw->immd) { 321 asyw->point.x = asyw->state.crtc_x; 322 asyw->point.y = asyw->state.crtc_y; 323 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) 324 asyw->set.point = true; 325 } 326 327 return wndw->func->acquire(wndw, asyw, asyh); 328 } 329 330 static int 331 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, 332 struct nv50_wndw_atom *armw, 333 struct nv50_wndw_atom *asyw, 334 struct nv50_head_atom *asyh) 335 { 336 struct drm_property_blob *ilut = asyh->state.degamma_lut; 337 338 /* I8 format without an input LUT makes no sense, and the 339 * HW error-checks for this. 340 * 341 * In order to handle legacy gamma, when there's no input 342 * LUT we need to steal the output LUT and use it instead. 343 */ 344 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) { 345 /* This should be an error, but there's legacy clients 346 * that do a modeset before providing a gamma table. 347 * 348 * We keep the window disabled to avoid angering HW. 349 */ 350 if (!(ilut = asyh->state.gamma_lut)) { 351 asyw->visible = false; 352 return 0; 353 } 354 355 if (wndw->func->ilut) 356 asyh->wndw.olut |= BIT(wndw->id); 357 } else { 358 asyh->wndw.olut &= ~BIT(wndw->id); 359 } 360 361 if (!ilut && wndw->func->ilut_identity && 362 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F && 363 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) { 364 static struct drm_property_blob dummy = {}; 365 ilut = &dummy; 366 } 367 368 /* Recalculate LUT state. */ 369 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut)); 370 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) { 371 if (!wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut))) { 372 DRM_DEBUG_KMS("Invalid ilut\n"); 373 return -EINVAL; 374 } 375 asyw->xlut.handle = wndw->wndw.vram.handle; 376 asyw->xlut.i.buffer = !asyw->xlut.i.buffer; 377 asyw->set.xlut = true; 378 } else { 379 asyw->clr.xlut = armw->xlut.handle != 0; 380 } 381 382 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */ 383 if (wndw->func->olut_core && 384 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle))) 385 asyw->set.xlut = true; 386 387 if (wndw->func->csc && asyh->state.ctm) { 388 const struct drm_color_ctm *ctm = asyh->state.ctm->data; 389 wndw->func->csc(wndw, asyw, ctm); 390 asyw->csc.valid = true; 391 asyw->set.csc = true; 392 } else { 393 asyw->csc.valid = false; 394 asyw->clr.csc = armw->csc.valid; 395 } 396 397 /* Can't do an immediate flip while changing the LUT. */ 398 asyh->state.async_flip = false; 399 return 0; 400 } 401 402 static int 403 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) 404 { 405 struct nouveau_drm *drm = nouveau_drm(plane->dev); 406 struct nv50_wndw *wndw = nv50_wndw(plane); 407 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); 408 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 409 struct nv50_head_atom *harm = NULL, *asyh = NULL; 410 bool modeset = false; 411 int ret; 412 413 NV_ATOMIC(drm, "%s atomic_check\n", plane->name); 414 415 /* Fetch the assembly state for the head the window will belong to, 416 * and determine whether the window will be visible. 417 */ 418 if (asyw->state.crtc) { 419 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 420 if (IS_ERR(asyh)) 421 return PTR_ERR(asyh); 422 modeset = drm_atomic_crtc_needs_modeset(&asyh->state); 423 asyw->visible = asyh->state.active; 424 } else { 425 asyw->visible = false; 426 } 427 428 /* Fetch assembly state for the head the window used to belong to. */ 429 if (armw->state.crtc) { 430 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); 431 if (IS_ERR(harm)) 432 return PTR_ERR(harm); 433 } 434 435 /* LUT configuration can potentially cause the window to be disabled. */ 436 if (asyw->visible && wndw->func->xlut_set && 437 (!armw->visible || 438 asyh->state.color_mgmt_changed || 439 asyw->state.fb->format->format != 440 armw->state.fb->format->format)) { 441 ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh); 442 if (ret) 443 return ret; 444 } 445 446 /* Calculate new window state. */ 447 if (asyw->visible) { 448 ret = nv50_wndw_atomic_check_acquire(wndw, modeset, 449 armw, asyw, asyh); 450 if (ret) 451 return ret; 452 453 asyh->wndw.mask |= BIT(wndw->id); 454 } else 455 if (armw->visible) { 456 nv50_wndw_atomic_check_release(wndw, asyw, harm); 457 harm->wndw.mask &= ~BIT(wndw->id); 458 } else { 459 return 0; 460 } 461 462 /* Aside from the obvious case where the window is actively being 463 * disabled, we might also need to temporarily disable the window 464 * when performing certain modeset operations. 465 */ 466 if (!asyw->visible || modeset) { 467 asyw->clr.ntfy = armw->ntfy.handle != 0; 468 asyw->clr.sema = armw->sema.handle != 0; 469 asyw->clr.xlut = armw->xlut.handle != 0; 470 if (asyw->clr.xlut && asyw->visible) 471 asyw->set.xlut = asyw->xlut.handle != 0; 472 asyw->clr.csc = armw->csc.valid; 473 if (wndw->func->image_clr) 474 asyw->clr.image = armw->image.handle[0] != 0; 475 } 476 477 return 0; 478 } 479 480 static void 481 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) 482 { 483 struct nouveau_drm *drm = nouveau_drm(plane->dev); 484 struct nouveau_bo *nvbo; 485 486 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); 487 if (!old_state->fb) 488 return; 489 490 nvbo = nouveau_gem_object(old_state->fb->obj[0]); 491 nouveau_bo_unpin(nvbo); 492 } 493 494 static int 495 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) 496 { 497 struct drm_framebuffer *fb = state->fb; 498 struct nouveau_drm *drm = nouveau_drm(plane->dev); 499 struct nv50_wndw *wndw = nv50_wndw(plane); 500 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 501 struct nouveau_bo *nvbo; 502 struct nv50_head_atom *asyh; 503 struct nv50_wndw_ctxdma *ctxdma; 504 int ret; 505 506 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, fb); 507 if (!asyw->state.fb) 508 return 0; 509 510 nvbo = nouveau_gem_object(fb->obj[0]); 511 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true); 512 if (ret) 513 return ret; 514 515 if (wndw->ctxdma.parent) { 516 ctxdma = nv50_wndw_ctxdma_new(wndw, fb); 517 if (IS_ERR(ctxdma)) { 518 nouveau_bo_unpin(nvbo); 519 return PTR_ERR(ctxdma); 520 } 521 522 asyw->image.handle[0] = ctxdma->object.handle; 523 } 524 525 asyw->state.fence = dma_resv_get_excl_rcu(nvbo->bo.base.resv); 526 asyw->image.offset[0] = nvbo->bo.offset; 527 528 if (wndw->func->prepare) { 529 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 530 if (IS_ERR(asyh)) 531 return PTR_ERR(asyh); 532 533 wndw->func->prepare(wndw, asyh, asyw); 534 } 535 536 return 0; 537 } 538 539 static const struct drm_plane_helper_funcs 540 nv50_wndw_helper = { 541 .prepare_fb = nv50_wndw_prepare_fb, 542 .cleanup_fb = nv50_wndw_cleanup_fb, 543 .atomic_check = nv50_wndw_atomic_check, 544 }; 545 546 static void 547 nv50_wndw_atomic_destroy_state(struct drm_plane *plane, 548 struct drm_plane_state *state) 549 { 550 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 551 __drm_atomic_helper_plane_destroy_state(&asyw->state); 552 kfree(asyw); 553 } 554 555 static struct drm_plane_state * 556 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) 557 { 558 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); 559 struct nv50_wndw_atom *asyw; 560 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) 561 return NULL; 562 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); 563 asyw->sema = armw->sema; 564 asyw->ntfy = armw->ntfy; 565 asyw->ilut = NULL; 566 asyw->xlut = armw->xlut; 567 asyw->csc = armw->csc; 568 asyw->image = armw->image; 569 asyw->point = armw->point; 570 asyw->clr.mask = 0; 571 asyw->set.mask = 0; 572 return &asyw->state; 573 } 574 575 static int 576 nv50_wndw_zpos_default(struct drm_plane *plane) 577 { 578 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 579 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255; 580 } 581 582 static void 583 nv50_wndw_reset(struct drm_plane *plane) 584 { 585 struct nv50_wndw_atom *asyw; 586 587 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL)))) 588 return; 589 590 if (plane->state) 591 plane->funcs->atomic_destroy_state(plane, plane->state); 592 593 __drm_atomic_helper_plane_reset(plane, &asyw->state); 594 plane->state->zpos = nv50_wndw_zpos_default(plane); 595 plane->state->normalized_zpos = nv50_wndw_zpos_default(plane); 596 } 597 598 static void 599 nv50_wndw_destroy(struct drm_plane *plane) 600 { 601 struct nv50_wndw *wndw = nv50_wndw(plane); 602 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp; 603 604 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) { 605 nv50_wndw_ctxdma_del(ctxdma); 606 } 607 608 nvif_notify_fini(&wndw->notify); 609 nv50_dmac_destroy(&wndw->wimm); 610 nv50_dmac_destroy(&wndw->wndw); 611 612 nv50_lut_fini(&wndw->ilut); 613 614 drm_plane_cleanup(&wndw->plane); 615 kfree(wndw); 616 } 617 618 /* This function assumes the format has already been validated against the plane 619 * and the modifier was validated against the device-wides modifier list at FB 620 * creation time. 621 */ 622 static bool nv50_plane_format_mod_supported(struct drm_plane *plane, 623 u32 format, u64 modifier) 624 { 625 struct nouveau_drm *drm = nouveau_drm(plane->dev); 626 uint8_t i; 627 628 if (drm->client.device.info.chipset < 0xc0) { 629 const struct drm_format_info *info = drm_format_info(format); 630 const uint8_t kind = (modifier >> 12) & 0xff; 631 632 if (!format) return false; 633 634 for (i = 0; i < info->num_planes; i++) 635 if ((info->cpp[i] != 4) && kind != 0x70) return false; 636 } 637 638 return true; 639 } 640 641 const struct drm_plane_funcs 642 nv50_wndw = { 643 .update_plane = drm_atomic_helper_update_plane, 644 .disable_plane = drm_atomic_helper_disable_plane, 645 .destroy = nv50_wndw_destroy, 646 .reset = nv50_wndw_reset, 647 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state, 648 .atomic_destroy_state = nv50_wndw_atomic_destroy_state, 649 .format_mod_supported = nv50_plane_format_mod_supported, 650 }; 651 652 static int 653 nv50_wndw_notify(struct nvif_notify *notify) 654 { 655 return NVIF_NOTIFY_KEEP; 656 } 657 658 void 659 nv50_wndw_fini(struct nv50_wndw *wndw) 660 { 661 nvif_notify_put(&wndw->notify); 662 } 663 664 void 665 nv50_wndw_init(struct nv50_wndw *wndw) 666 { 667 nvif_notify_get(&wndw->notify); 668 } 669 670 int 671 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, 672 enum drm_plane_type type, const char *name, int index, 673 const u32 *format, u32 heads, 674 enum nv50_disp_interlock_type interlock_type, u32 interlock_data, 675 struct nv50_wndw **pwndw) 676 { 677 struct nouveau_drm *drm = nouveau_drm(dev); 678 struct nvif_mmu *mmu = &drm->client.mmu; 679 struct nv50_disp *disp = nv50_disp(dev); 680 struct nv50_wndw *wndw; 681 int nformat; 682 int ret; 683 684 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL))) 685 return -ENOMEM; 686 wndw->func = func; 687 wndw->id = index; 688 wndw->interlock.type = interlock_type; 689 wndw->interlock.data = interlock_data; 690 691 wndw->ctxdma.parent = &wndw->wndw.base.user; 692 INIT_LIST_HEAD(&wndw->ctxdma.list); 693 694 for (nformat = 0; format[nformat]; nformat++); 695 696 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, 697 format, nformat, 698 nouveau_display(dev)->format_modifiers, 699 type, "%s-%d", name, index); 700 if (ret) { 701 kfree(*pwndw); 702 *pwndw = NULL; 703 return ret; 704 } 705 706 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); 707 708 if (wndw->func->ilut) { 709 ret = nv50_lut_init(disp, mmu, &wndw->ilut); 710 if (ret) 711 return ret; 712 } 713 714 wndw->notify.func = nv50_wndw_notify; 715 716 if (wndw->func->blend_set) { 717 ret = drm_plane_create_zpos_property(&wndw->plane, 718 nv50_wndw_zpos_default(&wndw->plane), 0, 254); 719 if (ret) 720 return ret; 721 722 ret = drm_plane_create_alpha_property(&wndw->plane); 723 if (ret) 724 return ret; 725 726 ret = drm_plane_create_blend_mode_property(&wndw->plane, 727 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 728 BIT(DRM_MODE_BLEND_PREMULTI) | 729 BIT(DRM_MODE_BLEND_COVERAGE)); 730 if (ret) 731 return ret; 732 } else { 733 ret = drm_plane_create_zpos_immutable_property(&wndw->plane, 734 nv50_wndw_zpos_default(&wndw->plane)); 735 if (ret) 736 return ret; 737 } 738 739 return 0; 740 } 741 742 int 743 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, 744 struct nv50_wndw **pwndw) 745 { 746 struct { 747 s32 oclass; 748 int version; 749 int (*new)(struct nouveau_drm *, enum drm_plane_type, 750 int, s32, struct nv50_wndw **); 751 } wndws[] = { 752 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new }, 753 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new }, 754 {} 755 }; 756 struct nv50_disp *disp = nv50_disp(drm->dev); 757 int cid, ret; 758 759 cid = nvif_mclass(&disp->disp->object, wndws); 760 if (cid < 0) { 761 NV_ERROR(drm, "No supported window class\n"); 762 return cid; 763 } 764 765 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw); 766 if (ret) 767 return ret; 768 769 return nv50_wimm_init(drm, *pwndw); 770 } 771