1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "wndw.h" 23 #include "wimm.h" 24 25 #include <nvif/class.h> 26 #include <nvif/cl0002.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_fourcc.h> 30 31 #include "nouveau_bo.h" 32 33 static void 34 nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma) 35 { 36 nvif_object_fini(&ctxdma->object); 37 list_del(&ctxdma->head); 38 kfree(ctxdma); 39 } 40 41 static struct nv50_wndw_ctxdma * 42 nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct nouveau_framebuffer *fb) 43 { 44 struct nouveau_drm *drm = nouveau_drm(fb->base.dev); 45 struct nv50_wndw_ctxdma *ctxdma; 46 const u8 kind = fb->nvbo->kind; 47 const u32 handle = 0xfb000000 | kind; 48 struct { 49 struct nv_dma_v0 base; 50 union { 51 struct nv50_dma_v0 nv50; 52 struct gf100_dma_v0 gf100; 53 struct gf119_dma_v0 gf119; 54 }; 55 } args = {}; 56 u32 argc = sizeof(args.base); 57 int ret; 58 59 list_for_each_entry(ctxdma, &wndw->ctxdma.list, head) { 60 if (ctxdma->object.handle == handle) 61 return ctxdma; 62 } 63 64 if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL))) 65 return ERR_PTR(-ENOMEM); 66 list_add(&ctxdma->head, &wndw->ctxdma.list); 67 68 args.base.target = NV_DMA_V0_TARGET_VRAM; 69 args.base.access = NV_DMA_V0_ACCESS_RDWR; 70 args.base.start = 0; 71 args.base.limit = drm->client.device.info.ram_user - 1; 72 73 if (drm->client.device.info.chipset < 0x80) { 74 args.nv50.part = NV50_DMA_V0_PART_256; 75 argc += sizeof(args.nv50); 76 } else 77 if (drm->client.device.info.chipset < 0xc0) { 78 args.nv50.part = NV50_DMA_V0_PART_256; 79 args.nv50.kind = kind; 80 argc += sizeof(args.nv50); 81 } else 82 if (drm->client.device.info.chipset < 0xd0) { 83 args.gf100.kind = kind; 84 argc += sizeof(args.gf100); 85 } else { 86 args.gf119.page = GF119_DMA_V0_PAGE_LP; 87 args.gf119.kind = kind; 88 argc += sizeof(args.gf119); 89 } 90 91 ret = nvif_object_init(wndw->ctxdma.parent, handle, NV_DMA_IN_MEMORY, 92 &args, argc, &ctxdma->object); 93 if (ret) { 94 nv50_wndw_ctxdma_del(ctxdma); 95 return ERR_PTR(ret); 96 } 97 98 return ctxdma; 99 } 100 101 int 102 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 103 { 104 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 105 if (asyw->set.ntfy) { 106 return wndw->func->ntfy_wait_begun(disp->sync, 107 asyw->ntfy.offset, 108 wndw->wndw.base.device); 109 } 110 return 0; 111 } 112 113 void 114 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush, 115 struct nv50_wndw_atom *asyw) 116 { 117 union nv50_wndw_atom_mask clr = { 118 .mask = asyw->clr.mask & ~(flush ? 0 : asyw->set.mask), 119 }; 120 if (clr.sema ) wndw->func-> sema_clr(wndw); 121 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); 122 if (clr.xlut ) wndw->func-> xlut_clr(wndw); 123 if (clr.csc ) wndw->func-> csc_clr(wndw); 124 if (clr.image) wndw->func->image_clr(wndw); 125 126 interlock[wndw->interlock.type] |= wndw->interlock.data; 127 } 128 129 void 130 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, 131 struct nv50_wndw_atom *asyw) 132 { 133 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 134 asyw->image.mode = 0; 135 asyw->image.interval = 1; 136 } 137 138 if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); 139 if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); 140 if (asyw->set.image) wndw->func->image_set(wndw, asyw); 141 142 if (asyw->set.xlut ) { 143 if (asyw->ilut) { 144 asyw->xlut.i.offset = 145 nv50_lut_load(&wndw->ilut, asyw->xlut.i.buffer, 146 asyw->ilut, asyw->xlut.i.load); 147 } 148 wndw->func->xlut_set(wndw, asyw); 149 } 150 151 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); 152 if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); 153 if (asyw->set.blend) wndw->func->blend_set(wndw, asyw); 154 if (asyw->set.point) { 155 if (asyw->set.point = false, asyw->set.mask) 156 interlock[wndw->interlock.type] |= wndw->interlock.data; 157 interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm; 158 159 wndw->immd->point(wndw, asyw); 160 wndw->immd->update(wndw, interlock); 161 } else { 162 interlock[wndw->interlock.type] |= wndw->interlock.data; 163 } 164 } 165 166 void 167 nv50_wndw_ntfy_enable(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) 168 { 169 struct nv50_disp *disp = nv50_disp(wndw->plane.dev); 170 171 asyw->ntfy.handle = wndw->wndw.sync.handle; 172 asyw->ntfy.offset = wndw->ntfy; 173 asyw->ntfy.awaken = false; 174 asyw->set.ntfy = true; 175 176 wndw->func->ntfy_reset(disp->sync, wndw->ntfy); 177 wndw->ntfy ^= 0x10; 178 } 179 180 static void 181 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw, 182 struct nv50_wndw_atom *asyw, 183 struct nv50_head_atom *asyh) 184 { 185 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 186 NV_ATOMIC(drm, "%s release\n", wndw->plane.name); 187 wndw->func->release(wndw, asyw, asyh); 188 asyw->ntfy.handle = 0; 189 asyw->sema.handle = 0; 190 } 191 192 static int 193 nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw) 194 { 195 switch (asyw->state.fb->format->format) { 196 case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break; 197 case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break; 198 default: 199 WARN_ON(1); 200 return -EINVAL; 201 } 202 asyw->image.colorspace = 1; 203 return 0; 204 } 205 206 static int 207 nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) 208 { 209 switch (asyw->state.fb->format->format) { 210 case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; 211 case DRM_FORMAT_XRGB8888 : 212 case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; 213 case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; 214 case DRM_FORMAT_XRGB1555 : 215 case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; 216 case DRM_FORMAT_XBGR2101010 : 217 case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break; 218 case DRM_FORMAT_XBGR8888 : 219 case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; 220 case DRM_FORMAT_XRGB2101010 : 221 case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break; 222 case DRM_FORMAT_XBGR16161616F: 223 case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break; 224 default: 225 return -EINVAL; 226 } 227 asyw->image.colorspace = 0; 228 return 0; 229 } 230 231 static int 232 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, 233 struct nv50_wndw_atom *armw, 234 struct nv50_wndw_atom *asyw, 235 struct nv50_head_atom *asyh) 236 { 237 struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb); 238 struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); 239 int ret; 240 241 NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); 242 243 if (asyw->state.fb != armw->state.fb || !armw->visible || modeset) { 244 asyw->image.w = fb->base.width; 245 asyw->image.h = fb->base.height; 246 asyw->image.kind = fb->nvbo->kind; 247 248 ret = nv50_wndw_atomic_check_acquire_rgb(asyw); 249 if (ret) { 250 ret = nv50_wndw_atomic_check_acquire_yuv(asyw); 251 if (ret) 252 return ret; 253 } 254 255 if (asyw->image.kind) { 256 asyw->image.layout = 0; 257 if (drm->client.device.info.chipset >= 0xc0) 258 asyw->image.blockh = fb->nvbo->mode >> 4; 259 else 260 asyw->image.blockh = fb->nvbo->mode; 261 asyw->image.blocks[0] = fb->base.pitches[0] / 64; 262 asyw->image.pitch[0] = 0; 263 } else { 264 asyw->image.layout = 1; 265 asyw->image.blockh = 0; 266 asyw->image.blocks[0] = 0; 267 asyw->image.pitch[0] = fb->base.pitches[0]; 268 } 269 270 if (!asyh->state.async_flip) 271 asyw->image.interval = 1; 272 else 273 asyw->image.interval = 0; 274 asyw->image.mode = asyw->image.interval ? 0 : 1; 275 asyw->set.image = wndw->func->image_set != NULL; 276 } 277 278 if (wndw->func->scale_set) { 279 asyw->scale.sx = asyw->state.src_x >> 16; 280 asyw->scale.sy = asyw->state.src_y >> 16; 281 asyw->scale.sw = asyw->state.src_w >> 16; 282 asyw->scale.sh = asyw->state.src_h >> 16; 283 asyw->scale.dw = asyw->state.crtc_w; 284 asyw->scale.dh = asyw->state.crtc_h; 285 if (memcmp(&armw->scale, &asyw->scale, sizeof(asyw->scale))) 286 asyw->set.scale = true; 287 } 288 289 if (wndw->func->blend_set) { 290 asyw->blend.depth = 255 - asyw->state.normalized_zpos; 291 asyw->blend.k1 = asyw->state.alpha >> 8; 292 switch (asyw->state.pixel_blend_mode) { 293 case DRM_MODE_BLEND_PREMULTI: 294 asyw->blend.src_color = 2; /* K1 */ 295 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ 296 break; 297 case DRM_MODE_BLEND_COVERAGE: 298 asyw->blend.src_color = 5; /* K1_TIMES_SRC */ 299 asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ 300 break; 301 case DRM_MODE_BLEND_PIXEL_NONE: 302 default: 303 asyw->blend.src_color = 2; /* K1 */ 304 asyw->blend.dst_color = 4; /* NEG_K1 */ 305 break; 306 } 307 if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) 308 asyw->set.blend = true; 309 } 310 311 if (wndw->immd) { 312 asyw->point.x = asyw->state.crtc_x; 313 asyw->point.y = asyw->state.crtc_y; 314 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) 315 asyw->set.point = true; 316 } 317 318 return wndw->func->acquire(wndw, asyw, asyh); 319 } 320 321 static int 322 nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, 323 struct nv50_wndw_atom *armw, 324 struct nv50_wndw_atom *asyw, 325 struct nv50_head_atom *asyh) 326 { 327 struct drm_property_blob *ilut = asyh->state.degamma_lut; 328 329 /* I8 format without an input LUT makes no sense, and the 330 * HW error-checks for this. 331 * 332 * In order to handle legacy gamma, when there's no input 333 * LUT we need to steal the output LUT and use it instead. 334 */ 335 if (!ilut && asyw->state.fb->format->format == DRM_FORMAT_C8) { 336 /* This should be an error, but there's legacy clients 337 * that do a modeset before providing a gamma table. 338 * 339 * We keep the window disabled to avoid angering HW. 340 */ 341 if (!(ilut = asyh->state.gamma_lut)) { 342 asyw->visible = false; 343 return 0; 344 } 345 346 if (wndw->func->ilut) 347 asyh->wndw.olut |= BIT(wndw->id); 348 } else { 349 asyh->wndw.olut &= ~BIT(wndw->id); 350 } 351 352 if (!ilut && wndw->func->ilut_identity && 353 asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F && 354 asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) { 355 static struct drm_property_blob dummy = {}; 356 ilut = &dummy; 357 } 358 359 /* Recalculate LUT state. */ 360 memset(&asyw->xlut, 0x00, sizeof(asyw->xlut)); 361 if ((asyw->ilut = wndw->func->ilut ? ilut : NULL)) { 362 if (!wndw->func->ilut(wndw, asyw, drm_color_lut_size(ilut))) { 363 DRM_DEBUG_KMS("Invalid ilut\n"); 364 return -EINVAL; 365 } 366 asyw->xlut.handle = wndw->wndw.vram.handle; 367 asyw->xlut.i.buffer = !asyw->xlut.i.buffer; 368 asyw->set.xlut = true; 369 } else { 370 asyw->clr.xlut = armw->xlut.handle != 0; 371 } 372 373 /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */ 374 if (wndw->func->olut_core && 375 (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle))) 376 asyw->set.xlut = true; 377 378 if (wndw->func->csc && asyh->state.ctm) { 379 const struct drm_color_ctm *ctm = asyh->state.ctm->data; 380 wndw->func->csc(wndw, asyw, ctm); 381 asyw->csc.valid = true; 382 asyw->set.csc = true; 383 } else { 384 asyw->csc.valid = false; 385 asyw->clr.csc = armw->csc.valid; 386 } 387 388 /* Can't do an immediate flip while changing the LUT. */ 389 asyh->state.async_flip = false; 390 return 0; 391 } 392 393 static int 394 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) 395 { 396 struct nouveau_drm *drm = nouveau_drm(plane->dev); 397 struct nv50_wndw *wndw = nv50_wndw(plane); 398 struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); 399 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 400 struct nv50_head_atom *harm = NULL, *asyh = NULL; 401 bool modeset = false; 402 int ret; 403 404 NV_ATOMIC(drm, "%s atomic_check\n", plane->name); 405 406 /* Fetch the assembly state for the head the window will belong to, 407 * and determine whether the window will be visible. 408 */ 409 if (asyw->state.crtc) { 410 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 411 if (IS_ERR(asyh)) 412 return PTR_ERR(asyh); 413 modeset = drm_atomic_crtc_needs_modeset(&asyh->state); 414 asyw->visible = asyh->state.active; 415 } else { 416 asyw->visible = false; 417 } 418 419 /* Fetch assembly state for the head the window used to belong to. */ 420 if (armw->state.crtc) { 421 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); 422 if (IS_ERR(harm)) 423 return PTR_ERR(harm); 424 } 425 426 /* LUT configuration can potentially cause the window to be disabled. */ 427 if (asyw->visible && wndw->func->xlut_set && 428 (!armw->visible || 429 asyh->state.color_mgmt_changed || 430 asyw->state.fb->format->format != 431 armw->state.fb->format->format)) { 432 ret = nv50_wndw_atomic_check_lut(wndw, armw, asyw, asyh); 433 if (ret) 434 return ret; 435 } 436 437 /* Calculate new window state. */ 438 if (asyw->visible) { 439 ret = nv50_wndw_atomic_check_acquire(wndw, modeset, 440 armw, asyw, asyh); 441 if (ret) 442 return ret; 443 444 asyh->wndw.mask |= BIT(wndw->id); 445 } else 446 if (armw->visible) { 447 nv50_wndw_atomic_check_release(wndw, asyw, harm); 448 harm->wndw.mask &= ~BIT(wndw->id); 449 } else { 450 return 0; 451 } 452 453 /* Aside from the obvious case where the window is actively being 454 * disabled, we might also need to temporarily disable the window 455 * when performing certain modeset operations. 456 */ 457 if (!asyw->visible || modeset) { 458 asyw->clr.ntfy = armw->ntfy.handle != 0; 459 asyw->clr.sema = armw->sema.handle != 0; 460 asyw->clr.xlut = armw->xlut.handle != 0; 461 if (asyw->clr.xlut && asyw->visible) 462 asyw->set.xlut = asyw->xlut.handle != 0; 463 asyw->clr.csc = armw->csc.valid; 464 if (wndw->func->image_clr) 465 asyw->clr.image = armw->image.handle[0] != 0; 466 } 467 468 return 0; 469 } 470 471 static void 472 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) 473 { 474 struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb); 475 struct nouveau_drm *drm = nouveau_drm(plane->dev); 476 477 NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); 478 if (!old_state->fb) 479 return; 480 481 nouveau_bo_unpin(fb->nvbo); 482 } 483 484 static int 485 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) 486 { 487 struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb); 488 struct nouveau_drm *drm = nouveau_drm(plane->dev); 489 struct nv50_wndw *wndw = nv50_wndw(plane); 490 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 491 struct nv50_head_atom *asyh; 492 struct nv50_wndw_ctxdma *ctxdma; 493 int ret; 494 495 NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb); 496 if (!asyw->state.fb) 497 return 0; 498 499 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true); 500 if (ret) 501 return ret; 502 503 if (wndw->ctxdma.parent) { 504 ctxdma = nv50_wndw_ctxdma_new(wndw, fb); 505 if (IS_ERR(ctxdma)) { 506 nouveau_bo_unpin(fb->nvbo); 507 return PTR_ERR(ctxdma); 508 } 509 510 asyw->image.handle[0] = ctxdma->object.handle; 511 } 512 513 asyw->state.fence = dma_resv_get_excl_rcu(fb->nvbo->bo.base.resv); 514 asyw->image.offset[0] = fb->nvbo->offset; 515 516 if (wndw->func->prepare) { 517 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); 518 if (IS_ERR(asyh)) 519 return PTR_ERR(asyh); 520 521 wndw->func->prepare(wndw, asyh, asyw); 522 } 523 524 return 0; 525 } 526 527 static const struct drm_plane_helper_funcs 528 nv50_wndw_helper = { 529 .prepare_fb = nv50_wndw_prepare_fb, 530 .cleanup_fb = nv50_wndw_cleanup_fb, 531 .atomic_check = nv50_wndw_atomic_check, 532 }; 533 534 static void 535 nv50_wndw_atomic_destroy_state(struct drm_plane *plane, 536 struct drm_plane_state *state) 537 { 538 struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); 539 __drm_atomic_helper_plane_destroy_state(&asyw->state); 540 kfree(asyw); 541 } 542 543 static struct drm_plane_state * 544 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) 545 { 546 struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); 547 struct nv50_wndw_atom *asyw; 548 if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) 549 return NULL; 550 __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); 551 asyw->sema = armw->sema; 552 asyw->ntfy = armw->ntfy; 553 asyw->ilut = NULL; 554 asyw->xlut = armw->xlut; 555 asyw->csc = armw->csc; 556 asyw->image = armw->image; 557 asyw->point = armw->point; 558 asyw->clr.mask = 0; 559 asyw->set.mask = 0; 560 return &asyw->state; 561 } 562 563 static int 564 nv50_wndw_zpos_default(struct drm_plane *plane) 565 { 566 return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 567 (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255; 568 } 569 570 static void 571 nv50_wndw_reset(struct drm_plane *plane) 572 { 573 struct nv50_wndw_atom *asyw; 574 575 if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL)))) 576 return; 577 578 if (plane->state) 579 plane->funcs->atomic_destroy_state(plane, plane->state); 580 581 __drm_atomic_helper_plane_reset(plane, &asyw->state); 582 plane->state->zpos = nv50_wndw_zpos_default(plane); 583 plane->state->normalized_zpos = nv50_wndw_zpos_default(plane); 584 } 585 586 static void 587 nv50_wndw_destroy(struct drm_plane *plane) 588 { 589 struct nv50_wndw *wndw = nv50_wndw(plane); 590 struct nv50_wndw_ctxdma *ctxdma, *ctxtmp; 591 592 list_for_each_entry_safe(ctxdma, ctxtmp, &wndw->ctxdma.list, head) { 593 nv50_wndw_ctxdma_del(ctxdma); 594 } 595 596 nvif_notify_fini(&wndw->notify); 597 nv50_dmac_destroy(&wndw->wimm); 598 nv50_dmac_destroy(&wndw->wndw); 599 600 nv50_lut_fini(&wndw->ilut); 601 602 drm_plane_cleanup(&wndw->plane); 603 kfree(wndw); 604 } 605 606 const struct drm_plane_funcs 607 nv50_wndw = { 608 .update_plane = drm_atomic_helper_update_plane, 609 .disable_plane = drm_atomic_helper_disable_plane, 610 .destroy = nv50_wndw_destroy, 611 .reset = nv50_wndw_reset, 612 .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state, 613 .atomic_destroy_state = nv50_wndw_atomic_destroy_state, 614 }; 615 616 static int 617 nv50_wndw_notify(struct nvif_notify *notify) 618 { 619 return NVIF_NOTIFY_KEEP; 620 } 621 622 void 623 nv50_wndw_fini(struct nv50_wndw *wndw) 624 { 625 nvif_notify_put(&wndw->notify); 626 } 627 628 void 629 nv50_wndw_init(struct nv50_wndw *wndw) 630 { 631 nvif_notify_get(&wndw->notify); 632 } 633 634 int 635 nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, 636 enum drm_plane_type type, const char *name, int index, 637 const u32 *format, u32 heads, 638 enum nv50_disp_interlock_type interlock_type, u32 interlock_data, 639 struct nv50_wndw **pwndw) 640 { 641 struct nouveau_drm *drm = nouveau_drm(dev); 642 struct nvif_mmu *mmu = &drm->client.mmu; 643 struct nv50_disp *disp = nv50_disp(dev); 644 struct nv50_wndw *wndw; 645 int nformat; 646 int ret; 647 648 if (!(wndw = *pwndw = kzalloc(sizeof(*wndw), GFP_KERNEL))) 649 return -ENOMEM; 650 wndw->func = func; 651 wndw->id = index; 652 wndw->interlock.type = interlock_type; 653 wndw->interlock.data = interlock_data; 654 655 wndw->ctxdma.parent = &wndw->wndw.base.user; 656 INIT_LIST_HEAD(&wndw->ctxdma.list); 657 658 for (nformat = 0; format[nformat]; nformat++); 659 660 ret = drm_universal_plane_init(dev, &wndw->plane, heads, &nv50_wndw, 661 format, nformat, NULL, 662 type, "%s-%d", name, index); 663 if (ret) { 664 kfree(*pwndw); 665 *pwndw = NULL; 666 return ret; 667 } 668 669 drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); 670 671 if (wndw->func->ilut) { 672 ret = nv50_lut_init(disp, mmu, &wndw->ilut); 673 if (ret) 674 return ret; 675 } 676 677 wndw->notify.func = nv50_wndw_notify; 678 679 if (wndw->func->blend_set) { 680 ret = drm_plane_create_zpos_property(&wndw->plane, 681 nv50_wndw_zpos_default(&wndw->plane), 0, 254); 682 if (ret) 683 return ret; 684 685 ret = drm_plane_create_alpha_property(&wndw->plane); 686 if (ret) 687 return ret; 688 689 ret = drm_plane_create_blend_mode_property(&wndw->plane, 690 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 691 BIT(DRM_MODE_BLEND_PREMULTI) | 692 BIT(DRM_MODE_BLEND_COVERAGE)); 693 if (ret) 694 return ret; 695 } else { 696 ret = drm_plane_create_zpos_immutable_property(&wndw->plane, 697 nv50_wndw_zpos_default(&wndw->plane)); 698 if (ret) 699 return ret; 700 } 701 702 return 0; 703 } 704 705 int 706 nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, 707 struct nv50_wndw **pwndw) 708 { 709 struct { 710 s32 oclass; 711 int version; 712 int (*new)(struct nouveau_drm *, enum drm_plane_type, 713 int, s32, struct nv50_wndw **); 714 } wndws[] = { 715 { TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new }, 716 { GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new }, 717 {} 718 }; 719 struct nv50_disp *disp = nv50_disp(drm->dev); 720 int cid, ret; 721 722 cid = nvif_mclass(&disp->disp->object, wndws); 723 if (cid < 0) { 724 NV_ERROR(drm, "No supported window class\n"); 725 return cid; 726 } 727 728 ret = wndws[cid].new(drm, type, index, wndws[cid].oclass, pwndw); 729 if (ret) 730 return ret; 731 732 return nv50_wimm_init(drm, *pwndw); 733 } 734