1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "head.h" 23 #include "base.h" 24 #include "core.h" 25 #include "curs.h" 26 #include "ovly.h" 27 28 #include <nvif/class.h> 29 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_crtc_helper.h> 32 #include <drm/drm_vblank.h> 33 #include "nouveau_connector.h" 34 void 35 nv50_head_flush_clr(struct nv50_head *head, 36 struct nv50_head_atom *asyh, bool flush) 37 { 38 union nv50_head_atom_mask clr = { 39 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), 40 }; 41 if (clr.olut) head->func->olut_clr(head); 42 if (clr.core) head->func->core_clr(head); 43 if (clr.curs) head->func->curs_clr(head); 44 } 45 46 void 47 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) 48 { 49 if (asyh->set.view ) head->func->view (head, asyh); 50 if (asyh->set.mode ) head->func->mode (head, asyh); 51 if (asyh->set.core ) head->func->core_set(head, asyh); 52 if (asyh->set.olut ) { 53 asyh->olut.offset = nv50_lut_load(&head->olut, 54 asyh->olut.buffer, 55 asyh->state.gamma_lut, 56 asyh->olut.load); 57 head->func->olut_set(head, asyh); 58 } 59 if (asyh->set.curs ) head->func->curs_set(head, asyh); 60 if (asyh->set.base ) head->func->base (head, asyh); 61 if (asyh->set.ovly ) head->func->ovly (head, asyh); 62 if (asyh->set.dither ) head->func->dither (head, asyh); 63 if (asyh->set.procamp) head->func->procamp (head, asyh); 64 if (asyh->set.or ) head->func->or (head, asyh); 65 } 66 67 static void 68 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh, 69 struct nv50_head_atom *asyh, 70 struct nouveau_conn_atom *asyc) 71 { 72 const int vib = asyc->procamp.color_vibrance - 100; 73 const int hue = asyc->procamp.vibrant_hue - 90; 74 const int adj = (vib > 0) ? 50 : 0; 75 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff; 76 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff; 77 asyh->set.procamp = true; 78 } 79 80 static void 81 nv50_head_atomic_check_dither(struct nv50_head_atom *armh, 82 struct nv50_head_atom *asyh, 83 struct nouveau_conn_atom *asyc) 84 { 85 u32 mode = 0x00; 86 87 if (asyc->dither.mode == DITHERING_MODE_AUTO) { 88 if (asyh->base.depth > asyh->or.bpc * 3) 89 mode = DITHERING_MODE_DYNAMIC2X2; 90 } else { 91 mode = asyc->dither.mode; 92 } 93 94 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) { 95 if (asyh->or.bpc >= 8) 96 mode |= DITHERING_DEPTH_8BPC; 97 } else { 98 mode |= asyc->dither.depth; 99 } 100 101 asyh->dither.enable = mode; 102 asyh->dither.bits = mode >> 1; 103 asyh->dither.mode = mode >> 3; 104 asyh->set.dither = true; 105 } 106 107 static void 108 nv50_head_atomic_check_view(struct nv50_head_atom *armh, 109 struct nv50_head_atom *asyh, 110 struct nouveau_conn_atom *asyc) 111 { 112 struct drm_connector *connector = asyc->state.connector; 113 struct drm_display_mode *omode = &asyh->state.adjusted_mode; 114 struct drm_display_mode *umode = &asyh->state.mode; 115 int mode = asyc->scaler.mode; 116 struct edid *edid; 117 int umode_vdisplay, omode_hdisplay, omode_vdisplay; 118 119 if (connector->edid_blob_ptr) 120 edid = (struct edid *)connector->edid_blob_ptr->data; 121 else 122 edid = NULL; 123 124 if (!asyc->scaler.full) { 125 if (mode == DRM_MODE_SCALE_NONE) 126 omode = umode; 127 } else { 128 /* Non-EDID LVDS/eDP mode. */ 129 mode = DRM_MODE_SCALE_FULLSCREEN; 130 } 131 132 /* For the user-specified mode, we must ignore doublescan and 133 * the like, but honor frame packing. 134 */ 135 umode_vdisplay = umode->vdisplay; 136 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 137 umode_vdisplay += umode->vtotal; 138 asyh->view.iW = umode->hdisplay; 139 asyh->view.iH = umode_vdisplay; 140 /* For the output mode, we can just use the stock helper. */ 141 drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay); 142 asyh->view.oW = omode_hdisplay; 143 asyh->view.oH = omode_vdisplay; 144 145 /* Add overscan compensation if necessary, will keep the aspect 146 * ratio the same as the backend mode unless overridden by the 147 * user setting both hborder and vborder properties. 148 */ 149 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON || 150 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO && 151 drm_detect_hdmi_monitor(edid)))) { 152 u32 bX = asyc->scaler.underscan.hborder; 153 u32 bY = asyc->scaler.underscan.vborder; 154 u32 r = (asyh->view.oH << 19) / asyh->view.oW; 155 156 if (bX) { 157 asyh->view.oW -= (bX * 2); 158 if (bY) asyh->view.oH -= (bY * 2); 159 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; 160 } else { 161 asyh->view.oW -= (asyh->view.oW >> 4) + 32; 162 if (bY) asyh->view.oH -= (bY * 2); 163 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; 164 } 165 } 166 167 /* Handle CENTER/ASPECT scaling, taking into account the areas 168 * removed already for overscan compensation. 169 */ 170 switch (mode) { 171 case DRM_MODE_SCALE_CENTER: 172 /* NOTE: This will cause scaling when the input is 173 * larger than the output. 174 */ 175 asyh->view.oW = min(asyh->view.iW, asyh->view.oW); 176 asyh->view.oH = min(asyh->view.iH, asyh->view.oH); 177 break; 178 case DRM_MODE_SCALE_ASPECT: 179 /* Determine whether the scaling should be on width or on 180 * height. This is done by comparing the aspect ratios of the 181 * sizes. If the output AR is larger than input AR, that means 182 * we want to change the width (letterboxed on the 183 * left/right), otherwise on the height (letterboxed on the 184 * top/bottom). 185 * 186 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR 187 * screen will have letterboxes on the left/right. However a 188 * 16:9 (1.777) AR image on that same screen will have 189 * letterboxes on the top/bottom. 190 * 191 * inputAR = iW / iH; outputAR = oW / oH 192 * outputAR > inputAR is equivalent to oW * iH > iW * oH 193 */ 194 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) { 195 /* Recompute output width, i.e. left/right letterbox */ 196 u32 r = (asyh->view.iW << 19) / asyh->view.iH; 197 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19; 198 } else { 199 /* Recompute output height, i.e. top/bottom letterbox */ 200 u32 r = (asyh->view.iH << 19) / asyh->view.iW; 201 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; 202 } 203 break; 204 default: 205 break; 206 } 207 208 asyh->set.view = true; 209 } 210 211 static int 212 nv50_head_atomic_check_lut(struct nv50_head *head, 213 struct nv50_head_atom *asyh) 214 { 215 struct nv50_disp *disp = nv50_disp(head->base.base.dev); 216 struct drm_property_blob *olut = asyh->state.gamma_lut; 217 int size; 218 219 /* Determine whether core output LUT should be enabled. */ 220 if (olut) { 221 /* Check if any window(s) have stolen the core output LUT 222 * to as an input LUT for legacy gamma + I8 colour format. 223 */ 224 if (asyh->wndw.olut) { 225 /* If any window has stolen the core output LUT, 226 * all of them must. 227 */ 228 if (asyh->wndw.olut != asyh->wndw.mask) 229 return -EINVAL; 230 olut = NULL; 231 } 232 } 233 234 if (!olut) { 235 if (!head->func->olut_identity) { 236 asyh->olut.handle = 0; 237 return 0; 238 } 239 size = 0; 240 } else { 241 size = drm_color_lut_size(olut); 242 } 243 244 if (!head->func->olut(head, asyh, size)) { 245 DRM_DEBUG_KMS("Invalid olut\n"); 246 return -EINVAL; 247 } 248 asyh->olut.handle = disp->core->chan.vram.handle; 249 asyh->olut.buffer = !asyh->olut.buffer; 250 251 return 0; 252 } 253 254 static void 255 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) 256 { 257 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 258 struct nv50_head_mode *m = &asyh->mode; 259 u32 blankus; 260 261 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); 262 263 /* 264 * DRM modes are defined in terms of a repeating interval 265 * starting with the active display area. The hardware modes 266 * are defined in terms of a repeating interval starting one 267 * unit (pixel or line) into the sync pulse. So, add bias. 268 */ 269 270 m->h.active = mode->crtc_htotal; 271 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1; 272 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1; 273 m->h.blanks = m->h.blanke + mode->crtc_hdisplay; 274 275 m->v.active = mode->crtc_vtotal; 276 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1; 277 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1; 278 m->v.blanks = m->v.blanke + mode->crtc_vdisplay; 279 280 /*XXX: Safe underestimate, even "0" works */ 281 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active; 282 blankus *= 1000; 283 blankus /= mode->crtc_clock; 284 m->v.blankus = blankus; 285 286 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 287 m->v.blank2e = m->v.active + m->v.blanke; 288 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay; 289 m->v.active = (m->v.active * 2) + 1; 290 m->interlace = true; 291 } else { 292 m->v.blank2e = 0; 293 m->v.blank2s = 1; 294 m->interlace = false; 295 } 296 m->clock = mode->crtc_clock; 297 298 asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); 299 asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); 300 asyh->set.or = head->func->or != NULL; 301 asyh->set.mode = true; 302 } 303 304 static int 305 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) 306 { 307 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 308 struct nv50_head *head = nv50_head(crtc); 309 struct nv50_head_atom *armh = nv50_head_atom(crtc->state); 310 struct nv50_head_atom *asyh = nv50_head_atom(state); 311 struct nouveau_conn_atom *asyc = NULL; 312 struct drm_connector_state *conns; 313 struct drm_connector *conn; 314 int i; 315 316 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active); 317 if (asyh->state.active) { 318 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) { 319 if (conns->crtc == crtc) { 320 asyc = nouveau_conn_atom(conns); 321 break; 322 } 323 } 324 325 if (armh->state.active) { 326 if (asyc) { 327 if (asyh->state.mode_changed) 328 asyc->set.scaler = true; 329 if (armh->base.depth != asyh->base.depth) 330 asyc->set.dither = true; 331 } 332 } else { 333 if (asyc) 334 asyc->set.mask = ~0; 335 asyh->set.mask = ~0; 336 asyh->set.or = head->func->or != NULL; 337 } 338 339 if (asyh->state.mode_changed || asyh->state.connectors_changed) 340 nv50_head_atomic_check_mode(head, asyh); 341 342 if (asyh->state.color_mgmt_changed || 343 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw))) { 344 int ret = nv50_head_atomic_check_lut(head, asyh); 345 if (ret) 346 return ret; 347 348 asyh->olut.visible = asyh->olut.handle != 0; 349 } 350 351 if (asyc) { 352 if (asyc->set.scaler) 353 nv50_head_atomic_check_view(armh, asyh, asyc); 354 if (asyc->set.dither) 355 nv50_head_atomic_check_dither(armh, asyh, asyc); 356 if (asyc->set.procamp) 357 nv50_head_atomic_check_procamp(armh, asyh, asyc); 358 } 359 360 if (head->func->core_calc) { 361 head->func->core_calc(head, asyh); 362 if (!asyh->core.visible) 363 asyh->olut.visible = false; 364 } 365 366 asyh->set.base = armh->base.cpp != asyh->base.cpp; 367 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp; 368 } else { 369 asyh->olut.visible = false; 370 asyh->core.visible = false; 371 asyh->curs.visible = false; 372 asyh->base.cpp = 0; 373 asyh->ovly.cpp = 0; 374 } 375 376 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) { 377 if (asyh->core.visible) { 378 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core))) 379 asyh->set.core = true; 380 } else 381 if (armh->core.visible) { 382 asyh->clr.core = true; 383 } 384 385 if (asyh->curs.visible) { 386 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs))) 387 asyh->set.curs = true; 388 } else 389 if (armh->curs.visible) { 390 asyh->clr.curs = true; 391 } 392 393 if (asyh->olut.visible) { 394 if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut))) 395 asyh->set.olut = true; 396 } else 397 if (armh->olut.visible) { 398 asyh->clr.olut = true; 399 } 400 } else { 401 asyh->clr.olut = armh->olut.visible; 402 asyh->clr.core = armh->core.visible; 403 asyh->clr.curs = armh->curs.visible; 404 asyh->set.olut = asyh->olut.visible; 405 asyh->set.core = asyh->core.visible; 406 asyh->set.curs = asyh->curs.visible; 407 } 408 409 if (asyh->clr.mask || asyh->set.mask) 410 nv50_atom(asyh->state.state)->lock_core = true; 411 return 0; 412 } 413 414 static const struct drm_crtc_helper_funcs 415 nv50_head_help = { 416 .atomic_check = nv50_head_atomic_check, 417 .get_scanout_position = nouveau_display_scanoutpos, 418 }; 419 420 static void 421 nv50_head_atomic_destroy_state(struct drm_crtc *crtc, 422 struct drm_crtc_state *state) 423 { 424 struct nv50_head_atom *asyh = nv50_head_atom(state); 425 __drm_atomic_helper_crtc_destroy_state(&asyh->state); 426 kfree(asyh); 427 } 428 429 static struct drm_crtc_state * 430 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc) 431 { 432 struct nv50_head_atom *armh = nv50_head_atom(crtc->state); 433 struct nv50_head_atom *asyh; 434 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL))) 435 return NULL; 436 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state); 437 asyh->wndw = armh->wndw; 438 asyh->view = armh->view; 439 asyh->mode = armh->mode; 440 asyh->olut = armh->olut; 441 asyh->core = armh->core; 442 asyh->curs = armh->curs; 443 asyh->base = armh->base; 444 asyh->ovly = armh->ovly; 445 asyh->dither = armh->dither; 446 asyh->procamp = armh->procamp; 447 asyh->or = armh->or; 448 asyh->dp = armh->dp; 449 asyh->clr.mask = 0; 450 asyh->set.mask = 0; 451 return &asyh->state; 452 } 453 454 static void 455 nv50_head_reset(struct drm_crtc *crtc) 456 { 457 struct nv50_head_atom *asyh; 458 459 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL)))) 460 return; 461 462 if (crtc->state) 463 nv50_head_atomic_destroy_state(crtc, crtc->state); 464 465 __drm_atomic_helper_crtc_reset(crtc, &asyh->state); 466 } 467 468 static void 469 nv50_head_destroy(struct drm_crtc *crtc) 470 { 471 struct nv50_head *head = nv50_head(crtc); 472 nv50_lut_fini(&head->olut); 473 drm_crtc_cleanup(crtc); 474 kfree(head); 475 } 476 477 static const struct drm_crtc_funcs 478 nv50_head_func = { 479 .reset = nv50_head_reset, 480 .gamma_set = drm_atomic_helper_legacy_gamma_set, 481 .destroy = nv50_head_destroy, 482 .set_config = drm_atomic_helper_set_config, 483 .page_flip = drm_atomic_helper_page_flip, 484 .atomic_duplicate_state = nv50_head_atomic_duplicate_state, 485 .atomic_destroy_state = nv50_head_atomic_destroy_state, 486 .enable_vblank = nouveau_display_vblank_enable, 487 .disable_vblank = nouveau_display_vblank_disable, 488 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 489 }; 490 491 struct nv50_head * 492 nv50_head_create(struct drm_device *dev, int index) 493 { 494 struct nouveau_drm *drm = nouveau_drm(dev); 495 struct nv50_disp *disp = nv50_disp(dev); 496 struct nv50_head *head; 497 struct nv50_wndw *base, *ovly, *curs; 498 struct drm_crtc *crtc; 499 int ret; 500 501 head = kzalloc(sizeof(*head), GFP_KERNEL); 502 if (!head) 503 return ERR_PTR(-ENOMEM); 504 505 head->func = disp->core->func->head; 506 head->base.index = index; 507 508 if (disp->disp->object.oclass < GV100_DISP) { 509 ret = nv50_base_new(drm, head->base.index, &base); 510 ret = nv50_ovly_new(drm, head->base.index, &ovly); 511 } else { 512 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY, 513 head->base.index * 2 + 0, &base); 514 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY, 515 head->base.index * 2 + 1, &ovly); 516 } 517 if (ret == 0) 518 ret = nv50_curs_new(drm, head->base.index, &curs); 519 if (ret) { 520 kfree(head); 521 return ERR_PTR(ret); 522 } 523 524 crtc = &head->base.base; 525 drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane, 526 &nv50_head_func, "head-%d", head->base.index); 527 drm_crtc_helper_add(crtc, &nv50_head_help); 528 /* Keep the legacy gamma size at 256 to avoid compatibility issues */ 529 drm_mode_crtc_set_gamma_size(crtc, 256); 530 drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size, 531 disp->disp->object.oclass >= GF110_DISP, 532 head->func->olut_size); 533 534 if (head->func->olut_set) { 535 ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut); 536 if (ret) { 537 nv50_head_destroy(crtc); 538 return ERR_PTR(ret); 539 } 540 } 541 542 return head; 543 } 544