1 /*
2  * Copyright 2018 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "head.h"
23 #include "base.h"
24 #include "core.h"
25 #include "curs.h"
26 #include "ovly.h"
27 #include "crc.h"
28 
29 #include <nvif/class.h>
30 #include <nvif/event.h>
31 #include <nvif/cl0046.h>
32 
33 #include <drm/drm_atomic.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_vblank.h>
37 #include "nouveau_connector.h"
38 
39 void
40 nv50_head_flush_clr(struct nv50_head *head,
41 		    struct nv50_head_atom *asyh, bool flush)
42 {
43 	union nv50_head_atom_mask clr = {
44 		.mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask),
45 	};
46 	if (clr.crc)  nv50_crc_atomic_clr(head);
47 	if (clr.olut) head->func->olut_clr(head);
48 	if (clr.core) head->func->core_clr(head);
49 	if (clr.curs) head->func->curs_clr(head);
50 }
51 
52 void
53 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
54 {
55 	if (asyh->set.view   ) head->func->view    (head, asyh);
56 	if (asyh->set.mode   ) head->func->mode    (head, asyh);
57 	if (asyh->set.core   ) head->func->core_set(head, asyh);
58 	if (asyh->set.olut   ) {
59 		asyh->olut.offset = nv50_lut_load(&head->olut,
60 						  asyh->olut.buffer,
61 						  asyh->state.gamma_lut,
62 						  asyh->olut.load);
63 		head->func->olut_set(head, asyh);
64 	}
65 	if (asyh->set.curs   ) head->func->curs_set(head, asyh);
66 	if (asyh->set.base   ) head->func->base    (head, asyh);
67 	if (asyh->set.ovly   ) head->func->ovly    (head, asyh);
68 	if (asyh->set.dither ) head->func->dither  (head, asyh);
69 	if (asyh->set.procamp) head->func->procamp (head, asyh);
70 	if (asyh->set.crc    ) nv50_crc_atomic_set (head, asyh);
71 	if (asyh->set.or     ) head->func->or      (head, asyh);
72 }
73 
74 static void
75 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
76 			       struct nv50_head_atom *asyh,
77 			       struct nouveau_conn_atom *asyc)
78 {
79 	const int vib = asyc->procamp.color_vibrance - 100;
80 	const int hue = asyc->procamp.vibrant_hue - 90;
81 	const int adj = (vib > 0) ? 50 : 0;
82 	asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
83 	asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
84 	asyh->set.procamp = true;
85 }
86 
87 static void
88 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
89 			      struct nv50_head_atom *asyh,
90 			      struct nouveau_conn_atom *asyc)
91 {
92 	u32 mode = 0x00;
93 
94 	if (asyc->dither.mode) {
95 		if (asyc->dither.mode == DITHERING_MODE_AUTO) {
96 			if (asyh->base.depth > asyh->or.bpc * 3)
97 				mode = DITHERING_MODE_DYNAMIC2X2;
98 		} else {
99 			mode = asyc->dither.mode;
100 		}
101 
102 		if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
103 			if (asyh->or.bpc >= 8)
104 				mode |= DITHERING_DEPTH_8BPC;
105 		} else {
106 			mode |= asyc->dither.depth;
107 		}
108 	}
109 
110 	asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);
111 	asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS);
112 	asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE);
113 	asyh->set.dither = true;
114 }
115 
116 static void
117 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
118 			    struct nv50_head_atom *asyh,
119 			    struct nouveau_conn_atom *asyc)
120 {
121 	struct drm_connector *connector = asyc->state.connector;
122 	struct drm_display_mode *omode = &asyh->state.adjusted_mode;
123 	struct drm_display_mode *umode = &asyh->state.mode;
124 	int mode = asyc->scaler.mode;
125 	struct edid *edid;
126 	int umode_vdisplay, omode_hdisplay, omode_vdisplay;
127 
128 	if (connector->edid_blob_ptr)
129 		edid = (struct edid *)connector->edid_blob_ptr->data;
130 	else
131 		edid = NULL;
132 
133 	if (!asyc->scaler.full) {
134 		if (mode == DRM_MODE_SCALE_NONE)
135 			omode = umode;
136 	} else {
137 		/* Non-EDID LVDS/eDP mode. */
138 		mode = DRM_MODE_SCALE_FULLSCREEN;
139 	}
140 
141 	/* For the user-specified mode, we must ignore doublescan and
142 	 * the like, but honor frame packing.
143 	 */
144 	umode_vdisplay = umode->vdisplay;
145 	if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
146 		umode_vdisplay += umode->vtotal;
147 	asyh->view.iW = umode->hdisplay;
148 	asyh->view.iH = umode_vdisplay;
149 	/* For the output mode, we can just use the stock helper. */
150 	drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay);
151 	asyh->view.oW = omode_hdisplay;
152 	asyh->view.oH = omode_vdisplay;
153 
154 	/* Add overscan compensation if necessary, will keep the aspect
155 	 * ratio the same as the backend mode unless overridden by the
156 	 * user setting both hborder and vborder properties.
157 	 */
158 	if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
159 	    (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
160 	     drm_detect_hdmi_monitor(edid)))) {
161 		u32 bX = asyc->scaler.underscan.hborder;
162 		u32 bY = asyc->scaler.underscan.vborder;
163 		u32 r = (asyh->view.oH << 19) / asyh->view.oW;
164 
165 		if (bX) {
166 			asyh->view.oW -= (bX * 2);
167 			if (bY) asyh->view.oH -= (bY * 2);
168 			else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
169 		} else {
170 			asyh->view.oW -= (asyh->view.oW >> 4) + 32;
171 			if (bY) asyh->view.oH -= (bY * 2);
172 			else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
173 		}
174 	}
175 
176 	/* Handle CENTER/ASPECT scaling, taking into account the areas
177 	 * removed already for overscan compensation.
178 	 */
179 	switch (mode) {
180 	case DRM_MODE_SCALE_CENTER:
181 		/* NOTE: This will cause scaling when the input is
182 		 * larger than the output.
183 		 */
184 		asyh->view.oW = min(asyh->view.iW, asyh->view.oW);
185 		asyh->view.oH = min(asyh->view.iH, asyh->view.oH);
186 		break;
187 	case DRM_MODE_SCALE_ASPECT:
188 		/* Determine whether the scaling should be on width or on
189 		 * height. This is done by comparing the aspect ratios of the
190 		 * sizes. If the output AR is larger than input AR, that means
191 		 * we want to change the width (letterboxed on the
192 		 * left/right), otherwise on the height (letterboxed on the
193 		 * top/bottom).
194 		 *
195 		 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR
196 		 * screen will have letterboxes on the left/right. However a
197 		 * 16:9 (1.777) AR image on that same screen will have
198 		 * letterboxes on the top/bottom.
199 		 *
200 		 * inputAR = iW / iH; outputAR = oW / oH
201 		 * outputAR > inputAR is equivalent to oW * iH > iW * oH
202 		 */
203 		if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) {
204 			/* Recompute output width, i.e. left/right letterbox */
205 			u32 r = (asyh->view.iW << 19) / asyh->view.iH;
206 			asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
207 		} else {
208 			/* Recompute output height, i.e. top/bottom letterbox */
209 			u32 r = (asyh->view.iH << 19) / asyh->view.iW;
210 			asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
211 		}
212 		break;
213 	default:
214 		break;
215 	}
216 
217 	asyh->set.view = true;
218 }
219 
220 static int
221 nv50_head_atomic_check_lut(struct nv50_head *head,
222 			   struct nv50_head_atom *asyh)
223 {
224 	struct nv50_disp *disp = nv50_disp(head->base.base.dev);
225 	struct drm_property_blob *olut = asyh->state.gamma_lut;
226 	int size;
227 
228 	/* Determine whether core output LUT should be enabled. */
229 	if (olut) {
230 		/* Check if any window(s) have stolen the core output LUT
231 		 * to as an input LUT for legacy gamma + I8 colour format.
232 		 */
233 		if (asyh->wndw.olut) {
234 			/* If any window has stolen the core output LUT,
235 			 * all of them must.
236 			 */
237 			if (asyh->wndw.olut != asyh->wndw.mask)
238 				return -EINVAL;
239 			olut = NULL;
240 		}
241 	}
242 
243 	if (!olut) {
244 		if (!head->func->olut_identity) {
245 			asyh->olut.handle = 0;
246 			return 0;
247 		}
248 		size = 0;
249 	} else {
250 		size = drm_color_lut_size(olut);
251 	}
252 
253 	if (!head->func->olut(head, asyh, size)) {
254 		DRM_DEBUG_KMS("Invalid olut\n");
255 		return -EINVAL;
256 	}
257 	asyh->olut.handle = disp->core->chan.vram.handle;
258 	asyh->olut.buffer = !asyh->olut.buffer;
259 
260 	return 0;
261 }
262 
263 static void
264 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
265 {
266 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;
267 	struct nv50_head_mode *m = &asyh->mode;
268 	u32 blankus;
269 
270 	drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
271 
272 	/*
273 	 * DRM modes are defined in terms of a repeating interval
274 	 * starting with the active display area.  The hardware modes
275 	 * are defined in terms of a repeating interval starting one
276 	 * unit (pixel or line) into the sync pulse.  So, add bias.
277 	 */
278 
279 	m->h.active = mode->crtc_htotal;
280 	m->h.synce  = mode->crtc_hsync_end - mode->crtc_hsync_start - 1;
281 	m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1;
282 	m->h.blanks = m->h.blanke + mode->crtc_hdisplay;
283 
284 	m->v.active = mode->crtc_vtotal;
285 	m->v.synce  = mode->crtc_vsync_end - mode->crtc_vsync_start - 1;
286 	m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1;
287 	m->v.blanks = m->v.blanke + mode->crtc_vdisplay;
288 
289 	/*XXX: Safe underestimate, even "0" works */
290 	blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active;
291 	blankus *= 1000;
292 	blankus /= mode->crtc_clock;
293 	m->v.blankus = blankus;
294 
295 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
296 		m->v.blank2e =  m->v.active + m->v.blanke;
297 		m->v.blank2s =  m->v.blank2e + mode->crtc_vdisplay;
298 		m->v.active  = (m->v.active * 2) + 1;
299 		m->interlace = true;
300 	} else {
301 		m->v.blank2e = 0;
302 		m->v.blank2s = 1;
303 		m->interlace = false;
304 	}
305 	m->clock = mode->crtc_clock;
306 
307 	asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
308 	asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
309 	asyh->set.or = head->func->or != NULL;
310 	asyh->set.mode = true;
311 }
312 
313 static int
314 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
315 {
316 	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
317 									      crtc);
318 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
319 									  crtc);
320 	struct nouveau_drm *drm = nouveau_drm(crtc->dev);
321 	struct nv50_head *head = nv50_head(crtc);
322 	struct nv50_head_atom *armh = nv50_head_atom(old_crtc_state);
323 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
324 	struct nouveau_conn_atom *asyc = NULL;
325 	struct drm_connector_state *conns;
326 	struct drm_connector *conn;
327 	int i, ret;
328 
329 	NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
330 	if (asyh->state.active) {
331 		for_each_new_connector_in_state(asyh->state.state, conn, conns, i) {
332 			if (conns->crtc == crtc) {
333 				asyc = nouveau_conn_atom(conns);
334 				break;
335 			}
336 		}
337 
338 		if (armh->state.active) {
339 			if (asyc) {
340 				if (asyh->state.mode_changed)
341 					asyc->set.scaler = true;
342 				if (armh->base.depth != asyh->base.depth)
343 					asyc->set.dither = true;
344 			}
345 		} else {
346 			if (asyc)
347 				asyc->set.mask = ~0;
348 			asyh->set.mask = ~0;
349 			asyh->set.or = head->func->or != NULL;
350 		}
351 
352 		if (asyh->state.mode_changed || asyh->state.connectors_changed)
353 			nv50_head_atomic_check_mode(head, asyh);
354 
355 		if (asyh->state.color_mgmt_changed ||
356 		    memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw))) {
357 			int ret = nv50_head_atomic_check_lut(head, asyh);
358 			if (ret)
359 				return ret;
360 
361 			asyh->olut.visible = asyh->olut.handle != 0;
362 		}
363 
364 		if (asyc) {
365 			if (asyc->set.scaler)
366 				nv50_head_atomic_check_view(armh, asyh, asyc);
367 			if (asyc->set.dither)
368 				nv50_head_atomic_check_dither(armh, asyh, asyc);
369 			if (asyc->set.procamp)
370 				nv50_head_atomic_check_procamp(armh, asyh, asyc);
371 		}
372 
373 		if (head->func->core_calc) {
374 			head->func->core_calc(head, asyh);
375 			if (!asyh->core.visible)
376 				asyh->olut.visible = false;
377 		}
378 
379 		asyh->set.base = armh->base.cpp != asyh->base.cpp;
380 		asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
381 	} else {
382 		asyh->olut.visible = false;
383 		asyh->core.visible = false;
384 		asyh->curs.visible = false;
385 		asyh->base.cpp = 0;
386 		asyh->ovly.cpp = 0;
387 	}
388 
389 	if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
390 		if (asyh->core.visible) {
391 			if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
392 				asyh->set.core = true;
393 		} else
394 		if (armh->core.visible) {
395 			asyh->clr.core = true;
396 		}
397 
398 		if (asyh->curs.visible) {
399 			if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
400 				asyh->set.curs = true;
401 		} else
402 		if (armh->curs.visible) {
403 			asyh->clr.curs = true;
404 		}
405 
406 		if (asyh->olut.visible) {
407 			if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut)))
408 				asyh->set.olut = true;
409 		} else
410 		if (armh->olut.visible) {
411 			asyh->clr.olut = true;
412 		}
413 	} else {
414 		asyh->clr.olut = armh->olut.visible;
415 		asyh->clr.core = armh->core.visible;
416 		asyh->clr.curs = armh->curs.visible;
417 		asyh->set.olut = asyh->olut.visible;
418 		asyh->set.core = asyh->core.visible;
419 		asyh->set.curs = asyh->curs.visible;
420 	}
421 
422 	ret = nv50_crc_atomic_check_head(head, asyh, armh);
423 	if (ret)
424 		return ret;
425 
426 	if (asyh->clr.mask || asyh->set.mask)
427 		nv50_atom(asyh->state.state)->lock_core = true;
428 	return 0;
429 }
430 
431 static const struct drm_crtc_helper_funcs
432 nv50_head_help = {
433 	.atomic_check = nv50_head_atomic_check,
434 	.get_scanout_position = nouveau_display_scanoutpos,
435 };
436 
437 static void
438 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
439 			       struct drm_crtc_state *state)
440 {
441 	struct nv50_head_atom *asyh = nv50_head_atom(state);
442 	__drm_atomic_helper_crtc_destroy_state(&asyh->state);
443 	kfree(asyh);
444 }
445 
446 static struct drm_crtc_state *
447 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
448 {
449 	struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
450 	struct nv50_head_atom *asyh;
451 	if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
452 		return NULL;
453 	__drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
454 	asyh->wndw = armh->wndw;
455 	asyh->view = armh->view;
456 	asyh->mode = armh->mode;
457 	asyh->olut = armh->olut;
458 	asyh->core = armh->core;
459 	asyh->curs = armh->curs;
460 	asyh->base = armh->base;
461 	asyh->ovly = armh->ovly;
462 	asyh->dither = armh->dither;
463 	asyh->procamp = armh->procamp;
464 	asyh->crc = armh->crc;
465 	asyh->or = armh->or;
466 	asyh->dp = armh->dp;
467 	asyh->clr.mask = 0;
468 	asyh->set.mask = 0;
469 	return &asyh->state;
470 }
471 
472 static void
473 nv50_head_reset(struct drm_crtc *crtc)
474 {
475 	struct nv50_head_atom *asyh;
476 
477 	if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
478 		return;
479 
480 	if (crtc->state)
481 		nv50_head_atomic_destroy_state(crtc, crtc->state);
482 
483 	__drm_atomic_helper_crtc_reset(crtc, &asyh->state);
484 }
485 
486 static int
487 nv50_head_late_register(struct drm_crtc *crtc)
488 {
489 	return nv50_head_crc_late_register(nv50_head(crtc));
490 }
491 
492 static void
493 nv50_head_destroy(struct drm_crtc *crtc)
494 {
495 	struct nv50_head *head = nv50_head(crtc);
496 
497 	nvif_notify_dtor(&head->base.vblank);
498 	nv50_lut_fini(&head->olut);
499 	drm_crtc_cleanup(crtc);
500 	kfree(head);
501 }
502 
503 static const struct drm_crtc_funcs
504 nv50_head_func = {
505 	.reset = nv50_head_reset,
506 	.destroy = nv50_head_destroy,
507 	.set_config = drm_atomic_helper_set_config,
508 	.page_flip = drm_atomic_helper_page_flip,
509 	.atomic_duplicate_state = nv50_head_atomic_duplicate_state,
510 	.atomic_destroy_state = nv50_head_atomic_destroy_state,
511 	.enable_vblank = nouveau_display_vblank_enable,
512 	.disable_vblank = nouveau_display_vblank_disable,
513 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
514 	.late_register = nv50_head_late_register,
515 };
516 
517 static const struct drm_crtc_funcs
518 nvd9_head_func = {
519 	.reset = nv50_head_reset,
520 	.destroy = nv50_head_destroy,
521 	.set_config = drm_atomic_helper_set_config,
522 	.page_flip = drm_atomic_helper_page_flip,
523 	.atomic_duplicate_state = nv50_head_atomic_duplicate_state,
524 	.atomic_destroy_state = nv50_head_atomic_destroy_state,
525 	.enable_vblank = nouveau_display_vblank_enable,
526 	.disable_vblank = nouveau_display_vblank_disable,
527 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
528 	.verify_crc_source = nv50_crc_verify_source,
529 	.get_crc_sources = nv50_crc_get_sources,
530 	.set_crc_source = nv50_crc_set_source,
531 	.late_register = nv50_head_late_register,
532 };
533 
534 static int nv50_head_vblank_handler(struct nvif_notify *notify)
535 {
536 	struct nouveau_crtc *nv_crtc =
537 		container_of(notify, struct nouveau_crtc, vblank);
538 
539 	if (drm_crtc_handle_vblank(&nv_crtc->base))
540 		nv50_crc_handle_vblank(nv50_head(&nv_crtc->base));
541 
542 	return NVIF_NOTIFY_KEEP;
543 }
544 
545 struct nv50_head *
546 nv50_head_create(struct drm_device *dev, int index)
547 {
548 	struct nouveau_drm *drm = nouveau_drm(dev);
549 	struct nv50_disp *disp = nv50_disp(dev);
550 	struct nv50_head *head;
551 	struct nv50_wndw *base, *ovly, *curs;
552 	struct nouveau_crtc *nv_crtc;
553 	struct drm_crtc *crtc;
554 	const struct drm_crtc_funcs *funcs;
555 	int ret;
556 
557 	head = kzalloc(sizeof(*head), GFP_KERNEL);
558 	if (!head)
559 		return ERR_PTR(-ENOMEM);
560 
561 	head->func = disp->core->func->head;
562 	head->base.index = index;
563 
564 	if (disp->disp->object.oclass < GF110_DISP)
565 		funcs = &nv50_head_func;
566 	else
567 		funcs = &nvd9_head_func;
568 
569 	if (disp->disp->object.oclass < GV100_DISP) {
570 		ret = nv50_base_new(drm, head->base.index, &base);
571 		ret = nv50_ovly_new(drm, head->base.index, &ovly);
572 	} else {
573 		ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY,
574 				    head->base.index * 2 + 0, &base);
575 		ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY,
576 				    head->base.index * 2 + 1, &ovly);
577 	}
578 	if (ret == 0)
579 		ret = nv50_curs_new(drm, head->base.index, &curs);
580 	if (ret) {
581 		kfree(head);
582 		return ERR_PTR(ret);
583 	}
584 
585 	nv_crtc = &head->base;
586 	crtc = &nv_crtc->base;
587 	drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane,
588 				  funcs, "head-%d", head->base.index);
589 	drm_crtc_helper_add(crtc, &nv50_head_help);
590 	/* Keep the legacy gamma size at 256 to avoid compatibility issues */
591 	drm_mode_crtc_set_gamma_size(crtc, 256);
592 	drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size,
593 				   disp->disp->object.oclass >= GF110_DISP,
594 				   head->func->olut_size);
595 
596 	if (head->func->olut_set) {
597 		ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut);
598 		if (ret) {
599 			nv50_head_destroy(crtc);
600 			return ERR_PTR(ret);
601 		}
602 	}
603 
604 	ret = nvif_notify_ctor(&disp->disp->object, "kmsVbl", nv50_head_vblank_handler,
605 			       false, NV04_DISP_NTFY_VBLANK,
606 			       &(struct nvif_notify_head_req_v0) {
607 				    .head = nv_crtc->index,
608 			       },
609 			       sizeof(struct nvif_notify_head_req_v0),
610 			       sizeof(struct nvif_notify_head_rep_v0),
611 			       &nv_crtc->vblank);
612 	if (ret)
613 		return ERR_PTR(ret);
614 
615 	return head;
616 }
617