1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 30 #include <linux/dma-mapping.h> 31 #include <linux/hdmi.h> 32 #include <linux/component.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_fb_helper.h> 38 #include <drm/drm_plane_helper.h> 39 #include <drm/drm_probe_helper.h> 40 #include <drm/drm_scdc_helper.h> 41 #include <drm/drm_vblank.h> 42 43 #include <nvif/class.h> 44 #include <nvif/cl0002.h> 45 #include <nvif/cl5070.h> 46 #include <nvif/cl507d.h> 47 #include <nvif/event.h> 48 #include <nvif/timer.h> 49 50 #include "nouveau_drv.h" 51 #include "nouveau_dma.h" 52 #include "nouveau_gem.h" 53 #include "nouveau_connector.h" 54 #include "nouveau_encoder.h" 55 #include "nouveau_fence.h" 56 #include "nouveau_fbcon.h" 57 58 #include <subdev/bios/dp.h> 59 60 /****************************************************************************** 61 * Atomic state 62 *****************************************************************************/ 63 64 struct nv50_outp_atom { 65 struct list_head head; 66 67 struct drm_encoder *encoder; 68 bool flush_disable; 69 70 union nv50_outp_atom_mask { 71 struct { 72 bool ctrl:1; 73 }; 74 u8 mask; 75 } set, clr; 76 }; 77 78 /****************************************************************************** 79 * EVO channel 80 *****************************************************************************/ 81 82 static int 83 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 84 const s32 *oclass, u8 head, void *data, u32 size, 85 struct nv50_chan *chan) 86 { 87 struct nvif_sclass *sclass; 88 int ret, i, n; 89 90 chan->device = device; 91 92 ret = n = nvif_object_sclass_get(disp, &sclass); 93 if (ret < 0) 94 return ret; 95 96 while (oclass[0]) { 97 for (i = 0; i < n; i++) { 98 if (sclass[i].oclass == oclass[0]) { 99 ret = nvif_object_init(disp, 0, oclass[0], 100 data, size, &chan->user); 101 if (ret == 0) 102 nvif_object_map(&chan->user, NULL, 0); 103 nvif_object_sclass_put(&sclass); 104 return ret; 105 } 106 } 107 oclass++; 108 } 109 110 nvif_object_sclass_put(&sclass); 111 return -ENOSYS; 112 } 113 114 static void 115 nv50_chan_destroy(struct nv50_chan *chan) 116 { 117 nvif_object_fini(&chan->user); 118 } 119 120 /****************************************************************************** 121 * DMA EVO channel 122 *****************************************************************************/ 123 124 void 125 nv50_dmac_destroy(struct nv50_dmac *dmac) 126 { 127 nvif_object_fini(&dmac->vram); 128 nvif_object_fini(&dmac->sync); 129 130 nv50_chan_destroy(&dmac->base); 131 132 nvif_mem_fini(&dmac->push); 133 } 134 135 int 136 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 137 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 138 struct nv50_dmac *dmac) 139 { 140 struct nouveau_cli *cli = (void *)device->object.client; 141 struct nv50_disp_core_channel_dma_v0 *args = data; 142 u8 type = NVIF_MEM_COHERENT; 143 int ret; 144 145 mutex_init(&dmac->lock); 146 147 /* Pascal added support for 47-bit physical addresses, but some 148 * parts of EVO still only accept 40-bit PAs. 149 * 150 * To avoid issues on systems with large amounts of RAM, and on 151 * systems where an IOMMU maps pages at a high address, we need 152 * to allocate push buffers in VRAM instead. 153 * 154 * This appears to match NVIDIA's behaviour on Pascal. 155 */ 156 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 157 type |= NVIF_MEM_VRAM; 158 159 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push); 160 if (ret) 161 return ret; 162 163 dmac->ptr = dmac->push.object.map.ptr; 164 165 args->pushbuf = nvif_handle(&dmac->push.object); 166 167 ret = nv50_chan_create(device, disp, oclass, head, data, size, 168 &dmac->base); 169 if (ret) 170 return ret; 171 172 if (!syncbuf) 173 return 0; 174 175 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, 176 &(struct nv_dma_v0) { 177 .target = NV_DMA_V0_TARGET_VRAM, 178 .access = NV_DMA_V0_ACCESS_RDWR, 179 .start = syncbuf + 0x0000, 180 .limit = syncbuf + 0x0fff, 181 }, sizeof(struct nv_dma_v0), 182 &dmac->sync); 183 if (ret) 184 return ret; 185 186 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, 187 &(struct nv_dma_v0) { 188 .target = NV_DMA_V0_TARGET_VRAM, 189 .access = NV_DMA_V0_ACCESS_RDWR, 190 .start = 0, 191 .limit = device->info.ram_user - 1, 192 }, sizeof(struct nv_dma_v0), 193 &dmac->vram); 194 if (ret) 195 return ret; 196 197 return ret; 198 } 199 200 /****************************************************************************** 201 * EVO channel helpers 202 *****************************************************************************/ 203 static void 204 evo_flush(struct nv50_dmac *dmac) 205 { 206 /* Push buffer fetches are not coherent with BAR1, we need to ensure 207 * writes have been flushed right through to VRAM before writing PUT. 208 */ 209 if (dmac->push.type & NVIF_MEM_VRAM) { 210 struct nvif_device *device = dmac->base.device; 211 nvif_wr32(&device->object, 0x070000, 0x00000001); 212 nvif_msec(device, 2000, 213 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 214 break; 215 ); 216 } 217 } 218 219 u32 * 220 evo_wait(struct nv50_dmac *evoc, int nr) 221 { 222 struct nv50_dmac *dmac = evoc; 223 struct nvif_device *device = dmac->base.device; 224 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; 225 226 mutex_lock(&dmac->lock); 227 if (put + nr >= (PAGE_SIZE / 4) - 8) { 228 dmac->ptr[put] = 0x20000000; 229 evo_flush(dmac); 230 231 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); 232 if (nvif_msec(device, 2000, 233 if (!nvif_rd32(&dmac->base.user, 0x0004)) 234 break; 235 ) < 0) { 236 mutex_unlock(&dmac->lock); 237 pr_err("nouveau: evo channel stalled\n"); 238 return NULL; 239 } 240 241 put = 0; 242 } 243 244 return dmac->ptr + put; 245 } 246 247 void 248 evo_kick(u32 *push, struct nv50_dmac *evoc) 249 { 250 struct nv50_dmac *dmac = evoc; 251 252 evo_flush(dmac); 253 254 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); 255 mutex_unlock(&dmac->lock); 256 } 257 258 /****************************************************************************** 259 * Output path helpers 260 *****************************************************************************/ 261 static void 262 nv50_outp_release(struct nouveau_encoder *nv_encoder) 263 { 264 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 265 struct { 266 struct nv50_disp_mthd_v1 base; 267 } args = { 268 .base.version = 1, 269 .base.method = NV50_DISP_MTHD_V1_RELEASE, 270 .base.hasht = nv_encoder->dcb->hasht, 271 .base.hashm = nv_encoder->dcb->hashm, 272 }; 273 274 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 275 nv_encoder->or = -1; 276 nv_encoder->link = 0; 277 } 278 279 static int 280 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda) 281 { 282 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 283 struct nv50_disp *disp = nv50_disp(drm->dev); 284 struct { 285 struct nv50_disp_mthd_v1 base; 286 struct nv50_disp_acquire_v0 info; 287 } args = { 288 .base.version = 1, 289 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 290 .base.hasht = nv_encoder->dcb->hasht, 291 .base.hashm = nv_encoder->dcb->hashm, 292 .info.hda = hda, 293 }; 294 int ret; 295 296 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 297 if (ret) { 298 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 299 return ret; 300 } 301 302 nv_encoder->or = args.info.or; 303 nv_encoder->link = args.info.link; 304 return 0; 305 } 306 307 static int 308 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 309 struct drm_crtc_state *crtc_state, 310 struct drm_connector_state *conn_state, 311 struct drm_display_mode *native_mode) 312 { 313 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 314 struct drm_display_mode *mode = &crtc_state->mode; 315 struct drm_connector *connector = conn_state->connector; 316 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 317 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 318 319 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 320 asyc->scaler.full = false; 321 if (!native_mode) 322 return 0; 323 324 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 325 switch (connector->connector_type) { 326 case DRM_MODE_CONNECTOR_LVDS: 327 case DRM_MODE_CONNECTOR_eDP: 328 /* Don't force scaler for EDID modes with 329 * same size as the native one (e.g. different 330 * refresh rate) 331 */ 332 if (mode->hdisplay == native_mode->hdisplay && 333 mode->vdisplay == native_mode->vdisplay && 334 mode->type & DRM_MODE_TYPE_DRIVER) 335 break; 336 mode = native_mode; 337 asyc->scaler.full = true; 338 break; 339 default: 340 break; 341 } 342 } else { 343 mode = native_mode; 344 } 345 346 if (!drm_mode_equal(adjusted_mode, mode)) { 347 drm_mode_copy(adjusted_mode, mode); 348 crtc_state->mode_changed = true; 349 } 350 351 return 0; 352 } 353 354 static int 355 nv50_outp_atomic_check(struct drm_encoder *encoder, 356 struct drm_crtc_state *crtc_state, 357 struct drm_connector_state *conn_state) 358 { 359 struct drm_connector *connector = conn_state->connector; 360 struct nouveau_connector *nv_connector = nouveau_connector(connector); 361 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 362 int ret; 363 364 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 365 nv_connector->native_mode); 366 if (ret) 367 return ret; 368 369 if (crtc_state->mode_changed || crtc_state->connectors_changed) 370 asyh->or.bpc = connector->display_info.bpc; 371 372 return 0; 373 } 374 375 /****************************************************************************** 376 * DAC 377 *****************************************************************************/ 378 static void 379 nv50_dac_disable(struct drm_encoder *encoder) 380 { 381 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 382 struct nv50_core *core = nv50_disp(encoder->dev)->core; 383 if (nv_encoder->crtc) 384 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); 385 nv_encoder->crtc = NULL; 386 nv50_outp_release(nv_encoder); 387 } 388 389 static void 390 nv50_dac_enable(struct drm_encoder *encoder) 391 { 392 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 393 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 394 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 395 struct nv50_core *core = nv50_disp(encoder->dev)->core; 396 397 nv50_outp_acquire(nv_encoder, false); 398 399 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); 400 asyh->or.depth = 0; 401 402 nv_encoder->crtc = encoder->crtc; 403 } 404 405 static enum drm_connector_status 406 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 407 { 408 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 409 struct nv50_disp *disp = nv50_disp(encoder->dev); 410 struct { 411 struct nv50_disp_mthd_v1 base; 412 struct nv50_disp_dac_load_v0 load; 413 } args = { 414 .base.version = 1, 415 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 416 .base.hasht = nv_encoder->dcb->hasht, 417 .base.hashm = nv_encoder->dcb->hashm, 418 }; 419 int ret; 420 421 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 422 if (args.load.data == 0) 423 args.load.data = 340; 424 425 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 426 if (ret || !args.load.load) 427 return connector_status_disconnected; 428 429 return connector_status_connected; 430 } 431 432 static const struct drm_encoder_helper_funcs 433 nv50_dac_help = { 434 .atomic_check = nv50_outp_atomic_check, 435 .enable = nv50_dac_enable, 436 .disable = nv50_dac_disable, 437 .detect = nv50_dac_detect 438 }; 439 440 static void 441 nv50_dac_destroy(struct drm_encoder *encoder) 442 { 443 drm_encoder_cleanup(encoder); 444 kfree(encoder); 445 } 446 447 static const struct drm_encoder_funcs 448 nv50_dac_func = { 449 .destroy = nv50_dac_destroy, 450 }; 451 452 static int 453 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 454 { 455 struct nouveau_drm *drm = nouveau_drm(connector->dev); 456 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 457 struct nvkm_i2c_bus *bus; 458 struct nouveau_encoder *nv_encoder; 459 struct drm_encoder *encoder; 460 int type = DRM_MODE_ENCODER_DAC; 461 462 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 463 if (!nv_encoder) 464 return -ENOMEM; 465 nv_encoder->dcb = dcbe; 466 467 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 468 if (bus) 469 nv_encoder->i2c = &bus->i2c; 470 471 encoder = to_drm_encoder(nv_encoder); 472 encoder->possible_crtcs = dcbe->heads; 473 encoder->possible_clones = 0; 474 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 475 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 476 drm_encoder_helper_add(encoder, &nv50_dac_help); 477 478 drm_connector_attach_encoder(connector, encoder); 479 return 0; 480 } 481 482 /* 483 * audio component binding for ELD notification 484 */ 485 static void 486 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 487 int dev_id) 488 { 489 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 490 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 491 port, dev_id); 492 } 493 494 static int 495 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 496 bool *enabled, unsigned char *buf, int max_bytes) 497 { 498 struct drm_device *drm_dev = dev_get_drvdata(kdev); 499 struct nouveau_drm *drm = nouveau_drm(drm_dev); 500 struct drm_encoder *encoder; 501 struct nouveau_encoder *nv_encoder; 502 struct nouveau_connector *nv_connector; 503 struct nouveau_crtc *nv_crtc; 504 int ret = 0; 505 506 *enabled = false; 507 drm_for_each_encoder(encoder, drm->dev) { 508 nv_encoder = nouveau_encoder(encoder); 509 nv_connector = nouveau_encoder_connector_get(nv_encoder); 510 nv_crtc = nouveau_crtc(encoder->crtc); 511 if (!nv_connector || !nv_crtc || nv_encoder->or != port || 512 nv_crtc->index != dev_id) 513 continue; 514 *enabled = nv_encoder->audio; 515 if (*enabled) { 516 ret = drm_eld_size(nv_connector->base.eld); 517 memcpy(buf, nv_connector->base.eld, 518 min(max_bytes, ret)); 519 } 520 break; 521 } 522 return ret; 523 } 524 525 static const struct drm_audio_component_ops nv50_audio_component_ops = { 526 .get_eld = nv50_audio_component_get_eld, 527 }; 528 529 static int 530 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 531 void *data) 532 { 533 struct drm_device *drm_dev = dev_get_drvdata(kdev); 534 struct nouveau_drm *drm = nouveau_drm(drm_dev); 535 struct drm_audio_component *acomp = data; 536 537 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 538 return -ENOMEM; 539 540 drm_modeset_lock_all(drm_dev); 541 acomp->ops = &nv50_audio_component_ops; 542 acomp->dev = kdev; 543 drm->audio.component = acomp; 544 drm_modeset_unlock_all(drm_dev); 545 return 0; 546 } 547 548 static void 549 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 550 void *data) 551 { 552 struct drm_device *drm_dev = dev_get_drvdata(kdev); 553 struct nouveau_drm *drm = nouveau_drm(drm_dev); 554 struct drm_audio_component *acomp = data; 555 556 drm_modeset_lock_all(drm_dev); 557 drm->audio.component = NULL; 558 acomp->ops = NULL; 559 acomp->dev = NULL; 560 drm_modeset_unlock_all(drm_dev); 561 } 562 563 static const struct component_ops nv50_audio_component_bind_ops = { 564 .bind = nv50_audio_component_bind, 565 .unbind = nv50_audio_component_unbind, 566 }; 567 568 static void 569 nv50_audio_component_init(struct nouveau_drm *drm) 570 { 571 if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 572 drm->audio.component_registered = true; 573 } 574 575 static void 576 nv50_audio_component_fini(struct nouveau_drm *drm) 577 { 578 if (drm->audio.component_registered) { 579 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 580 drm->audio.component_registered = false; 581 } 582 } 583 584 /****************************************************************************** 585 * Audio 586 *****************************************************************************/ 587 static void 588 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 589 { 590 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 591 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 592 struct nv50_disp *disp = nv50_disp(encoder->dev); 593 struct { 594 struct nv50_disp_mthd_v1 base; 595 struct nv50_disp_sor_hda_eld_v0 eld; 596 } args = { 597 .base.version = 1, 598 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 599 .base.hasht = nv_encoder->dcb->hasht, 600 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 601 (0x0100 << nv_crtc->index), 602 }; 603 604 nv_encoder->audio = false; 605 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 606 607 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 608 nv_crtc->index); 609 } 610 611 static void 612 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 613 { 614 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 615 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 616 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 617 struct nouveau_connector *nv_connector; 618 struct nv50_disp *disp = nv50_disp(encoder->dev); 619 struct __packed { 620 struct { 621 struct nv50_disp_mthd_v1 mthd; 622 struct nv50_disp_sor_hda_eld_v0 eld; 623 } base; 624 u8 data[sizeof(nv_connector->base.eld)]; 625 } args = { 626 .base.mthd.version = 1, 627 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 628 .base.mthd.hasht = nv_encoder->dcb->hasht, 629 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 630 (0x0100 << nv_crtc->index), 631 }; 632 633 nv_connector = nouveau_encoder_connector_get(nv_encoder); 634 if (!drm_detect_monitor_audio(nv_connector->edid)) 635 return; 636 637 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 638 639 nvif_mthd(&disp->disp->object, 0, &args, 640 sizeof(args.base) + drm_eld_size(args.data)); 641 nv_encoder->audio = true; 642 643 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 644 nv_crtc->index); 645 } 646 647 /****************************************************************************** 648 * HDMI 649 *****************************************************************************/ 650 static void 651 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 652 { 653 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 654 struct nv50_disp *disp = nv50_disp(encoder->dev); 655 struct { 656 struct nv50_disp_mthd_v1 base; 657 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 658 } args = { 659 .base.version = 1, 660 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 661 .base.hasht = nv_encoder->dcb->hasht, 662 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 663 (0x0100 << nv_crtc->index), 664 }; 665 666 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 667 } 668 669 static void 670 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 671 { 672 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 673 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 674 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 675 struct nv50_disp *disp = nv50_disp(encoder->dev); 676 struct { 677 struct nv50_disp_mthd_v1 base; 678 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 679 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 680 } args = { 681 .base.version = 1, 682 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 683 .base.hasht = nv_encoder->dcb->hasht, 684 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 685 (0x0100 << nv_crtc->index), 686 .pwr.state = 1, 687 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 688 }; 689 struct nouveau_connector *nv_connector; 690 struct drm_hdmi_info *hdmi; 691 u32 max_ac_packet; 692 union hdmi_infoframe avi_frame; 693 union hdmi_infoframe vendor_frame; 694 bool high_tmds_clock_ratio = false, scrambling = false; 695 u8 config; 696 int ret; 697 int size; 698 699 nv_connector = nouveau_encoder_connector_get(nv_encoder); 700 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 701 return; 702 703 hdmi = &nv_connector->base.display_info.hdmi; 704 705 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 706 &nv_connector->base, mode); 707 if (!ret) { 708 /* We have an AVI InfoFrame, populate it to the display */ 709 args.pwr.avi_infoframe_length 710 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 711 } 712 713 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 714 &nv_connector->base, mode); 715 if (!ret) { 716 /* We have a Vendor InfoFrame, populate it to the display */ 717 args.pwr.vendor_infoframe_length 718 = hdmi_infoframe_pack(&vendor_frame, 719 args.infoframes 720 + args.pwr.avi_infoframe_length, 721 17); 722 } 723 724 max_ac_packet = mode->htotal - mode->hdisplay; 725 max_ac_packet -= args.pwr.rekey; 726 max_ac_packet -= 18; /* constant from tegra */ 727 args.pwr.max_ac_packet = max_ac_packet / 32; 728 729 if (hdmi->scdc.scrambling.supported) { 730 high_tmds_clock_ratio = mode->clock > 340000; 731 scrambling = high_tmds_clock_ratio || 732 hdmi->scdc.scrambling.low_rates; 733 } 734 735 args.pwr.scdc = 736 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 737 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 738 739 size = sizeof(args.base) 740 + sizeof(args.pwr) 741 + args.pwr.avi_infoframe_length 742 + args.pwr.vendor_infoframe_length; 743 nvif_mthd(&disp->disp->object, 0, &args, size); 744 745 nv50_audio_enable(encoder, mode); 746 747 /* If SCDC is supported by the downstream monitor, update 748 * divider / scrambling settings to what we programmed above. 749 */ 750 if (!hdmi->scdc.scrambling.supported) 751 return; 752 753 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 754 if (ret < 0) { 755 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 756 return; 757 } 758 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 759 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 760 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 761 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 762 if (ret < 0) 763 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 764 config, ret); 765 } 766 767 /****************************************************************************** 768 * MST 769 *****************************************************************************/ 770 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 771 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 772 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 773 774 struct nv50_mstm { 775 struct nouveau_encoder *outp; 776 777 struct drm_dp_mst_topology_mgr mgr; 778 779 bool modified; 780 bool disabled; 781 int links; 782 }; 783 784 struct nv50_mstc { 785 struct nv50_mstm *mstm; 786 struct drm_dp_mst_port *port; 787 struct drm_connector connector; 788 789 struct drm_display_mode *native; 790 struct edid *edid; 791 }; 792 793 struct nv50_msto { 794 struct drm_encoder encoder; 795 796 struct nv50_head *head; 797 struct nv50_mstc *mstc; 798 bool disabled; 799 }; 800 801 static struct drm_dp_payload * 802 nv50_msto_payload(struct nv50_msto *msto) 803 { 804 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 805 struct nv50_mstc *mstc = msto->mstc; 806 struct nv50_mstm *mstm = mstc->mstm; 807 int vcpi = mstc->port->vcpi.vcpi, i; 808 809 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 810 811 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 812 for (i = 0; i < mstm->mgr.max_payloads; i++) { 813 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 814 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 815 mstm->outp->base.base.name, i, payload->vcpi, 816 payload->start_slot, payload->num_slots); 817 } 818 819 for (i = 0; i < mstm->mgr.max_payloads; i++) { 820 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 821 if (payload->vcpi == vcpi) 822 return payload; 823 } 824 825 return NULL; 826 } 827 828 static void 829 nv50_msto_cleanup(struct nv50_msto *msto) 830 { 831 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 832 struct nv50_mstc *mstc = msto->mstc; 833 struct nv50_mstm *mstm = mstc->mstm; 834 835 if (!msto->disabled) 836 return; 837 838 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 839 840 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 841 842 msto->mstc = NULL; 843 msto->disabled = false; 844 } 845 846 static void 847 nv50_msto_prepare(struct nv50_msto *msto) 848 { 849 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 850 struct nv50_mstc *mstc = msto->mstc; 851 struct nv50_mstm *mstm = mstc->mstm; 852 struct { 853 struct nv50_disp_mthd_v1 base; 854 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 855 } args = { 856 .base.version = 1, 857 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 858 .base.hasht = mstm->outp->dcb->hasht, 859 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 860 (0x0100 << msto->head->base.index), 861 }; 862 863 mutex_lock(&mstm->mgr.payload_lock); 864 865 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 866 if (mstc->port->vcpi.vcpi > 0) { 867 struct drm_dp_payload *payload = nv50_msto_payload(msto); 868 if (payload) { 869 args.vcpi.start_slot = payload->start_slot; 870 args.vcpi.num_slots = payload->num_slots; 871 args.vcpi.pbn = mstc->port->vcpi.pbn; 872 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 873 } 874 } 875 876 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 877 msto->encoder.name, msto->head->base.base.name, 878 args.vcpi.start_slot, args.vcpi.num_slots, 879 args.vcpi.pbn, args.vcpi.aligned_pbn); 880 881 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 882 mutex_unlock(&mstm->mgr.payload_lock); 883 } 884 885 static int 886 nv50_msto_atomic_check(struct drm_encoder *encoder, 887 struct drm_crtc_state *crtc_state, 888 struct drm_connector_state *conn_state) 889 { 890 struct drm_atomic_state *state = crtc_state->state; 891 struct drm_connector *connector = conn_state->connector; 892 struct nv50_mstc *mstc = nv50_mstc(connector); 893 struct nv50_mstm *mstm = mstc->mstm; 894 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 895 int slots; 896 int ret; 897 898 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 899 mstc->native); 900 if (ret) 901 return ret; 902 903 if (!crtc_state->mode_changed && !crtc_state->connectors_changed) 904 return 0; 905 906 /* 907 * When restoring duplicated states, we need to make sure that the bw 908 * remains the same and avoid recalculating it, as the connector's bpc 909 * may have changed after the state was duplicated 910 */ 911 if (!state->duplicated) { 912 const int clock = crtc_state->adjusted_mode.clock; 913 914 asyh->or.bpc = connector->display_info.bpc; 915 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 916 false); 917 } 918 919 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, 920 asyh->dp.pbn, 0); 921 if (slots < 0) 922 return slots; 923 924 asyh->dp.tu = slots; 925 926 return 0; 927 } 928 929 static u8 930 nv50_dp_bpc_to_depth(unsigned int bpc) 931 { 932 switch (bpc) { 933 case 6: return 0x2; 934 case 8: return 0x5; 935 case 10: /* fall-through */ 936 default: return 0x6; 937 } 938 } 939 940 static void 941 nv50_msto_enable(struct drm_encoder *encoder) 942 { 943 struct nv50_head *head = nv50_head(encoder->crtc); 944 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state); 945 struct nv50_msto *msto = nv50_msto(encoder); 946 struct nv50_mstc *mstc = NULL; 947 struct nv50_mstm *mstm = NULL; 948 struct drm_connector *connector; 949 struct drm_connector_list_iter conn_iter; 950 u8 proto; 951 bool r; 952 953 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 954 drm_for_each_connector_iter(connector, &conn_iter) { 955 if (connector->state->best_encoder == &msto->encoder) { 956 mstc = nv50_mstc(connector); 957 mstm = mstc->mstm; 958 break; 959 } 960 } 961 drm_connector_list_iter_end(&conn_iter); 962 963 if (WARN_ON(!mstc)) 964 return; 965 966 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, 967 armh->dp.tu); 968 if (!r) 969 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 970 971 if (!mstm->links++) 972 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); 973 974 if (mstm->outp->link & 1) 975 proto = 0x8; 976 else 977 proto = 0x9; 978 979 mstm->outp->update(mstm->outp, head->base.index, armh, proto, 980 nv50_dp_bpc_to_depth(armh->or.bpc)); 981 982 msto->mstc = mstc; 983 mstm->modified = true; 984 } 985 986 static void 987 nv50_msto_disable(struct drm_encoder *encoder) 988 { 989 struct nv50_msto *msto = nv50_msto(encoder); 990 struct nv50_mstc *mstc = msto->mstc; 991 struct nv50_mstm *mstm = mstc->mstm; 992 993 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 994 995 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 996 mstm->modified = true; 997 if (!--mstm->links) 998 mstm->disabled = true; 999 msto->disabled = true; 1000 } 1001 1002 static const struct drm_encoder_helper_funcs 1003 nv50_msto_help = { 1004 .disable = nv50_msto_disable, 1005 .enable = nv50_msto_enable, 1006 .atomic_check = nv50_msto_atomic_check, 1007 }; 1008 1009 static void 1010 nv50_msto_destroy(struct drm_encoder *encoder) 1011 { 1012 struct nv50_msto *msto = nv50_msto(encoder); 1013 drm_encoder_cleanup(&msto->encoder); 1014 kfree(msto); 1015 } 1016 1017 static const struct drm_encoder_funcs 1018 nv50_msto = { 1019 .destroy = nv50_msto_destroy, 1020 }; 1021 1022 static struct nv50_msto * 1023 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1024 { 1025 struct nv50_msto *msto; 1026 int ret; 1027 1028 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1029 if (!msto) 1030 return ERR_PTR(-ENOMEM); 1031 1032 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1033 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1034 if (ret) { 1035 kfree(msto); 1036 return ERR_PTR(ret); 1037 } 1038 1039 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1040 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1041 msto->head = head; 1042 return msto; 1043 } 1044 1045 static struct drm_encoder * 1046 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1047 struct drm_connector_state *connector_state) 1048 { 1049 struct nv50_mstc *mstc = nv50_mstc(connector); 1050 struct drm_crtc *crtc = connector_state->crtc; 1051 1052 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1053 return NULL; 1054 1055 return &nv50_head(crtc)->msto->encoder; 1056 } 1057 1058 static enum drm_mode_status 1059 nv50_mstc_mode_valid(struct drm_connector *connector, 1060 struct drm_display_mode *mode) 1061 { 1062 struct nv50_mstc *mstc = nv50_mstc(connector); 1063 struct nouveau_encoder *outp = mstc->mstm->outp; 1064 1065 /* TODO: calculate the PBN from the dotclock and validate against the 1066 * MSTB's max possible PBN 1067 */ 1068 1069 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1070 } 1071 1072 static int 1073 nv50_mstc_get_modes(struct drm_connector *connector) 1074 { 1075 struct nv50_mstc *mstc = nv50_mstc(connector); 1076 int ret = 0; 1077 1078 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1079 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1080 if (mstc->edid) 1081 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1082 1083 /* 1084 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1085 * to 8 to save bandwidth on the topology. In the future, we'll want 1086 * to properly fix this by dynamically selecting the highest possible 1087 * bpc that would fit in the topology 1088 */ 1089 if (connector->display_info.bpc) 1090 connector->display_info.bpc = 1091 clamp(connector->display_info.bpc, 6U, 8U); 1092 else 1093 connector->display_info.bpc = 8; 1094 1095 if (mstc->native) 1096 drm_mode_destroy(mstc->connector.dev, mstc->native); 1097 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1098 return ret; 1099 } 1100 1101 static int 1102 nv50_mstc_atomic_check(struct drm_connector *connector, 1103 struct drm_atomic_state *state) 1104 { 1105 struct nv50_mstc *mstc = nv50_mstc(connector); 1106 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1107 struct drm_connector_state *new_conn_state = 1108 drm_atomic_get_new_connector_state(state, connector); 1109 struct drm_connector_state *old_conn_state = 1110 drm_atomic_get_old_connector_state(state, connector); 1111 struct drm_crtc_state *crtc_state; 1112 struct drm_crtc *new_crtc = new_conn_state->crtc; 1113 1114 if (!old_conn_state->crtc) 1115 return 0; 1116 1117 /* We only want to free VCPI if this state disables the CRTC on this 1118 * connector 1119 */ 1120 if (new_crtc) { 1121 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 1122 1123 if (!crtc_state || 1124 !drm_atomic_crtc_needs_modeset(crtc_state) || 1125 crtc_state->enable) 1126 return 0; 1127 } 1128 1129 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 1130 } 1131 1132 static int 1133 nv50_mstc_detect(struct drm_connector *connector, 1134 struct drm_modeset_acquire_ctx *ctx, bool force) 1135 { 1136 struct nv50_mstc *mstc = nv50_mstc(connector); 1137 int ret; 1138 1139 if (drm_connector_is_unregistered(connector)) 1140 return connector_status_disconnected; 1141 1142 ret = pm_runtime_get_sync(connector->dev->dev); 1143 if (ret < 0 && ret != -EACCES) { 1144 pm_runtime_put_autosuspend(connector->dev->dev); 1145 return connector_status_disconnected; 1146 } 1147 1148 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1149 mstc->port); 1150 1151 pm_runtime_mark_last_busy(connector->dev->dev); 1152 pm_runtime_put_autosuspend(connector->dev->dev); 1153 return ret; 1154 } 1155 1156 static const struct drm_connector_helper_funcs 1157 nv50_mstc_help = { 1158 .get_modes = nv50_mstc_get_modes, 1159 .mode_valid = nv50_mstc_mode_valid, 1160 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1161 .atomic_check = nv50_mstc_atomic_check, 1162 .detect_ctx = nv50_mstc_detect, 1163 }; 1164 1165 static void 1166 nv50_mstc_destroy(struct drm_connector *connector) 1167 { 1168 struct nv50_mstc *mstc = nv50_mstc(connector); 1169 1170 drm_connector_cleanup(&mstc->connector); 1171 drm_dp_mst_put_port_malloc(mstc->port); 1172 1173 kfree(mstc); 1174 } 1175 1176 static const struct drm_connector_funcs 1177 nv50_mstc = { 1178 .reset = nouveau_conn_reset, 1179 .fill_modes = drm_helper_probe_single_connector_modes, 1180 .destroy = nv50_mstc_destroy, 1181 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1182 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1183 .atomic_set_property = nouveau_conn_atomic_set_property, 1184 .atomic_get_property = nouveau_conn_atomic_get_property, 1185 }; 1186 1187 static int 1188 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1189 const char *path, struct nv50_mstc **pmstc) 1190 { 1191 struct drm_device *dev = mstm->outp->base.base.dev; 1192 struct drm_crtc *crtc; 1193 struct nv50_mstc *mstc; 1194 int ret; 1195 1196 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1197 return -ENOMEM; 1198 mstc->mstm = mstm; 1199 mstc->port = port; 1200 1201 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1202 DRM_MODE_CONNECTOR_DisplayPort); 1203 if (ret) { 1204 kfree(*pmstc); 1205 *pmstc = NULL; 1206 return ret; 1207 } 1208 1209 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1210 1211 mstc->connector.funcs->reset(&mstc->connector); 1212 nouveau_conn_attach_properties(&mstc->connector); 1213 1214 drm_for_each_crtc(crtc, dev) { 1215 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1216 continue; 1217 1218 drm_connector_attach_encoder(&mstc->connector, 1219 &nv50_head(crtc)->msto->encoder); 1220 } 1221 1222 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1223 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1224 drm_connector_set_path_property(&mstc->connector, path); 1225 drm_dp_mst_get_port_malloc(port); 1226 return 0; 1227 } 1228 1229 static void 1230 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1231 { 1232 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1233 struct drm_encoder *encoder; 1234 int ret; 1235 1236 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1237 ret = drm_dp_check_act_status(&mstm->mgr); 1238 1239 ret = drm_dp_update_payload_part2(&mstm->mgr); 1240 1241 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1242 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1243 struct nv50_msto *msto = nv50_msto(encoder); 1244 struct nv50_mstc *mstc = msto->mstc; 1245 if (mstc && mstc->mstm == mstm) 1246 nv50_msto_cleanup(msto); 1247 } 1248 } 1249 1250 mstm->modified = false; 1251 } 1252 1253 static void 1254 nv50_mstm_prepare(struct nv50_mstm *mstm) 1255 { 1256 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1257 struct drm_encoder *encoder; 1258 int ret; 1259 1260 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1261 ret = drm_dp_update_payload_part1(&mstm->mgr); 1262 1263 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1264 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1265 struct nv50_msto *msto = nv50_msto(encoder); 1266 struct nv50_mstc *mstc = msto->mstc; 1267 if (mstc && mstc->mstm == mstm) 1268 nv50_msto_prepare(msto); 1269 } 1270 } 1271 1272 if (mstm->disabled) { 1273 if (!mstm->links) 1274 nv50_outp_release(mstm->outp); 1275 mstm->disabled = false; 1276 } 1277 } 1278 1279 static struct drm_connector * 1280 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1281 struct drm_dp_mst_port *port, const char *path) 1282 { 1283 struct nv50_mstm *mstm = nv50_mstm(mgr); 1284 struct nv50_mstc *mstc; 1285 int ret; 1286 1287 ret = nv50_mstc_new(mstm, port, path, &mstc); 1288 if (ret) 1289 return NULL; 1290 1291 return &mstc->connector; 1292 } 1293 1294 static const struct drm_dp_mst_topology_cbs 1295 nv50_mstm = { 1296 .add_connector = nv50_mstm_add_connector, 1297 }; 1298 1299 void 1300 nv50_mstm_service(struct nv50_mstm *mstm) 1301 { 1302 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1303 bool handled = true; 1304 int ret; 1305 u8 esi[8] = {}; 1306 1307 if (!aux) 1308 return; 1309 1310 while (handled) { 1311 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1312 if (ret != 8) { 1313 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1314 return; 1315 } 1316 1317 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1318 if (!handled) 1319 break; 1320 1321 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1322 } 1323 } 1324 1325 void 1326 nv50_mstm_remove(struct nv50_mstm *mstm) 1327 { 1328 if (mstm) 1329 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1330 } 1331 1332 static int 1333 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1334 { 1335 struct nouveau_encoder *outp = mstm->outp; 1336 struct { 1337 struct nv50_disp_mthd_v1 base; 1338 struct nv50_disp_sor_dp_mst_link_v0 mst; 1339 } args = { 1340 .base.version = 1, 1341 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1342 .base.hasht = outp->dcb->hasht, 1343 .base.hashm = outp->dcb->hashm, 1344 .mst.state = state, 1345 }; 1346 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1347 struct nvif_object *disp = &drm->display->disp.object; 1348 int ret; 1349 1350 if (dpcd >= 0x12) { 1351 /* Even if we're enabling MST, start with disabling the 1352 * branching unit to clear any sink-side MST topology state 1353 * that wasn't set by us 1354 */ 1355 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0); 1356 if (ret < 0) 1357 return ret; 1358 1359 if (state) { 1360 /* Now, start initializing */ 1361 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 1362 DP_MST_EN); 1363 if (ret < 0) 1364 return ret; 1365 } 1366 } 1367 1368 return nvif_mthd(disp, 0, &args, sizeof(args)); 1369 } 1370 1371 int 1372 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1373 { 1374 struct drm_dp_aux *aux; 1375 int ret; 1376 bool old_state, new_state; 1377 u8 mstm_ctrl; 1378 1379 if (!mstm) 1380 return 0; 1381 1382 mutex_lock(&mstm->mgr.lock); 1383 1384 old_state = mstm->mgr.mst_state; 1385 new_state = old_state; 1386 aux = mstm->mgr.aux; 1387 1388 if (old_state) { 1389 /* Just check that the MST hub is still as we expect it */ 1390 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl); 1391 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) { 1392 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n"); 1393 new_state = false; 1394 } 1395 } else if (dpcd[0] >= 0x12) { 1396 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); 1397 if (ret < 0) 1398 goto probe_error; 1399 1400 if (!(dpcd[1] & DP_MST_CAP)) 1401 dpcd[0] = 0x11; 1402 else 1403 new_state = allow; 1404 } 1405 1406 if (new_state == old_state) { 1407 mutex_unlock(&mstm->mgr.lock); 1408 return new_state; 1409 } 1410 1411 ret = nv50_mstm_enable(mstm, dpcd[0], new_state); 1412 if (ret) 1413 goto probe_error; 1414 1415 mutex_unlock(&mstm->mgr.lock); 1416 1417 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state); 1418 if (ret) 1419 return nv50_mstm_enable(mstm, dpcd[0], 0); 1420 1421 return new_state; 1422 1423 probe_error: 1424 mutex_unlock(&mstm->mgr.lock); 1425 return ret; 1426 } 1427 1428 static void 1429 nv50_mstm_fini(struct nv50_mstm *mstm) 1430 { 1431 if (mstm && mstm->mgr.mst_state) 1432 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1433 } 1434 1435 static void 1436 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime) 1437 { 1438 int ret; 1439 1440 if (!mstm || !mstm->mgr.mst_state) 1441 return; 1442 1443 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1444 if (ret == -1) { 1445 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1446 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1447 } 1448 } 1449 1450 static void 1451 nv50_mstm_del(struct nv50_mstm **pmstm) 1452 { 1453 struct nv50_mstm *mstm = *pmstm; 1454 if (mstm) { 1455 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1456 kfree(*pmstm); 1457 *pmstm = NULL; 1458 } 1459 } 1460 1461 static int 1462 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1463 int conn_base_id, struct nv50_mstm **pmstm) 1464 { 1465 const int max_payloads = hweight8(outp->dcb->heads); 1466 struct drm_device *dev = outp->base.base.dev; 1467 struct nv50_mstm *mstm; 1468 int ret; 1469 u8 dpcd; 1470 1471 /* This is a workaround for some monitors not functioning 1472 * correctly in MST mode on initial module load. I think 1473 * some bad interaction with the VBIOS may be responsible. 1474 * 1475 * A good ol' off and on again seems to work here ;) 1476 */ 1477 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1478 if (ret >= 0 && dpcd >= 0x12) 1479 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1480 1481 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1482 return -ENOMEM; 1483 mstm->outp = outp; 1484 mstm->mgr.cbs = &nv50_mstm; 1485 1486 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1487 max_payloads, conn_base_id); 1488 if (ret) 1489 return ret; 1490 1491 return 0; 1492 } 1493 1494 /****************************************************************************** 1495 * SOR 1496 *****************************************************************************/ 1497 static void 1498 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1499 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1500 { 1501 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1502 struct nv50_core *core = disp->core; 1503 1504 if (!asyh) { 1505 nv_encoder->ctrl &= ~BIT(head); 1506 if (!(nv_encoder->ctrl & 0x0000000f)) 1507 nv_encoder->ctrl = 0; 1508 } else { 1509 nv_encoder->ctrl |= proto << 8; 1510 nv_encoder->ctrl |= BIT(head); 1511 asyh->or.depth = depth; 1512 } 1513 1514 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1515 } 1516 1517 static void 1518 nv50_sor_disable(struct drm_encoder *encoder) 1519 { 1520 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1521 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1522 1523 nv_encoder->crtc = NULL; 1524 1525 if (nv_crtc) { 1526 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1527 u8 pwr; 1528 1529 if (aux) { 1530 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1531 if (ret == 0) { 1532 pwr &= ~DP_SET_POWER_MASK; 1533 pwr |= DP_SET_POWER_D3; 1534 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1535 } 1536 } 1537 1538 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1539 nv50_audio_disable(encoder, nv_crtc); 1540 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1541 nv50_outp_release(nv_encoder); 1542 } 1543 } 1544 1545 static void 1546 nv50_sor_enable(struct drm_encoder *encoder) 1547 { 1548 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1549 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1550 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1551 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1552 struct { 1553 struct nv50_disp_mthd_v1 base; 1554 struct nv50_disp_sor_lvds_script_v0 lvds; 1555 } lvds = { 1556 .base.version = 1, 1557 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1558 .base.hasht = nv_encoder->dcb->hasht, 1559 .base.hashm = nv_encoder->dcb->hashm, 1560 }; 1561 struct nv50_disp *disp = nv50_disp(encoder->dev); 1562 struct drm_device *dev = encoder->dev; 1563 struct nouveau_drm *drm = nouveau_drm(dev); 1564 struct nouveau_connector *nv_connector; 1565 struct nvbios *bios = &drm->vbios; 1566 bool hda = false; 1567 u8 proto = 0xf; 1568 u8 depth = 0x0; 1569 1570 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1571 nv_encoder->crtc = encoder->crtc; 1572 1573 if ((disp->disp->object.oclass == GT214_DISP || 1574 disp->disp->object.oclass >= GF110_DISP) && 1575 drm_detect_monitor_audio(nv_connector->edid)) 1576 hda = true; 1577 nv50_outp_acquire(nv_encoder, hda); 1578 1579 switch (nv_encoder->dcb->type) { 1580 case DCB_OUTPUT_TMDS: 1581 if (nv_encoder->link & 1) { 1582 proto = 0x1; 1583 /* Only enable dual-link if: 1584 * - Need to (i.e. rate > 165MHz) 1585 * - DCB says we can 1586 * - Not an HDMI monitor, since there's no dual-link 1587 * on HDMI. 1588 */ 1589 if (mode->clock >= 165000 && 1590 nv_encoder->dcb->duallink_possible && 1591 !drm_detect_hdmi_monitor(nv_connector->edid)) 1592 proto |= 0x4; 1593 } else { 1594 proto = 0x2; 1595 } 1596 1597 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1598 break; 1599 case DCB_OUTPUT_LVDS: 1600 proto = 0x0; 1601 1602 if (bios->fp_no_ddc) { 1603 if (bios->fp.dual_link) 1604 lvds.lvds.script |= 0x0100; 1605 if (bios->fp.if_is_24bit) 1606 lvds.lvds.script |= 0x0200; 1607 } else { 1608 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1609 if (((u8 *)nv_connector->edid)[121] == 2) 1610 lvds.lvds.script |= 0x0100; 1611 } else 1612 if (mode->clock >= bios->fp.duallink_transition_clk) { 1613 lvds.lvds.script |= 0x0100; 1614 } 1615 1616 if (lvds.lvds.script & 0x0100) { 1617 if (bios->fp.strapless_is_24bit & 2) 1618 lvds.lvds.script |= 0x0200; 1619 } else { 1620 if (bios->fp.strapless_is_24bit & 1) 1621 lvds.lvds.script |= 0x0200; 1622 } 1623 1624 if (asyh->or.bpc == 8) 1625 lvds.lvds.script |= 0x0200; 1626 } 1627 1628 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1629 break; 1630 case DCB_OUTPUT_DP: 1631 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1632 1633 if (nv_encoder->link & 1) 1634 proto = 0x8; 1635 else 1636 proto = 0x9; 1637 1638 nv50_audio_enable(encoder, mode); 1639 break; 1640 default: 1641 BUG(); 1642 break; 1643 } 1644 1645 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1646 } 1647 1648 static const struct drm_encoder_helper_funcs 1649 nv50_sor_help = { 1650 .atomic_check = nv50_outp_atomic_check, 1651 .enable = nv50_sor_enable, 1652 .disable = nv50_sor_disable, 1653 }; 1654 1655 static void 1656 nv50_sor_destroy(struct drm_encoder *encoder) 1657 { 1658 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1659 nv50_mstm_del(&nv_encoder->dp.mstm); 1660 drm_encoder_cleanup(encoder); 1661 kfree(encoder); 1662 } 1663 1664 static const struct drm_encoder_funcs 1665 nv50_sor_func = { 1666 .destroy = nv50_sor_destroy, 1667 }; 1668 1669 static bool nv50_has_mst(struct nouveau_drm *drm) 1670 { 1671 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1672 u32 data; 1673 u8 ver, hdr, cnt, len; 1674 1675 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1676 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1677 } 1678 1679 static int 1680 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1681 { 1682 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1683 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1684 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1685 struct nouveau_encoder *nv_encoder; 1686 struct drm_encoder *encoder; 1687 struct nv50_disp *disp = nv50_disp(connector->dev); 1688 int type, ret; 1689 1690 switch (dcbe->type) { 1691 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1692 case DCB_OUTPUT_TMDS: 1693 case DCB_OUTPUT_DP: 1694 default: 1695 type = DRM_MODE_ENCODER_TMDS; 1696 break; 1697 } 1698 1699 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1700 if (!nv_encoder) 1701 return -ENOMEM; 1702 nv_encoder->dcb = dcbe; 1703 nv_encoder->update = nv50_sor_update; 1704 1705 encoder = to_drm_encoder(nv_encoder); 1706 encoder->possible_crtcs = dcbe->heads; 1707 encoder->possible_clones = 0; 1708 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1709 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1710 drm_encoder_helper_add(encoder, &nv50_sor_help); 1711 1712 drm_connector_attach_encoder(connector, encoder); 1713 1714 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1715 1716 if (dcbe->type == DCB_OUTPUT_DP) { 1717 struct nvkm_i2c_aux *aux = 1718 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1719 1720 if (aux) { 1721 if (disp->disp->object.oclass < GF110_DISP) { 1722 /* HW has no support for address-only 1723 * transactions, so we're required to 1724 * use custom I2C-over-AUX code. 1725 */ 1726 nv_encoder->i2c = &aux->i2c; 1727 } else { 1728 nv_encoder->i2c = &nv_connector->aux.ddc; 1729 } 1730 nv_encoder->aux = aux; 1731 } 1732 1733 if (nv_connector->type != DCB_CONNECTOR_eDP && 1734 nv50_has_mst(drm)) { 1735 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1736 16, nv_connector->base.base.id, 1737 &nv_encoder->dp.mstm); 1738 if (ret) 1739 return ret; 1740 } 1741 } else { 1742 struct nvkm_i2c_bus *bus = 1743 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1744 if (bus) 1745 nv_encoder->i2c = &bus->i2c; 1746 } 1747 1748 return 0; 1749 } 1750 1751 /****************************************************************************** 1752 * PIOR 1753 *****************************************************************************/ 1754 static int 1755 nv50_pior_atomic_check(struct drm_encoder *encoder, 1756 struct drm_crtc_state *crtc_state, 1757 struct drm_connector_state *conn_state) 1758 { 1759 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1760 if (ret) 1761 return ret; 1762 crtc_state->adjusted_mode.clock *= 2; 1763 return 0; 1764 } 1765 1766 static void 1767 nv50_pior_disable(struct drm_encoder *encoder) 1768 { 1769 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1770 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1771 if (nv_encoder->crtc) 1772 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); 1773 nv_encoder->crtc = NULL; 1774 nv50_outp_release(nv_encoder); 1775 } 1776 1777 static void 1778 nv50_pior_enable(struct drm_encoder *encoder) 1779 { 1780 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1781 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1782 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1783 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1784 u8 owner = 1 << nv_crtc->index; 1785 u8 proto; 1786 1787 nv50_outp_acquire(nv_encoder, false); 1788 1789 switch (asyh->or.bpc) { 1790 case 10: asyh->or.depth = 0x6; break; 1791 case 8: asyh->or.depth = 0x5; break; 1792 case 6: asyh->or.depth = 0x2; break; 1793 default: asyh->or.depth = 0x0; break; 1794 } 1795 1796 switch (nv_encoder->dcb->type) { 1797 case DCB_OUTPUT_TMDS: 1798 case DCB_OUTPUT_DP: 1799 proto = 0x0; 1800 break; 1801 default: 1802 BUG(); 1803 break; 1804 } 1805 1806 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); 1807 nv_encoder->crtc = encoder->crtc; 1808 } 1809 1810 static const struct drm_encoder_helper_funcs 1811 nv50_pior_help = { 1812 .atomic_check = nv50_pior_atomic_check, 1813 .enable = nv50_pior_enable, 1814 .disable = nv50_pior_disable, 1815 }; 1816 1817 static void 1818 nv50_pior_destroy(struct drm_encoder *encoder) 1819 { 1820 drm_encoder_cleanup(encoder); 1821 kfree(encoder); 1822 } 1823 1824 static const struct drm_encoder_funcs 1825 nv50_pior_func = { 1826 .destroy = nv50_pior_destroy, 1827 }; 1828 1829 static int 1830 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1831 { 1832 struct drm_device *dev = connector->dev; 1833 struct nouveau_drm *drm = nouveau_drm(dev); 1834 struct nv50_disp *disp = nv50_disp(dev); 1835 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1836 struct nvkm_i2c_bus *bus = NULL; 1837 struct nvkm_i2c_aux *aux = NULL; 1838 struct i2c_adapter *ddc; 1839 struct nouveau_encoder *nv_encoder; 1840 struct drm_encoder *encoder; 1841 int type; 1842 1843 switch (dcbe->type) { 1844 case DCB_OUTPUT_TMDS: 1845 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1846 ddc = bus ? &bus->i2c : NULL; 1847 type = DRM_MODE_ENCODER_TMDS; 1848 break; 1849 case DCB_OUTPUT_DP: 1850 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1851 ddc = aux ? &aux->i2c : NULL; 1852 type = DRM_MODE_ENCODER_TMDS; 1853 break; 1854 default: 1855 return -ENODEV; 1856 } 1857 1858 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1859 if (!nv_encoder) 1860 return -ENOMEM; 1861 nv_encoder->dcb = dcbe; 1862 nv_encoder->i2c = ddc; 1863 nv_encoder->aux = aux; 1864 1865 encoder = to_drm_encoder(nv_encoder); 1866 encoder->possible_crtcs = dcbe->heads; 1867 encoder->possible_clones = 0; 1868 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1869 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1870 drm_encoder_helper_add(encoder, &nv50_pior_help); 1871 1872 drm_connector_attach_encoder(connector, encoder); 1873 1874 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1875 1876 return 0; 1877 } 1878 1879 /****************************************************************************** 1880 * Atomic 1881 *****************************************************************************/ 1882 1883 static void 1884 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1885 { 1886 struct nouveau_drm *drm = nouveau_drm(state->dev); 1887 struct nv50_disp *disp = nv50_disp(drm->dev); 1888 struct nv50_core *core = disp->core; 1889 struct nv50_mstm *mstm; 1890 struct drm_encoder *encoder; 1891 1892 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1893 1894 drm_for_each_encoder(encoder, drm->dev) { 1895 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1896 mstm = nouveau_encoder(encoder)->dp.mstm; 1897 if (mstm && mstm->modified) 1898 nv50_mstm_prepare(mstm); 1899 } 1900 } 1901 1902 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1903 core->func->update(core, interlock, true); 1904 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1905 disp->core->chan.base.device)) 1906 NV_ERROR(drm, "core notifier timeout\n"); 1907 1908 drm_for_each_encoder(encoder, drm->dev) { 1909 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1910 mstm = nouveau_encoder(encoder)->dp.mstm; 1911 if (mstm && mstm->modified) 1912 nv50_mstm_cleanup(mstm); 1913 } 1914 } 1915 } 1916 1917 static void 1918 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 1919 { 1920 struct drm_plane_state *new_plane_state; 1921 struct drm_plane *plane; 1922 int i; 1923 1924 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1925 struct nv50_wndw *wndw = nv50_wndw(plane); 1926 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 1927 if (wndw->func->update) 1928 wndw->func->update(wndw, interlock); 1929 } 1930 } 1931 } 1932 1933 static void 1934 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1935 { 1936 struct drm_device *dev = state->dev; 1937 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1938 struct drm_crtc *crtc; 1939 struct drm_plane_state *new_plane_state; 1940 struct drm_plane *plane; 1941 struct nouveau_drm *drm = nouveau_drm(dev); 1942 struct nv50_disp *disp = nv50_disp(dev); 1943 struct nv50_atom *atom = nv50_atom(state); 1944 struct nv50_core *core = disp->core; 1945 struct nv50_outp_atom *outp, *outt; 1946 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 1947 int i; 1948 1949 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 1950 drm_atomic_helper_wait_for_fences(dev, state, false); 1951 drm_atomic_helper_wait_for_dependencies(state); 1952 drm_atomic_helper_update_legacy_modeset_state(dev, state); 1953 1954 if (atom->lock_core) 1955 mutex_lock(&disp->mutex); 1956 1957 /* Disable head(s). */ 1958 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1959 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 1960 struct nv50_head *head = nv50_head(crtc); 1961 1962 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 1963 asyh->clr.mask, asyh->set.mask); 1964 1965 if (old_crtc_state->active && !new_crtc_state->active) { 1966 pm_runtime_put_noidle(dev->dev); 1967 drm_crtc_vblank_off(crtc); 1968 } 1969 1970 if (asyh->clr.mask) { 1971 nv50_head_flush_clr(head, asyh, atom->flush_disable); 1972 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 1973 } 1974 } 1975 1976 /* Disable plane(s). */ 1977 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1978 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 1979 struct nv50_wndw *wndw = nv50_wndw(plane); 1980 1981 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 1982 asyw->clr.mask, asyw->set.mask); 1983 if (!asyw->clr.mask) 1984 continue; 1985 1986 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 1987 } 1988 1989 /* Disable output path(s). */ 1990 list_for_each_entry(outp, &atom->outp, head) { 1991 const struct drm_encoder_helper_funcs *help; 1992 struct drm_encoder *encoder; 1993 1994 encoder = outp->encoder; 1995 help = encoder->helper_private; 1996 1997 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 1998 outp->clr.mask, outp->set.mask); 1999 2000 if (outp->clr.mask) { 2001 help->disable(encoder); 2002 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2003 if (outp->flush_disable) { 2004 nv50_disp_atomic_commit_wndw(state, interlock); 2005 nv50_disp_atomic_commit_core(state, interlock); 2006 memset(interlock, 0x00, sizeof(interlock)); 2007 } 2008 } 2009 } 2010 2011 /* Flush disable. */ 2012 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2013 if (atom->flush_disable) { 2014 nv50_disp_atomic_commit_wndw(state, interlock); 2015 nv50_disp_atomic_commit_core(state, interlock); 2016 memset(interlock, 0x00, sizeof(interlock)); 2017 } 2018 } 2019 2020 /* Update output path(s). */ 2021 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2022 const struct drm_encoder_helper_funcs *help; 2023 struct drm_encoder *encoder; 2024 2025 encoder = outp->encoder; 2026 help = encoder->helper_private; 2027 2028 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2029 outp->set.mask, outp->clr.mask); 2030 2031 if (outp->set.mask) { 2032 help->enable(encoder); 2033 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2034 } 2035 2036 list_del(&outp->head); 2037 kfree(outp); 2038 } 2039 2040 /* Update head(s). */ 2041 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2042 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2043 struct nv50_head *head = nv50_head(crtc); 2044 2045 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2046 asyh->set.mask, asyh->clr.mask); 2047 2048 if (asyh->set.mask) { 2049 nv50_head_flush_set(head, asyh); 2050 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2051 } 2052 2053 if (new_crtc_state->active) { 2054 if (!old_crtc_state->active) { 2055 drm_crtc_vblank_on(crtc); 2056 pm_runtime_get_noresume(dev->dev); 2057 } 2058 if (new_crtc_state->event) 2059 drm_crtc_vblank_get(crtc); 2060 } 2061 } 2062 2063 /* Update window->head assignment. 2064 * 2065 * This has to happen in an update that's not interlocked with 2066 * any window channels to avoid hitting HW error checks. 2067 * 2068 *TODO: Proper handling of window ownership (Turing apparently 2069 * supports non-fixed mappings). 2070 */ 2071 if (core->assign_windows) { 2072 core->func->wndw.owner(core); 2073 core->func->update(core, interlock, false); 2074 core->assign_windows = false; 2075 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2076 } 2077 2078 /* Update plane(s). */ 2079 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2080 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2081 struct nv50_wndw *wndw = nv50_wndw(plane); 2082 2083 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2084 asyw->set.mask, asyw->clr.mask); 2085 if ( !asyw->set.mask && 2086 (!asyw->clr.mask || atom->flush_disable)) 2087 continue; 2088 2089 nv50_wndw_flush_set(wndw, interlock, asyw); 2090 } 2091 2092 /* Flush update. */ 2093 nv50_disp_atomic_commit_wndw(state, interlock); 2094 2095 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2096 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2097 interlock[NV50_DISP_INTERLOCK_OVLY] || 2098 interlock[NV50_DISP_INTERLOCK_WNDW] || 2099 !atom->state.legacy_cursor_update) 2100 nv50_disp_atomic_commit_core(state, interlock); 2101 else 2102 disp->core->func->update(disp->core, interlock, false); 2103 } 2104 2105 if (atom->lock_core) 2106 mutex_unlock(&disp->mutex); 2107 2108 /* Wait for HW to signal completion. */ 2109 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2110 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2111 struct nv50_wndw *wndw = nv50_wndw(plane); 2112 int ret = nv50_wndw_wait_armed(wndw, asyw); 2113 if (ret) 2114 NV_ERROR(drm, "%s: timeout\n", plane->name); 2115 } 2116 2117 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2118 if (new_crtc_state->event) { 2119 unsigned long flags; 2120 /* Get correct count/ts if racing with vblank irq */ 2121 if (new_crtc_state->active) 2122 drm_crtc_accurate_vblank_count(crtc); 2123 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2124 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2125 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2126 2127 new_crtc_state->event = NULL; 2128 if (new_crtc_state->active) 2129 drm_crtc_vblank_put(crtc); 2130 } 2131 } 2132 2133 drm_atomic_helper_commit_hw_done(state); 2134 drm_atomic_helper_cleanup_planes(dev, state); 2135 drm_atomic_helper_commit_cleanup_done(state); 2136 drm_atomic_state_put(state); 2137 2138 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2139 pm_runtime_mark_last_busy(dev->dev); 2140 pm_runtime_put_autosuspend(dev->dev); 2141 } 2142 2143 static void 2144 nv50_disp_atomic_commit_work(struct work_struct *work) 2145 { 2146 struct drm_atomic_state *state = 2147 container_of(work, typeof(*state), commit_work); 2148 nv50_disp_atomic_commit_tail(state); 2149 } 2150 2151 static int 2152 nv50_disp_atomic_commit(struct drm_device *dev, 2153 struct drm_atomic_state *state, bool nonblock) 2154 { 2155 struct drm_plane_state *new_plane_state; 2156 struct drm_plane *plane; 2157 int ret, i; 2158 2159 ret = pm_runtime_get_sync(dev->dev); 2160 if (ret < 0 && ret != -EACCES) 2161 return ret; 2162 2163 ret = drm_atomic_helper_setup_commit(state, nonblock); 2164 if (ret) 2165 goto done; 2166 2167 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2168 2169 ret = drm_atomic_helper_prepare_planes(dev, state); 2170 if (ret) 2171 goto done; 2172 2173 if (!nonblock) { 2174 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2175 if (ret) 2176 goto err_cleanup; 2177 } 2178 2179 ret = drm_atomic_helper_swap_state(state, true); 2180 if (ret) 2181 goto err_cleanup; 2182 2183 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2184 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2185 struct nv50_wndw *wndw = nv50_wndw(plane); 2186 2187 if (asyw->set.image) 2188 nv50_wndw_ntfy_enable(wndw, asyw); 2189 } 2190 2191 drm_atomic_state_get(state); 2192 2193 /* 2194 * Grab another RPM ref for the commit tail, which will release the 2195 * ref when it's finished 2196 */ 2197 pm_runtime_get_noresume(dev->dev); 2198 2199 if (nonblock) 2200 queue_work(system_unbound_wq, &state->commit_work); 2201 else 2202 nv50_disp_atomic_commit_tail(state); 2203 2204 err_cleanup: 2205 if (ret) 2206 drm_atomic_helper_cleanup_planes(dev, state); 2207 done: 2208 pm_runtime_put_autosuspend(dev->dev); 2209 return ret; 2210 } 2211 2212 static struct nv50_outp_atom * 2213 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2214 { 2215 struct nv50_outp_atom *outp; 2216 2217 list_for_each_entry(outp, &atom->outp, head) { 2218 if (outp->encoder == encoder) 2219 return outp; 2220 } 2221 2222 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2223 if (!outp) 2224 return ERR_PTR(-ENOMEM); 2225 2226 list_add(&outp->head, &atom->outp); 2227 outp->encoder = encoder; 2228 return outp; 2229 } 2230 2231 static int 2232 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2233 struct drm_connector_state *old_connector_state) 2234 { 2235 struct drm_encoder *encoder = old_connector_state->best_encoder; 2236 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2237 struct drm_crtc *crtc; 2238 struct nv50_outp_atom *outp; 2239 2240 if (!(crtc = old_connector_state->crtc)) 2241 return 0; 2242 2243 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2244 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2245 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2246 outp = nv50_disp_outp_atomic_add(atom, encoder); 2247 if (IS_ERR(outp)) 2248 return PTR_ERR(outp); 2249 2250 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2251 outp->flush_disable = true; 2252 atom->flush_disable = true; 2253 } 2254 outp->clr.ctrl = true; 2255 atom->lock_core = true; 2256 } 2257 2258 return 0; 2259 } 2260 2261 static int 2262 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2263 struct drm_connector_state *connector_state) 2264 { 2265 struct drm_encoder *encoder = connector_state->best_encoder; 2266 struct drm_crtc_state *new_crtc_state; 2267 struct drm_crtc *crtc; 2268 struct nv50_outp_atom *outp; 2269 2270 if (!(crtc = connector_state->crtc)) 2271 return 0; 2272 2273 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2274 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2275 outp = nv50_disp_outp_atomic_add(atom, encoder); 2276 if (IS_ERR(outp)) 2277 return PTR_ERR(outp); 2278 2279 outp->set.ctrl = true; 2280 atom->lock_core = true; 2281 } 2282 2283 return 0; 2284 } 2285 2286 static int 2287 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2288 { 2289 struct nv50_atom *atom = nv50_atom(state); 2290 struct drm_connector_state *old_connector_state, *new_connector_state; 2291 struct drm_connector *connector; 2292 struct drm_crtc_state *new_crtc_state; 2293 struct drm_crtc *crtc; 2294 int ret, i; 2295 2296 /* We need to handle colour management on a per-plane basis. */ 2297 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2298 if (new_crtc_state->color_mgmt_changed) { 2299 ret = drm_atomic_add_affected_planes(state, crtc); 2300 if (ret) 2301 return ret; 2302 } 2303 } 2304 2305 ret = drm_atomic_helper_check(dev, state); 2306 if (ret) 2307 return ret; 2308 2309 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2310 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2311 if (ret) 2312 return ret; 2313 2314 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2315 if (ret) 2316 return ret; 2317 } 2318 2319 ret = drm_dp_mst_atomic_check(state); 2320 if (ret) 2321 return ret; 2322 2323 return 0; 2324 } 2325 2326 static void 2327 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2328 { 2329 struct nv50_atom *atom = nv50_atom(state); 2330 struct nv50_outp_atom *outp, *outt; 2331 2332 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2333 list_del(&outp->head); 2334 kfree(outp); 2335 } 2336 2337 drm_atomic_state_default_clear(state); 2338 } 2339 2340 static void 2341 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2342 { 2343 struct nv50_atom *atom = nv50_atom(state); 2344 drm_atomic_state_default_release(&atom->state); 2345 kfree(atom); 2346 } 2347 2348 static struct drm_atomic_state * 2349 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2350 { 2351 struct nv50_atom *atom; 2352 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2353 drm_atomic_state_init(dev, &atom->state) < 0) { 2354 kfree(atom); 2355 return NULL; 2356 } 2357 INIT_LIST_HEAD(&atom->outp); 2358 return &atom->state; 2359 } 2360 2361 static const struct drm_mode_config_funcs 2362 nv50_disp_func = { 2363 .fb_create = nouveau_user_framebuffer_create, 2364 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2365 .atomic_check = nv50_disp_atomic_check, 2366 .atomic_commit = nv50_disp_atomic_commit, 2367 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2368 .atomic_state_clear = nv50_disp_atomic_state_clear, 2369 .atomic_state_free = nv50_disp_atomic_state_free, 2370 }; 2371 2372 /****************************************************************************** 2373 * Init 2374 *****************************************************************************/ 2375 2376 static void 2377 nv50_display_fini(struct drm_device *dev, bool suspend) 2378 { 2379 struct nouveau_encoder *nv_encoder; 2380 struct drm_encoder *encoder; 2381 struct drm_plane *plane; 2382 2383 drm_for_each_plane(plane, dev) { 2384 struct nv50_wndw *wndw = nv50_wndw(plane); 2385 if (plane->funcs != &nv50_wndw) 2386 continue; 2387 nv50_wndw_fini(wndw); 2388 } 2389 2390 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2391 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2392 nv_encoder = nouveau_encoder(encoder); 2393 nv50_mstm_fini(nv_encoder->dp.mstm); 2394 } 2395 } 2396 } 2397 2398 static int 2399 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2400 { 2401 struct nv50_core *core = nv50_disp(dev)->core; 2402 struct drm_encoder *encoder; 2403 struct drm_plane *plane; 2404 2405 if (resume || runtime) 2406 core->func->init(core); 2407 2408 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2409 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2410 struct nouveau_encoder *nv_encoder = 2411 nouveau_encoder(encoder); 2412 nv50_mstm_init(nv_encoder->dp.mstm, runtime); 2413 } 2414 } 2415 2416 drm_for_each_plane(plane, dev) { 2417 struct nv50_wndw *wndw = nv50_wndw(plane); 2418 if (plane->funcs != &nv50_wndw) 2419 continue; 2420 nv50_wndw_init(wndw); 2421 } 2422 2423 return 0; 2424 } 2425 2426 static void 2427 nv50_display_destroy(struct drm_device *dev) 2428 { 2429 struct nv50_disp *disp = nv50_disp(dev); 2430 2431 nv50_audio_component_fini(nouveau_drm(dev)); 2432 2433 nvif_object_unmap(&disp->caps); 2434 nvif_object_fini(&disp->caps); 2435 nv50_core_del(&disp->core); 2436 2437 nouveau_bo_unmap(disp->sync); 2438 if (disp->sync) 2439 nouveau_bo_unpin(disp->sync); 2440 nouveau_bo_ref(NULL, &disp->sync); 2441 2442 nouveau_display(dev)->priv = NULL; 2443 kfree(disp); 2444 } 2445 2446 int 2447 nv50_display_create(struct drm_device *dev) 2448 { 2449 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2450 struct nouveau_drm *drm = nouveau_drm(dev); 2451 struct dcb_table *dcb = &drm->vbios.dcb; 2452 struct drm_connector *connector, *tmp; 2453 struct nv50_disp *disp; 2454 struct dcb_output *dcbe; 2455 int crtcs, ret, i; 2456 bool has_mst = nv50_has_mst(drm); 2457 2458 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2459 if (!disp) 2460 return -ENOMEM; 2461 2462 mutex_init(&disp->mutex); 2463 2464 nouveau_display(dev)->priv = disp; 2465 nouveau_display(dev)->dtor = nv50_display_destroy; 2466 nouveau_display(dev)->init = nv50_display_init; 2467 nouveau_display(dev)->fini = nv50_display_fini; 2468 disp->disp = &nouveau_display(dev)->disp; 2469 dev->mode_config.funcs = &nv50_disp_func; 2470 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2471 dev->mode_config.normalize_zpos = true; 2472 2473 /* small shared memory area we use for notifiers and semaphores */ 2474 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2475 0, 0x0000, NULL, NULL, &disp->sync); 2476 if (!ret) { 2477 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2478 if (!ret) { 2479 ret = nouveau_bo_map(disp->sync); 2480 if (ret) 2481 nouveau_bo_unpin(disp->sync); 2482 } 2483 if (ret) 2484 nouveau_bo_ref(NULL, &disp->sync); 2485 } 2486 2487 if (ret) 2488 goto out; 2489 2490 /* allocate master evo channel */ 2491 ret = nv50_core_new(drm, &disp->core); 2492 if (ret) 2493 goto out; 2494 2495 disp->core->func->init(disp->core); 2496 if (disp->core->func->caps_init) { 2497 ret = disp->core->func->caps_init(drm, disp); 2498 if (ret) 2499 goto out; 2500 } 2501 2502 /* Assign the correct format modifiers */ 2503 if (disp->disp->object.oclass >= TU102_DISP) 2504 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2505 else 2506 if (disp->disp->object.oclass >= GF110_DISP) 2507 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2508 else 2509 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2510 2511 /* create crtc objects to represent the hw heads */ 2512 if (disp->disp->object.oclass >= GV100_DISP) 2513 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2514 else 2515 if (disp->disp->object.oclass >= GF110_DISP) 2516 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2517 else 2518 crtcs = 0x3; 2519 2520 for (i = 0; i < fls(crtcs); i++) { 2521 struct nv50_head *head; 2522 2523 if (!(crtcs & (1 << i))) 2524 continue; 2525 2526 head = nv50_head_create(dev, i); 2527 if (IS_ERR(head)) { 2528 ret = PTR_ERR(head); 2529 goto out; 2530 } 2531 2532 if (has_mst) { 2533 head->msto = nv50_msto_new(dev, head, i); 2534 if (IS_ERR(head->msto)) { 2535 ret = PTR_ERR(head->msto); 2536 head->msto = NULL; 2537 goto out; 2538 } 2539 2540 /* 2541 * FIXME: This is a hack to workaround the following 2542 * issues: 2543 * 2544 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2545 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2546 * 2547 * Once these issues are closed, this should be 2548 * removed 2549 */ 2550 head->msto->encoder.possible_crtcs = crtcs; 2551 } 2552 } 2553 2554 /* create encoder/connector objects based on VBIOS DCB table */ 2555 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2556 connector = nouveau_connector_create(dev, dcbe); 2557 if (IS_ERR(connector)) 2558 continue; 2559 2560 if (dcbe->location == DCB_LOC_ON_CHIP) { 2561 switch (dcbe->type) { 2562 case DCB_OUTPUT_TMDS: 2563 case DCB_OUTPUT_LVDS: 2564 case DCB_OUTPUT_DP: 2565 ret = nv50_sor_create(connector, dcbe); 2566 break; 2567 case DCB_OUTPUT_ANALOG: 2568 ret = nv50_dac_create(connector, dcbe); 2569 break; 2570 default: 2571 ret = -ENODEV; 2572 break; 2573 } 2574 } else { 2575 ret = nv50_pior_create(connector, dcbe); 2576 } 2577 2578 if (ret) { 2579 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2580 dcbe->location, dcbe->type, 2581 ffs(dcbe->or) - 1, ret); 2582 ret = 0; 2583 } 2584 } 2585 2586 /* cull any connectors we created that don't have an encoder */ 2587 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2588 if (connector->possible_encoders) 2589 continue; 2590 2591 NV_WARN(drm, "%s has no encoders, removing\n", 2592 connector->name); 2593 connector->funcs->destroy(connector); 2594 } 2595 2596 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2597 dev->vblank_disable_immediate = true; 2598 2599 nv50_audio_component_init(drm); 2600 2601 out: 2602 if (ret) 2603 nv50_display_destroy(dev); 2604 return ret; 2605 } 2606 2607 /****************************************************************************** 2608 * Format modifiers 2609 *****************************************************************************/ 2610 2611 /**************************************************************** 2612 * Log2(block height) ----------------------------+ * 2613 * Page Kind ----------------------------------+ | * 2614 * Gob Height/Page Kind Generation ------+ | | * 2615 * Sector layout -------+ | | | * 2616 * Compression ------+ | | | | */ 2617 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2618 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2619 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2620 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2621 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2622 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2623 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2624 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2625 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2626 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2627 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2628 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2629 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2630 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2631 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2632 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2633 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2634 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2635 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2636 DRM_FORMAT_MOD_LINEAR, 2637 DRM_FORMAT_MOD_INVALID 2638 }; 2639 2640 /**************************************************************** 2641 * Log2(block height) ----------------------------+ * 2642 * Page Kind ----------------------------------+ | * 2643 * Gob Height/Page Kind Generation ------+ | | * 2644 * Sector layout -------+ | | | * 2645 * Compression ------+ | | | | */ 2646 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2647 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2648 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2649 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2650 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2651 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2652 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2653 DRM_FORMAT_MOD_LINEAR, 2654 DRM_FORMAT_MOD_INVALID 2655 }; 2656