1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 #include <linux/iopoll.h> 35 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_dp_helper.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_fb_helper.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_scdc_helper.h> 44 #include <drm/drm_vblank.h> 45 46 #include <nvif/push507c.h> 47 48 #include <nvif/class.h> 49 #include <nvif/cl0002.h> 50 #include <nvif/cl5070.h> 51 #include <nvif/cl507d.h> 52 #include <nvif/event.h> 53 #include <nvif/timer.h> 54 55 #include <nvhw/class/cl507c.h> 56 #include <nvhw/class/cl507d.h> 57 #include <nvhw/class/cl837d.h> 58 #include <nvhw/class/cl887d.h> 59 #include <nvhw/class/cl907d.h> 60 #include <nvhw/class/cl917d.h> 61 62 #include "nouveau_drv.h" 63 #include "nouveau_dma.h" 64 #include "nouveau_gem.h" 65 #include "nouveau_connector.h" 66 #include "nouveau_encoder.h" 67 #include "nouveau_fence.h" 68 #include "nouveau_fbcon.h" 69 70 #include <subdev/bios/dp.h> 71 72 /****************************************************************************** 73 * EVO channel 74 *****************************************************************************/ 75 76 static int 77 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 78 const s32 *oclass, u8 head, void *data, u32 size, 79 struct nv50_chan *chan) 80 { 81 struct nvif_sclass *sclass; 82 int ret, i, n; 83 84 chan->device = device; 85 86 ret = n = nvif_object_sclass_get(disp, &sclass); 87 if (ret < 0) 88 return ret; 89 90 while (oclass[0]) { 91 for (i = 0; i < n; i++) { 92 if (sclass[i].oclass == oclass[0]) { 93 ret = nvif_object_ctor(disp, "kmsChan", 0, 94 oclass[0], data, size, 95 &chan->user); 96 if (ret == 0) 97 nvif_object_map(&chan->user, NULL, 0); 98 nvif_object_sclass_put(&sclass); 99 return ret; 100 } 101 } 102 oclass++; 103 } 104 105 nvif_object_sclass_put(&sclass); 106 return -ENOSYS; 107 } 108 109 static void 110 nv50_chan_destroy(struct nv50_chan *chan) 111 { 112 nvif_object_dtor(&chan->user); 113 } 114 115 /****************************************************************************** 116 * DMA EVO channel 117 *****************************************************************************/ 118 119 void 120 nv50_dmac_destroy(struct nv50_dmac *dmac) 121 { 122 nvif_object_dtor(&dmac->vram); 123 nvif_object_dtor(&dmac->sync); 124 125 nv50_chan_destroy(&dmac->base); 126 127 nvif_mem_dtor(&dmac->_push.mem); 128 } 129 130 static void 131 nv50_dmac_kick(struct nvif_push *push) 132 { 133 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 134 135 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 136 if (dmac->put != dmac->cur) { 137 /* Push buffer fetches are not coherent with BAR1, we need to ensure 138 * writes have been flushed right through to VRAM before writing PUT. 139 */ 140 if (dmac->push->mem.type & NVIF_MEM_VRAM) { 141 struct nvif_device *device = dmac->base.device; 142 nvif_wr32(&device->object, 0x070000, 0x00000001); 143 nvif_msec(device, 2000, 144 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 145 break; 146 ); 147 } 148 149 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); 150 dmac->put = dmac->cur; 151 } 152 153 push->bgn = push->cur; 154 } 155 156 static int 157 nv50_dmac_free(struct nv50_dmac *dmac) 158 { 159 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 160 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ 161 return get - dmac->cur - 5; 162 return dmac->max - dmac->cur; 163 } 164 165 static int 166 nv50_dmac_wind(struct nv50_dmac *dmac) 167 { 168 /* Wait for GET to depart from the beginning of the push buffer to 169 * prevent writing PUT == GET, which would be ignored by HW. 170 */ 171 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 172 if (get == 0) { 173 /* Corner-case, HW idle, but non-committed work pending. */ 174 if (dmac->put == 0) 175 nv50_dmac_kick(dmac->push); 176 177 if (nvif_msec(dmac->base.device, 2000, 178 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) 179 break; 180 ) < 0) 181 return -ETIMEDOUT; 182 } 183 184 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); 185 dmac->cur = 0; 186 return 0; 187 } 188 189 static int 190 nv50_dmac_wait(struct nvif_push *push, u32 size) 191 { 192 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 193 int free; 194 195 if (WARN_ON(size > dmac->max)) 196 return -EINVAL; 197 198 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 199 if (dmac->cur + size >= dmac->max) { 200 int ret = nv50_dmac_wind(dmac); 201 if (ret) 202 return ret; 203 204 push->cur = dmac->_push.mem.object.map.ptr; 205 push->cur = push->cur + dmac->cur; 206 nv50_dmac_kick(push); 207 } 208 209 if (nvif_msec(dmac->base.device, 2000, 210 if ((free = nv50_dmac_free(dmac)) >= size) 211 break; 212 ) < 0) { 213 WARN_ON(1); 214 return -ETIMEDOUT; 215 } 216 217 push->bgn = dmac->_push.mem.object.map.ptr; 218 push->bgn = push->bgn + dmac->cur; 219 push->cur = push->bgn; 220 push->end = push->cur + free; 221 return 0; 222 } 223 224 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)"); 225 static int nv50_dmac_vram_pushbuf = -1; 226 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400); 227 228 int 229 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 230 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf, 231 struct nv50_dmac *dmac) 232 { 233 struct nouveau_cli *cli = (void *)device->object.client; 234 struct nv50_disp_core_channel_dma_v0 *args = data; 235 u8 type = NVIF_MEM_COHERENT; 236 int ret; 237 238 mutex_init(&dmac->lock); 239 240 /* Pascal added support for 47-bit physical addresses, but some 241 * parts of EVO still only accept 40-bit PAs. 242 * 243 * To avoid issues on systems with large amounts of RAM, and on 244 * systems where an IOMMU maps pages at a high address, we need 245 * to allocate push buffers in VRAM instead. 246 * 247 * This appears to match NVIDIA's behaviour on Pascal. 248 */ 249 if ((nv50_dmac_vram_pushbuf > 0) || 250 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL)) 251 type |= NVIF_MEM_VRAM; 252 253 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, 254 &dmac->_push.mem); 255 if (ret) 256 return ret; 257 258 dmac->ptr = dmac->_push.mem.object.map.ptr; 259 dmac->_push.wait = nv50_dmac_wait; 260 dmac->_push.kick = nv50_dmac_kick; 261 dmac->push = &dmac->_push; 262 dmac->push->bgn = dmac->_push.mem.object.map.ptr; 263 dmac->push->cur = dmac->push->bgn; 264 dmac->push->end = dmac->push->bgn; 265 dmac->max = 0x1000/4 - 1; 266 267 /* EVO channels are affected by a HW bug where the last 12 DWORDs 268 * of the push buffer aren't able to be used safely. 269 */ 270 if (disp->oclass < GV100_DISP) 271 dmac->max -= 12; 272 273 args->pushbuf = nvif_handle(&dmac->_push.mem.object); 274 275 ret = nv50_chan_create(device, disp, oclass, head, data, size, 276 &dmac->base); 277 if (ret) 278 return ret; 279 280 if (syncbuf < 0) 281 return 0; 282 283 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, 284 NV_DMA_IN_MEMORY, 285 &(struct nv_dma_v0) { 286 .target = NV_DMA_V0_TARGET_VRAM, 287 .access = NV_DMA_V0_ACCESS_RDWR, 288 .start = syncbuf + 0x0000, 289 .limit = syncbuf + 0x0fff, 290 }, sizeof(struct nv_dma_v0), 291 &dmac->sync); 292 if (ret) 293 return ret; 294 295 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, 296 NV_DMA_IN_MEMORY, 297 &(struct nv_dma_v0) { 298 .target = NV_DMA_V0_TARGET_VRAM, 299 .access = NV_DMA_V0_ACCESS_RDWR, 300 .start = 0, 301 .limit = device->info.ram_user - 1, 302 }, sizeof(struct nv_dma_v0), 303 &dmac->vram); 304 if (ret) 305 return ret; 306 307 return ret; 308 } 309 310 /****************************************************************************** 311 * Output path helpers 312 *****************************************************************************/ 313 static void 314 nv50_outp_dump_caps(struct nouveau_drm *drm, 315 struct nouveau_encoder *outp) 316 { 317 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n", 318 outp->base.base.name, outp->caps.dp_interlace); 319 } 320 321 static void 322 nv50_outp_release(struct nouveau_encoder *nv_encoder) 323 { 324 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 325 struct { 326 struct nv50_disp_mthd_v1 base; 327 } args = { 328 .base.version = 1, 329 .base.method = NV50_DISP_MTHD_V1_RELEASE, 330 .base.hasht = nv_encoder->dcb->hasht, 331 .base.hashm = nv_encoder->dcb->hashm, 332 }; 333 334 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 335 nv_encoder->or = -1; 336 nv_encoder->link = 0; 337 } 338 339 static int 340 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda) 341 { 342 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 343 struct nv50_disp *disp = nv50_disp(drm->dev); 344 struct { 345 struct nv50_disp_mthd_v1 base; 346 struct nv50_disp_acquire_v0 info; 347 } args = { 348 .base.version = 1, 349 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 350 .base.hasht = nv_encoder->dcb->hasht, 351 .base.hashm = nv_encoder->dcb->hashm, 352 .info.hda = hda, 353 }; 354 int ret; 355 356 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 357 if (ret) { 358 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 359 return ret; 360 } 361 362 nv_encoder->or = args.info.or; 363 nv_encoder->link = args.info.link; 364 return 0; 365 } 366 367 static int 368 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 369 struct drm_crtc_state *crtc_state, 370 struct drm_connector_state *conn_state, 371 struct drm_display_mode *native_mode) 372 { 373 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 374 struct drm_display_mode *mode = &crtc_state->mode; 375 struct drm_connector *connector = conn_state->connector; 376 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 377 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 378 379 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 380 asyc->scaler.full = false; 381 if (!native_mode) 382 return 0; 383 384 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 385 switch (connector->connector_type) { 386 case DRM_MODE_CONNECTOR_LVDS: 387 case DRM_MODE_CONNECTOR_eDP: 388 /* Don't force scaler for EDID modes with 389 * same size as the native one (e.g. different 390 * refresh rate) 391 */ 392 if (mode->hdisplay == native_mode->hdisplay && 393 mode->vdisplay == native_mode->vdisplay && 394 mode->type & DRM_MODE_TYPE_DRIVER) 395 break; 396 mode = native_mode; 397 asyc->scaler.full = true; 398 break; 399 default: 400 break; 401 } 402 } else { 403 mode = native_mode; 404 } 405 406 if (!drm_mode_equal(adjusted_mode, mode)) { 407 drm_mode_copy(adjusted_mode, mode); 408 crtc_state->mode_changed = true; 409 } 410 411 return 0; 412 } 413 414 static int 415 nv50_outp_atomic_check(struct drm_encoder *encoder, 416 struct drm_crtc_state *crtc_state, 417 struct drm_connector_state *conn_state) 418 { 419 struct drm_connector *connector = conn_state->connector; 420 struct nouveau_connector *nv_connector = nouveau_connector(connector); 421 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 422 int ret; 423 424 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 425 nv_connector->native_mode); 426 if (ret) 427 return ret; 428 429 if (crtc_state->mode_changed || crtc_state->connectors_changed) 430 asyh->or.bpc = connector->display_info.bpc; 431 432 return 0; 433 } 434 435 struct nouveau_connector * 436 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 437 { 438 struct drm_connector *connector; 439 struct drm_connector_state *connector_state; 440 struct drm_encoder *encoder = to_drm_encoder(outp); 441 int i; 442 443 for_each_new_connector_in_state(state, connector, connector_state, i) { 444 if (connector_state->best_encoder == encoder) 445 return nouveau_connector(connector); 446 } 447 448 return NULL; 449 } 450 451 struct nouveau_connector * 452 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 453 { 454 struct drm_connector *connector; 455 struct drm_connector_state *connector_state; 456 struct drm_encoder *encoder = to_drm_encoder(outp); 457 int i; 458 459 for_each_old_connector_in_state(state, connector, connector_state, i) { 460 if (connector_state->best_encoder == encoder) 461 return nouveau_connector(connector); 462 } 463 464 return NULL; 465 } 466 467 static struct nouveau_crtc * 468 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp) 469 { 470 struct drm_crtc *crtc; 471 struct drm_crtc_state *crtc_state; 472 const u32 mask = drm_encoder_mask(&outp->base.base); 473 int i; 474 475 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 476 if (crtc_state->encoder_mask & mask) 477 return nouveau_crtc(crtc); 478 } 479 480 return NULL; 481 } 482 483 /****************************************************************************** 484 * DAC 485 *****************************************************************************/ 486 static void 487 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 488 { 489 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 490 struct nv50_core *core = nv50_disp(encoder->dev)->core; 491 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); 492 493 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL); 494 nv_encoder->crtc = NULL; 495 nv50_outp_release(nv_encoder); 496 } 497 498 static void 499 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 500 { 501 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 502 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 503 struct nv50_head_atom *asyh = 504 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 505 struct nv50_core *core = nv50_disp(encoder->dev)->core; 506 u32 ctrl = 0; 507 508 switch (nv_crtc->index) { 509 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; 510 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; 511 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; 512 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; 513 default: 514 WARN_ON(1); 515 break; 516 } 517 518 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); 519 520 nv50_outp_acquire(nv_encoder, false); 521 522 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh); 523 asyh->or.depth = 0; 524 525 nv_encoder->crtc = &nv_crtc->base; 526 } 527 528 static enum drm_connector_status 529 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 530 { 531 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 532 struct nv50_disp *disp = nv50_disp(encoder->dev); 533 struct { 534 struct nv50_disp_mthd_v1 base; 535 struct nv50_disp_dac_load_v0 load; 536 } args = { 537 .base.version = 1, 538 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 539 .base.hasht = nv_encoder->dcb->hasht, 540 .base.hashm = nv_encoder->dcb->hashm, 541 }; 542 int ret; 543 544 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 545 if (args.load.data == 0) 546 args.load.data = 340; 547 548 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 549 if (ret || !args.load.load) 550 return connector_status_disconnected; 551 552 return connector_status_connected; 553 } 554 555 static const struct drm_encoder_helper_funcs 556 nv50_dac_help = { 557 .atomic_check = nv50_outp_atomic_check, 558 .atomic_enable = nv50_dac_atomic_enable, 559 .atomic_disable = nv50_dac_atomic_disable, 560 .detect = nv50_dac_detect 561 }; 562 563 static void 564 nv50_dac_destroy(struct drm_encoder *encoder) 565 { 566 drm_encoder_cleanup(encoder); 567 kfree(encoder); 568 } 569 570 static const struct drm_encoder_funcs 571 nv50_dac_func = { 572 .destroy = nv50_dac_destroy, 573 }; 574 575 static int 576 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 577 { 578 struct nouveau_drm *drm = nouveau_drm(connector->dev); 579 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 580 struct nvkm_i2c_bus *bus; 581 struct nouveau_encoder *nv_encoder; 582 struct drm_encoder *encoder; 583 int type = DRM_MODE_ENCODER_DAC; 584 585 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 586 if (!nv_encoder) 587 return -ENOMEM; 588 nv_encoder->dcb = dcbe; 589 590 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 591 if (bus) 592 nv_encoder->i2c = &bus->i2c; 593 594 encoder = to_drm_encoder(nv_encoder); 595 encoder->possible_crtcs = dcbe->heads; 596 encoder->possible_clones = 0; 597 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 598 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 599 drm_encoder_helper_add(encoder, &nv50_dac_help); 600 601 drm_connector_attach_encoder(connector, encoder); 602 return 0; 603 } 604 605 /* 606 * audio component binding for ELD notification 607 */ 608 static void 609 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 610 int dev_id) 611 { 612 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 613 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 614 port, dev_id); 615 } 616 617 static int 618 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 619 bool *enabled, unsigned char *buf, int max_bytes) 620 { 621 struct drm_device *drm_dev = dev_get_drvdata(kdev); 622 struct nouveau_drm *drm = nouveau_drm(drm_dev); 623 struct drm_encoder *encoder; 624 struct nouveau_encoder *nv_encoder; 625 struct nouveau_crtc *nv_crtc; 626 int ret = 0; 627 628 *enabled = false; 629 630 mutex_lock(&drm->audio.lock); 631 632 drm_for_each_encoder(encoder, drm->dev) { 633 struct nouveau_connector *nv_connector = NULL; 634 635 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) 636 continue; /* TODO */ 637 638 nv_encoder = nouveau_encoder(encoder); 639 nv_connector = nouveau_connector(nv_encoder->audio.connector); 640 nv_crtc = nouveau_crtc(nv_encoder->crtc); 641 642 if (!nv_crtc || nv_encoder->or != port || nv_crtc->index != dev_id) 643 continue; 644 645 *enabled = nv_encoder->audio.enabled; 646 if (*enabled) { 647 ret = drm_eld_size(nv_connector->base.eld); 648 memcpy(buf, nv_connector->base.eld, 649 min(max_bytes, ret)); 650 } 651 break; 652 } 653 654 mutex_unlock(&drm->audio.lock); 655 656 return ret; 657 } 658 659 static const struct drm_audio_component_ops nv50_audio_component_ops = { 660 .get_eld = nv50_audio_component_get_eld, 661 }; 662 663 static int 664 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 665 void *data) 666 { 667 struct drm_device *drm_dev = dev_get_drvdata(kdev); 668 struct nouveau_drm *drm = nouveau_drm(drm_dev); 669 struct drm_audio_component *acomp = data; 670 671 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 672 return -ENOMEM; 673 674 drm_modeset_lock_all(drm_dev); 675 acomp->ops = &nv50_audio_component_ops; 676 acomp->dev = kdev; 677 drm->audio.component = acomp; 678 drm_modeset_unlock_all(drm_dev); 679 return 0; 680 } 681 682 static void 683 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 684 void *data) 685 { 686 struct drm_device *drm_dev = dev_get_drvdata(kdev); 687 struct nouveau_drm *drm = nouveau_drm(drm_dev); 688 struct drm_audio_component *acomp = data; 689 690 drm_modeset_lock_all(drm_dev); 691 drm->audio.component = NULL; 692 acomp->ops = NULL; 693 acomp->dev = NULL; 694 drm_modeset_unlock_all(drm_dev); 695 } 696 697 static const struct component_ops nv50_audio_component_bind_ops = { 698 .bind = nv50_audio_component_bind, 699 .unbind = nv50_audio_component_unbind, 700 }; 701 702 static void 703 nv50_audio_component_init(struct nouveau_drm *drm) 704 { 705 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 706 return; 707 708 drm->audio.component_registered = true; 709 mutex_init(&drm->audio.lock); 710 } 711 712 static void 713 nv50_audio_component_fini(struct nouveau_drm *drm) 714 { 715 if (!drm->audio.component_registered) 716 return; 717 718 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 719 drm->audio.component_registered = false; 720 mutex_destroy(&drm->audio.lock); 721 } 722 723 /****************************************************************************** 724 * Audio 725 *****************************************************************************/ 726 static void 727 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 728 { 729 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 730 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 731 struct nv50_disp *disp = nv50_disp(encoder->dev); 732 struct { 733 struct nv50_disp_mthd_v1 base; 734 struct nv50_disp_sor_hda_eld_v0 eld; 735 } args = { 736 .base.version = 1, 737 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 738 .base.hasht = nv_encoder->dcb->hasht, 739 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 740 (0x0100 << nv_crtc->index), 741 }; 742 743 mutex_lock(&drm->audio.lock); 744 if (nv_encoder->audio.enabled) { 745 nv_encoder->audio.enabled = false; 746 nv_encoder->audio.connector = NULL; 747 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 748 } 749 mutex_unlock(&drm->audio.lock); 750 751 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 752 nv_crtc->index); 753 } 754 755 static void 756 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 757 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 758 struct drm_display_mode *mode) 759 { 760 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 761 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 762 struct nv50_disp *disp = nv50_disp(encoder->dev); 763 struct __packed { 764 struct { 765 struct nv50_disp_mthd_v1 mthd; 766 struct nv50_disp_sor_hda_eld_v0 eld; 767 } base; 768 u8 data[sizeof(nv_connector->base.eld)]; 769 } args = { 770 .base.mthd.version = 1, 771 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 772 .base.mthd.hasht = nv_encoder->dcb->hasht, 773 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 774 (0x0100 << nv_crtc->index), 775 }; 776 777 if (!drm_detect_monitor_audio(nv_connector->edid)) 778 return; 779 780 mutex_lock(&drm->audio.lock); 781 782 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 783 784 nvif_mthd(&disp->disp->object, 0, &args, 785 sizeof(args.base) + drm_eld_size(args.data)); 786 nv_encoder->audio.enabled = true; 787 nv_encoder->audio.connector = &nv_connector->base; 788 789 mutex_unlock(&drm->audio.lock); 790 791 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 792 nv_crtc->index); 793 } 794 795 /****************************************************************************** 796 * HDMI 797 *****************************************************************************/ 798 static void 799 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 800 { 801 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 802 struct nv50_disp *disp = nv50_disp(encoder->dev); 803 struct { 804 struct nv50_disp_mthd_v1 base; 805 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 806 } args = { 807 .base.version = 1, 808 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 809 .base.hasht = nv_encoder->dcb->hasht, 810 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 811 (0x0100 << nv_crtc->index), 812 }; 813 814 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 815 } 816 817 static void 818 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 819 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 820 struct drm_display_mode *mode) 821 { 822 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 823 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 824 struct nv50_disp *disp = nv50_disp(encoder->dev); 825 struct { 826 struct nv50_disp_mthd_v1 base; 827 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 828 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 829 } args = { 830 .base.version = 1, 831 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 832 .base.hasht = nv_encoder->dcb->hasht, 833 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 834 (0x0100 << nv_crtc->index), 835 .pwr.state = 1, 836 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 837 }; 838 struct drm_hdmi_info *hdmi; 839 u32 max_ac_packet; 840 union hdmi_infoframe avi_frame; 841 union hdmi_infoframe vendor_frame; 842 bool high_tmds_clock_ratio = false, scrambling = false; 843 u8 config; 844 int ret; 845 int size; 846 847 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 848 return; 849 850 hdmi = &nv_connector->base.display_info.hdmi; 851 852 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 853 &nv_connector->base, mode); 854 if (!ret) { 855 /* We have an AVI InfoFrame, populate it to the display */ 856 args.pwr.avi_infoframe_length 857 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 858 } 859 860 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 861 &nv_connector->base, mode); 862 if (!ret) { 863 /* We have a Vendor InfoFrame, populate it to the display */ 864 args.pwr.vendor_infoframe_length 865 = hdmi_infoframe_pack(&vendor_frame, 866 args.infoframes 867 + args.pwr.avi_infoframe_length, 868 17); 869 } 870 871 max_ac_packet = mode->htotal - mode->hdisplay; 872 max_ac_packet -= args.pwr.rekey; 873 max_ac_packet -= 18; /* constant from tegra */ 874 args.pwr.max_ac_packet = max_ac_packet / 32; 875 876 if (hdmi->scdc.scrambling.supported) { 877 high_tmds_clock_ratio = mode->clock > 340000; 878 scrambling = high_tmds_clock_ratio || 879 hdmi->scdc.scrambling.low_rates; 880 } 881 882 args.pwr.scdc = 883 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 884 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 885 886 size = sizeof(args.base) 887 + sizeof(args.pwr) 888 + args.pwr.avi_infoframe_length 889 + args.pwr.vendor_infoframe_length; 890 nvif_mthd(&disp->disp->object, 0, &args, size); 891 892 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 893 894 /* If SCDC is supported by the downstream monitor, update 895 * divider / scrambling settings to what we programmed above. 896 */ 897 if (!hdmi->scdc.scrambling.supported) 898 return; 899 900 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 901 if (ret < 0) { 902 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 903 return; 904 } 905 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 906 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 907 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 908 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 909 if (ret < 0) 910 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 911 config, ret); 912 } 913 914 /****************************************************************************** 915 * MST 916 *****************************************************************************/ 917 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 918 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 919 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 920 921 struct nv50_mstc { 922 struct nv50_mstm *mstm; 923 struct drm_dp_mst_port *port; 924 struct drm_connector connector; 925 926 struct drm_display_mode *native; 927 struct edid *edid; 928 }; 929 930 struct nv50_msto { 931 struct drm_encoder encoder; 932 933 /* head is statically assigned on msto creation */ 934 struct nv50_head *head; 935 struct nv50_mstc *mstc; 936 bool disabled; 937 }; 938 939 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 940 { 941 struct nv50_msto *msto; 942 943 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 944 return nouveau_encoder(encoder); 945 946 msto = nv50_msto(encoder); 947 if (!msto->mstc) 948 return NULL; 949 return msto->mstc->mstm->outp; 950 } 951 952 static struct drm_dp_payload * 953 nv50_msto_payload(struct nv50_msto *msto) 954 { 955 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 956 struct nv50_mstc *mstc = msto->mstc; 957 struct nv50_mstm *mstm = mstc->mstm; 958 int vcpi = mstc->port->vcpi.vcpi, i; 959 960 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 961 962 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 963 for (i = 0; i < mstm->mgr.max_payloads; i++) { 964 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 965 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 966 mstm->outp->base.base.name, i, payload->vcpi, 967 payload->start_slot, payload->num_slots); 968 } 969 970 for (i = 0; i < mstm->mgr.max_payloads; i++) { 971 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 972 if (payload->vcpi == vcpi) 973 return payload; 974 } 975 976 return NULL; 977 } 978 979 static void 980 nv50_msto_cleanup(struct nv50_msto *msto) 981 { 982 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 983 struct nv50_mstc *mstc = msto->mstc; 984 struct nv50_mstm *mstm = mstc->mstm; 985 986 if (!msto->disabled) 987 return; 988 989 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 990 991 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 992 993 msto->mstc = NULL; 994 msto->disabled = false; 995 } 996 997 static void 998 nv50_msto_prepare(struct nv50_msto *msto) 999 { 1000 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 1001 struct nv50_mstc *mstc = msto->mstc; 1002 struct nv50_mstm *mstm = mstc->mstm; 1003 struct { 1004 struct nv50_disp_mthd_v1 base; 1005 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 1006 } args = { 1007 .base.version = 1, 1008 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 1009 .base.hasht = mstm->outp->dcb->hasht, 1010 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 1011 (0x0100 << msto->head->base.index), 1012 }; 1013 1014 mutex_lock(&mstm->mgr.payload_lock); 1015 1016 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 1017 if (mstc->port->vcpi.vcpi > 0) { 1018 struct drm_dp_payload *payload = nv50_msto_payload(msto); 1019 if (payload) { 1020 args.vcpi.start_slot = payload->start_slot; 1021 args.vcpi.num_slots = payload->num_slots; 1022 args.vcpi.pbn = mstc->port->vcpi.pbn; 1023 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 1024 } 1025 } 1026 1027 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 1028 msto->encoder.name, msto->head->base.base.name, 1029 args.vcpi.start_slot, args.vcpi.num_slots, 1030 args.vcpi.pbn, args.vcpi.aligned_pbn); 1031 1032 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 1033 mutex_unlock(&mstm->mgr.payload_lock); 1034 } 1035 1036 static int 1037 nv50_msto_atomic_check(struct drm_encoder *encoder, 1038 struct drm_crtc_state *crtc_state, 1039 struct drm_connector_state *conn_state) 1040 { 1041 struct drm_atomic_state *state = crtc_state->state; 1042 struct drm_connector *connector = conn_state->connector; 1043 struct nv50_mstc *mstc = nv50_mstc(connector); 1044 struct nv50_mstm *mstm = mstc->mstm; 1045 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 1046 int slots; 1047 int ret; 1048 1049 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 1050 mstc->native); 1051 if (ret) 1052 return ret; 1053 1054 if (!crtc_state->mode_changed && !crtc_state->connectors_changed) 1055 return 0; 1056 1057 /* 1058 * When restoring duplicated states, we need to make sure that the bw 1059 * remains the same and avoid recalculating it, as the connector's bpc 1060 * may have changed after the state was duplicated 1061 */ 1062 if (!state->duplicated) { 1063 const int clock = crtc_state->adjusted_mode.clock; 1064 1065 asyh->or.bpc = connector->display_info.bpc; 1066 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 1067 false); 1068 } 1069 1070 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, 1071 asyh->dp.pbn, 0); 1072 if (slots < 0) 1073 return slots; 1074 1075 asyh->dp.tu = slots; 1076 1077 return 0; 1078 } 1079 1080 static u8 1081 nv50_dp_bpc_to_depth(unsigned int bpc) 1082 { 1083 switch (bpc) { 1084 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; 1085 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; 1086 case 10: 1087 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; 1088 } 1089 } 1090 1091 static void 1092 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1093 { 1094 struct nv50_msto *msto = nv50_msto(encoder); 1095 struct nv50_head *head = msto->head; 1096 struct nv50_head_atom *asyh = 1097 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base)); 1098 struct nv50_mstc *mstc = NULL; 1099 struct nv50_mstm *mstm = NULL; 1100 struct drm_connector *connector; 1101 struct drm_connector_list_iter conn_iter; 1102 u8 proto; 1103 bool r; 1104 1105 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 1106 drm_for_each_connector_iter(connector, &conn_iter) { 1107 if (connector->state->best_encoder == &msto->encoder) { 1108 mstc = nv50_mstc(connector); 1109 mstm = mstc->mstm; 1110 break; 1111 } 1112 } 1113 drm_connector_list_iter_end(&conn_iter); 1114 1115 if (WARN_ON(!mstc)) 1116 return; 1117 1118 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, asyh->dp.pbn, asyh->dp.tu); 1119 if (!r) 1120 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 1121 1122 if (!mstm->links++) 1123 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); 1124 1125 if (mstm->outp->link & 1) 1126 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1127 else 1128 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1129 1130 mstm->outp->update(mstm->outp, head->base.index, asyh, proto, 1131 nv50_dp_bpc_to_depth(asyh->or.bpc)); 1132 1133 msto->mstc = mstc; 1134 mstm->modified = true; 1135 } 1136 1137 static void 1138 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1139 { 1140 struct nv50_msto *msto = nv50_msto(encoder); 1141 struct nv50_mstc *mstc = msto->mstc; 1142 struct nv50_mstm *mstm = mstc->mstm; 1143 1144 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 1145 1146 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 1147 mstm->modified = true; 1148 if (!--mstm->links) 1149 mstm->disabled = true; 1150 msto->disabled = true; 1151 } 1152 1153 static const struct drm_encoder_helper_funcs 1154 nv50_msto_help = { 1155 .atomic_disable = nv50_msto_atomic_disable, 1156 .atomic_enable = nv50_msto_atomic_enable, 1157 .atomic_check = nv50_msto_atomic_check, 1158 }; 1159 1160 static void 1161 nv50_msto_destroy(struct drm_encoder *encoder) 1162 { 1163 struct nv50_msto *msto = nv50_msto(encoder); 1164 drm_encoder_cleanup(&msto->encoder); 1165 kfree(msto); 1166 } 1167 1168 static const struct drm_encoder_funcs 1169 nv50_msto = { 1170 .destroy = nv50_msto_destroy, 1171 }; 1172 1173 static struct nv50_msto * 1174 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1175 { 1176 struct nv50_msto *msto; 1177 int ret; 1178 1179 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1180 if (!msto) 1181 return ERR_PTR(-ENOMEM); 1182 1183 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1184 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1185 if (ret) { 1186 kfree(msto); 1187 return ERR_PTR(ret); 1188 } 1189 1190 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1191 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1192 msto->head = head; 1193 return msto; 1194 } 1195 1196 static struct drm_encoder * 1197 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1198 struct drm_atomic_state *state) 1199 { 1200 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 1201 connector); 1202 struct nv50_mstc *mstc = nv50_mstc(connector); 1203 struct drm_crtc *crtc = connector_state->crtc; 1204 1205 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1206 return NULL; 1207 1208 return &nv50_head(crtc)->msto->encoder; 1209 } 1210 1211 static enum drm_mode_status 1212 nv50_mstc_mode_valid(struct drm_connector *connector, 1213 struct drm_display_mode *mode) 1214 { 1215 struct nv50_mstc *mstc = nv50_mstc(connector); 1216 struct nouveau_encoder *outp = mstc->mstm->outp; 1217 1218 /* TODO: calculate the PBN from the dotclock and validate against the 1219 * MSTB's max possible PBN 1220 */ 1221 1222 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1223 } 1224 1225 static int 1226 nv50_mstc_get_modes(struct drm_connector *connector) 1227 { 1228 struct nv50_mstc *mstc = nv50_mstc(connector); 1229 int ret = 0; 1230 1231 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1232 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1233 if (mstc->edid) 1234 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1235 1236 /* 1237 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1238 * to 8 to save bandwidth on the topology. In the future, we'll want 1239 * to properly fix this by dynamically selecting the highest possible 1240 * bpc that would fit in the topology 1241 */ 1242 if (connector->display_info.bpc) 1243 connector->display_info.bpc = 1244 clamp(connector->display_info.bpc, 6U, 8U); 1245 else 1246 connector->display_info.bpc = 8; 1247 1248 if (mstc->native) 1249 drm_mode_destroy(mstc->connector.dev, mstc->native); 1250 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1251 return ret; 1252 } 1253 1254 static int 1255 nv50_mstc_atomic_check(struct drm_connector *connector, 1256 struct drm_atomic_state *state) 1257 { 1258 struct nv50_mstc *mstc = nv50_mstc(connector); 1259 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1260 struct drm_connector_state *new_conn_state = 1261 drm_atomic_get_new_connector_state(state, connector); 1262 struct drm_connector_state *old_conn_state = 1263 drm_atomic_get_old_connector_state(state, connector); 1264 struct drm_crtc_state *crtc_state; 1265 struct drm_crtc *new_crtc = new_conn_state->crtc; 1266 1267 if (!old_conn_state->crtc) 1268 return 0; 1269 1270 /* We only want to free VCPI if this state disables the CRTC on this 1271 * connector 1272 */ 1273 if (new_crtc) { 1274 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 1275 1276 if (!crtc_state || 1277 !drm_atomic_crtc_needs_modeset(crtc_state) || 1278 crtc_state->enable) 1279 return 0; 1280 } 1281 1282 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 1283 } 1284 1285 static int 1286 nv50_mstc_detect(struct drm_connector *connector, 1287 struct drm_modeset_acquire_ctx *ctx, bool force) 1288 { 1289 struct nv50_mstc *mstc = nv50_mstc(connector); 1290 int ret; 1291 1292 if (drm_connector_is_unregistered(connector)) 1293 return connector_status_disconnected; 1294 1295 ret = pm_runtime_get_sync(connector->dev->dev); 1296 if (ret < 0 && ret != -EACCES) { 1297 pm_runtime_put_autosuspend(connector->dev->dev); 1298 return connector_status_disconnected; 1299 } 1300 1301 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1302 mstc->port); 1303 if (ret != connector_status_connected) 1304 goto out; 1305 1306 out: 1307 pm_runtime_mark_last_busy(connector->dev->dev); 1308 pm_runtime_put_autosuspend(connector->dev->dev); 1309 return ret; 1310 } 1311 1312 static const struct drm_connector_helper_funcs 1313 nv50_mstc_help = { 1314 .get_modes = nv50_mstc_get_modes, 1315 .mode_valid = nv50_mstc_mode_valid, 1316 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1317 .atomic_check = nv50_mstc_atomic_check, 1318 .detect_ctx = nv50_mstc_detect, 1319 }; 1320 1321 static void 1322 nv50_mstc_destroy(struct drm_connector *connector) 1323 { 1324 struct nv50_mstc *mstc = nv50_mstc(connector); 1325 1326 drm_connector_cleanup(&mstc->connector); 1327 drm_dp_mst_put_port_malloc(mstc->port); 1328 1329 kfree(mstc); 1330 } 1331 1332 static const struct drm_connector_funcs 1333 nv50_mstc = { 1334 .reset = nouveau_conn_reset, 1335 .fill_modes = drm_helper_probe_single_connector_modes, 1336 .destroy = nv50_mstc_destroy, 1337 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1338 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1339 .atomic_set_property = nouveau_conn_atomic_set_property, 1340 .atomic_get_property = nouveau_conn_atomic_get_property, 1341 }; 1342 1343 static int 1344 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1345 const char *path, struct nv50_mstc **pmstc) 1346 { 1347 struct drm_device *dev = mstm->outp->base.base.dev; 1348 struct drm_crtc *crtc; 1349 struct nv50_mstc *mstc; 1350 int ret; 1351 1352 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1353 return -ENOMEM; 1354 mstc->mstm = mstm; 1355 mstc->port = port; 1356 1357 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1358 DRM_MODE_CONNECTOR_DisplayPort); 1359 if (ret) { 1360 kfree(*pmstc); 1361 *pmstc = NULL; 1362 return ret; 1363 } 1364 1365 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1366 1367 mstc->connector.funcs->reset(&mstc->connector); 1368 nouveau_conn_attach_properties(&mstc->connector); 1369 1370 drm_for_each_crtc(crtc, dev) { 1371 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1372 continue; 1373 1374 drm_connector_attach_encoder(&mstc->connector, 1375 &nv50_head(crtc)->msto->encoder); 1376 } 1377 1378 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1379 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1380 drm_connector_set_path_property(&mstc->connector, path); 1381 drm_dp_mst_get_port_malloc(port); 1382 return 0; 1383 } 1384 1385 static void 1386 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1387 { 1388 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1389 struct drm_encoder *encoder; 1390 int ret; 1391 1392 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1393 ret = drm_dp_check_act_status(&mstm->mgr); 1394 1395 ret = drm_dp_update_payload_part2(&mstm->mgr); 1396 1397 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1398 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1399 struct nv50_msto *msto = nv50_msto(encoder); 1400 struct nv50_mstc *mstc = msto->mstc; 1401 if (mstc && mstc->mstm == mstm) 1402 nv50_msto_cleanup(msto); 1403 } 1404 } 1405 1406 mstm->modified = false; 1407 } 1408 1409 static void 1410 nv50_mstm_prepare(struct nv50_mstm *mstm) 1411 { 1412 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1413 struct drm_encoder *encoder; 1414 int ret; 1415 1416 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1417 ret = drm_dp_update_payload_part1(&mstm->mgr); 1418 1419 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1420 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1421 struct nv50_msto *msto = nv50_msto(encoder); 1422 struct nv50_mstc *mstc = msto->mstc; 1423 if (mstc && mstc->mstm == mstm) 1424 nv50_msto_prepare(msto); 1425 } 1426 } 1427 1428 if (mstm->disabled) { 1429 if (!mstm->links) 1430 nv50_outp_release(mstm->outp); 1431 mstm->disabled = false; 1432 } 1433 } 1434 1435 static struct drm_connector * 1436 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1437 struct drm_dp_mst_port *port, const char *path) 1438 { 1439 struct nv50_mstm *mstm = nv50_mstm(mgr); 1440 struct nv50_mstc *mstc; 1441 int ret; 1442 1443 ret = nv50_mstc_new(mstm, port, path, &mstc); 1444 if (ret) 1445 return NULL; 1446 1447 return &mstc->connector; 1448 } 1449 1450 static const struct drm_dp_mst_topology_cbs 1451 nv50_mstm = { 1452 .add_connector = nv50_mstm_add_connector, 1453 }; 1454 1455 bool 1456 nv50_mstm_service(struct nouveau_drm *drm, 1457 struct nouveau_connector *nv_connector, 1458 struct nv50_mstm *mstm) 1459 { 1460 struct drm_dp_aux *aux = &nv_connector->aux; 1461 bool handled = true, ret = true; 1462 int rc; 1463 u8 esi[8] = {}; 1464 1465 while (handled) { 1466 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1467 if (rc != 8) { 1468 ret = false; 1469 break; 1470 } 1471 1472 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1473 if (!handled) 1474 break; 1475 1476 rc = drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 1477 3); 1478 if (rc != 3) { 1479 ret = false; 1480 break; 1481 } 1482 } 1483 1484 if (!ret) 1485 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n", 1486 nv_connector->base.name, rc); 1487 1488 return ret; 1489 } 1490 1491 void 1492 nv50_mstm_remove(struct nv50_mstm *mstm) 1493 { 1494 mstm->is_mst = false; 1495 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1496 } 1497 1498 static int 1499 nv50_mstm_enable(struct nv50_mstm *mstm, int state) 1500 { 1501 struct nouveau_encoder *outp = mstm->outp; 1502 struct { 1503 struct nv50_disp_mthd_v1 base; 1504 struct nv50_disp_sor_dp_mst_link_v0 mst; 1505 } args = { 1506 .base.version = 1, 1507 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1508 .base.hasht = outp->dcb->hasht, 1509 .base.hashm = outp->dcb->hashm, 1510 .mst.state = state, 1511 }; 1512 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1513 struct nvif_object *disp = &drm->display->disp.object; 1514 1515 return nvif_mthd(disp, 0, &args, sizeof(args)); 1516 } 1517 1518 int 1519 nv50_mstm_detect(struct nouveau_encoder *outp) 1520 { 1521 struct nv50_mstm *mstm = outp->dp.mstm; 1522 struct drm_dp_aux *aux; 1523 int ret; 1524 1525 if (!mstm || !mstm->can_mst) 1526 return 0; 1527 1528 aux = mstm->mgr.aux; 1529 1530 /* Clear any leftover MST state we didn't set ourselves by first 1531 * disabling MST if it was already enabled 1532 */ 1533 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1534 if (ret < 0) 1535 return ret; 1536 1537 /* And start enabling */ 1538 ret = nv50_mstm_enable(mstm, true); 1539 if (ret) 1540 return ret; 1541 1542 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true); 1543 if (ret) { 1544 nv50_mstm_enable(mstm, false); 1545 return ret; 1546 } 1547 1548 mstm->is_mst = true; 1549 return 1; 1550 } 1551 1552 static void 1553 nv50_mstm_fini(struct nouveau_encoder *outp) 1554 { 1555 struct nv50_mstm *mstm = outp->dp.mstm; 1556 1557 if (!mstm) 1558 return; 1559 1560 /* Don't change the MST state of this connector until we've finished 1561 * resuming, since we can't safely grab hpd_irq_lock in our resume 1562 * path to protect mstm->is_mst without potentially deadlocking 1563 */ 1564 mutex_lock(&outp->dp.hpd_irq_lock); 1565 mstm->suspended = true; 1566 mutex_unlock(&outp->dp.hpd_irq_lock); 1567 1568 if (mstm->is_mst) 1569 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1570 } 1571 1572 static void 1573 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime) 1574 { 1575 struct nv50_mstm *mstm = outp->dp.mstm; 1576 int ret = 0; 1577 1578 if (!mstm) 1579 return; 1580 1581 if (mstm->is_mst) { 1582 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1583 if (ret == -1) 1584 nv50_mstm_remove(mstm); 1585 } 1586 1587 mutex_lock(&outp->dp.hpd_irq_lock); 1588 mstm->suspended = false; 1589 mutex_unlock(&outp->dp.hpd_irq_lock); 1590 1591 if (ret == -1) 1592 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1593 } 1594 1595 static void 1596 nv50_mstm_del(struct nv50_mstm **pmstm) 1597 { 1598 struct nv50_mstm *mstm = *pmstm; 1599 if (mstm) { 1600 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1601 kfree(*pmstm); 1602 *pmstm = NULL; 1603 } 1604 } 1605 1606 static int 1607 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1608 int conn_base_id, struct nv50_mstm **pmstm) 1609 { 1610 const int max_payloads = hweight8(outp->dcb->heads); 1611 struct drm_device *dev = outp->base.base.dev; 1612 struct nv50_mstm *mstm; 1613 int ret; 1614 1615 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1616 return -ENOMEM; 1617 mstm->outp = outp; 1618 mstm->mgr.cbs = &nv50_mstm; 1619 1620 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1621 max_payloads, outp->dcb->dpconf.link_nr, 1622 drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw), 1623 conn_base_id); 1624 if (ret) 1625 return ret; 1626 1627 return 0; 1628 } 1629 1630 /****************************************************************************** 1631 * SOR 1632 *****************************************************************************/ 1633 static void 1634 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1635 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1636 { 1637 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1638 struct nv50_core *core = disp->core; 1639 1640 if (!asyh) { 1641 nv_encoder->ctrl &= ~BIT(head); 1642 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) 1643 nv_encoder->ctrl = 0; 1644 } else { 1645 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); 1646 nv_encoder->ctrl |= BIT(head); 1647 asyh->or.depth = depth; 1648 } 1649 1650 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1651 } 1652 1653 /* TODO: Should we extend this to PWM-only backlights? 1654 * As well, should we add a DRM helper for waiting for the backlight to acknowledge 1655 * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a 1656 * fixed time delay from the vbios… 1657 */ 1658 static void 1659 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1660 { 1661 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1662 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 1663 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1664 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder); 1665 struct nouveau_backlight *backlight = nv_connector->backlight; 1666 struct drm_dp_aux *aux = &nv_connector->aux; 1667 int ret; 1668 u8 pwr; 1669 1670 if (backlight && backlight->uses_dpcd) { 1671 ret = drm_edp_backlight_disable(aux, &backlight->edp_info); 1672 if (ret < 0) 1673 NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n", 1674 nv_connector->base.base.id, nv_connector->base.name, ret); 1675 } 1676 1677 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 1678 int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr); 1679 1680 if (ret == 0) { 1681 pwr &= ~DP_SET_POWER_MASK; 1682 pwr |= DP_SET_POWER_D3; 1683 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr); 1684 } 1685 } 1686 1687 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1688 nv50_audio_disable(encoder, nv_crtc); 1689 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1690 nv50_outp_release(nv_encoder); 1691 nv_encoder->crtc = NULL; 1692 } 1693 1694 static void 1695 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1696 { 1697 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1698 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1699 struct nv50_head_atom *asyh = 1700 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1701 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1702 struct { 1703 struct nv50_disp_mthd_v1 base; 1704 struct nv50_disp_sor_lvds_script_v0 lvds; 1705 } lvds = { 1706 .base.version = 1, 1707 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1708 .base.hasht = nv_encoder->dcb->hasht, 1709 .base.hashm = nv_encoder->dcb->hashm, 1710 }; 1711 struct nv50_disp *disp = nv50_disp(encoder->dev); 1712 struct drm_device *dev = encoder->dev; 1713 struct nouveau_drm *drm = nouveau_drm(dev); 1714 struct nouveau_connector *nv_connector; 1715 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1716 struct nouveau_backlight *backlight; 1717 #endif 1718 struct nvbios *bios = &drm->vbios; 1719 bool hda = false; 1720 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; 1721 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; 1722 1723 nv_connector = nv50_outp_get_new_connector(state, nv_encoder); 1724 nv_encoder->crtc = &nv_crtc->base; 1725 1726 if ((disp->disp->object.oclass == GT214_DISP || 1727 disp->disp->object.oclass >= GF110_DISP) && 1728 drm_detect_monitor_audio(nv_connector->edid)) 1729 hda = true; 1730 nv50_outp_acquire(nv_encoder, hda); 1731 1732 switch (nv_encoder->dcb->type) { 1733 case DCB_OUTPUT_TMDS: 1734 if (nv_encoder->link & 1) { 1735 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; 1736 /* Only enable dual-link if: 1737 * - Need to (i.e. rate > 165MHz) 1738 * - DCB says we can 1739 * - Not an HDMI monitor, since there's no dual-link 1740 * on HDMI. 1741 */ 1742 if (mode->clock >= 165000 && 1743 nv_encoder->dcb->duallink_possible && 1744 !drm_detect_hdmi_monitor(nv_connector->edid)) 1745 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; 1746 } else { 1747 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; 1748 } 1749 1750 nv50_hdmi_enable(&nv_encoder->base.base, nv_crtc, nv_connector, state, mode); 1751 break; 1752 case DCB_OUTPUT_LVDS: 1753 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; 1754 1755 if (bios->fp_no_ddc) { 1756 if (bios->fp.dual_link) 1757 lvds.lvds.script |= 0x0100; 1758 if (bios->fp.if_is_24bit) 1759 lvds.lvds.script |= 0x0200; 1760 } else { 1761 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1762 if (((u8 *)nv_connector->edid)[121] == 2) 1763 lvds.lvds.script |= 0x0100; 1764 } else 1765 if (mode->clock >= bios->fp.duallink_transition_clk) { 1766 lvds.lvds.script |= 0x0100; 1767 } 1768 1769 if (lvds.lvds.script & 0x0100) { 1770 if (bios->fp.strapless_is_24bit & 2) 1771 lvds.lvds.script |= 0x0200; 1772 } else { 1773 if (bios->fp.strapless_is_24bit & 1) 1774 lvds.lvds.script |= 0x0200; 1775 } 1776 1777 if (asyh->or.bpc == 8) 1778 lvds.lvds.script |= 0x0200; 1779 } 1780 1781 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1782 break; 1783 case DCB_OUTPUT_DP: 1784 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1785 1786 if (nv_encoder->link & 1) 1787 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1788 else 1789 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1790 1791 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 1792 1793 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1794 backlight = nv_connector->backlight; 1795 if (backlight && backlight->uses_dpcd) 1796 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info, 1797 (u16)backlight->dev->props.brightness); 1798 #endif 1799 1800 break; 1801 default: 1802 BUG(); 1803 break; 1804 } 1805 1806 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1807 } 1808 1809 static const struct drm_encoder_helper_funcs 1810 nv50_sor_help = { 1811 .atomic_check = nv50_outp_atomic_check, 1812 .atomic_enable = nv50_sor_atomic_enable, 1813 .atomic_disable = nv50_sor_atomic_disable, 1814 }; 1815 1816 static void 1817 nv50_sor_destroy(struct drm_encoder *encoder) 1818 { 1819 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1820 nv50_mstm_del(&nv_encoder->dp.mstm); 1821 drm_encoder_cleanup(encoder); 1822 1823 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) 1824 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1825 1826 kfree(encoder); 1827 } 1828 1829 static const struct drm_encoder_funcs 1830 nv50_sor_func = { 1831 .destroy = nv50_sor_destroy, 1832 }; 1833 1834 static bool nv50_has_mst(struct nouveau_drm *drm) 1835 { 1836 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1837 u32 data; 1838 u8 ver, hdr, cnt, len; 1839 1840 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1841 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1842 } 1843 1844 static int 1845 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1846 { 1847 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1848 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1849 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1850 struct nouveau_encoder *nv_encoder; 1851 struct drm_encoder *encoder; 1852 struct nv50_disp *disp = nv50_disp(connector->dev); 1853 int type, ret; 1854 1855 switch (dcbe->type) { 1856 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1857 case DCB_OUTPUT_TMDS: 1858 case DCB_OUTPUT_DP: 1859 default: 1860 type = DRM_MODE_ENCODER_TMDS; 1861 break; 1862 } 1863 1864 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1865 if (!nv_encoder) 1866 return -ENOMEM; 1867 nv_encoder->dcb = dcbe; 1868 nv_encoder->update = nv50_sor_update; 1869 1870 encoder = to_drm_encoder(nv_encoder); 1871 encoder->possible_crtcs = dcbe->heads; 1872 encoder->possible_clones = 0; 1873 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1874 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1875 drm_encoder_helper_add(encoder, &nv50_sor_help); 1876 1877 drm_connector_attach_encoder(connector, encoder); 1878 1879 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1880 nv50_outp_dump_caps(drm, nv_encoder); 1881 1882 if (dcbe->type == DCB_OUTPUT_DP) { 1883 struct nvkm_i2c_aux *aux = 1884 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1885 1886 mutex_init(&nv_encoder->dp.hpd_irq_lock); 1887 1888 if (aux) { 1889 if (disp->disp->object.oclass < GF110_DISP) { 1890 /* HW has no support for address-only 1891 * transactions, so we're required to 1892 * use custom I2C-over-AUX code. 1893 */ 1894 nv_encoder->i2c = &aux->i2c; 1895 } else { 1896 nv_encoder->i2c = &nv_connector->aux.ddc; 1897 } 1898 nv_encoder->aux = aux; 1899 } 1900 1901 if (nv_connector->type != DCB_CONNECTOR_eDP && 1902 nv50_has_mst(drm)) { 1903 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1904 16, nv_connector->base.base.id, 1905 &nv_encoder->dp.mstm); 1906 if (ret) 1907 return ret; 1908 } 1909 } else { 1910 struct nvkm_i2c_bus *bus = 1911 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1912 if (bus) 1913 nv_encoder->i2c = &bus->i2c; 1914 } 1915 1916 return 0; 1917 } 1918 1919 /****************************************************************************** 1920 * PIOR 1921 *****************************************************************************/ 1922 static int 1923 nv50_pior_atomic_check(struct drm_encoder *encoder, 1924 struct drm_crtc_state *crtc_state, 1925 struct drm_connector_state *conn_state) 1926 { 1927 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1928 if (ret) 1929 return ret; 1930 crtc_state->adjusted_mode.clock *= 2; 1931 return 0; 1932 } 1933 1934 static void 1935 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1936 { 1937 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1938 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1939 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); 1940 1941 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL); 1942 nv_encoder->crtc = NULL; 1943 nv50_outp_release(nv_encoder); 1944 } 1945 1946 static void 1947 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1948 { 1949 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1950 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1951 struct nv50_head_atom *asyh = 1952 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1953 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1954 u32 ctrl = 0; 1955 1956 switch (nv_crtc->index) { 1957 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; 1958 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; 1959 default: 1960 WARN_ON(1); 1961 break; 1962 } 1963 1964 nv50_outp_acquire(nv_encoder, false); 1965 1966 switch (asyh->or.bpc) { 1967 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; 1968 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; 1969 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; 1970 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; 1971 } 1972 1973 switch (nv_encoder->dcb->type) { 1974 case DCB_OUTPUT_TMDS: 1975 case DCB_OUTPUT_DP: 1976 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1977 break; 1978 default: 1979 BUG(); 1980 break; 1981 } 1982 1983 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh); 1984 nv_encoder->crtc = &nv_crtc->base; 1985 } 1986 1987 static const struct drm_encoder_helper_funcs 1988 nv50_pior_help = { 1989 .atomic_check = nv50_pior_atomic_check, 1990 .atomic_enable = nv50_pior_atomic_enable, 1991 .atomic_disable = nv50_pior_atomic_disable, 1992 }; 1993 1994 static void 1995 nv50_pior_destroy(struct drm_encoder *encoder) 1996 { 1997 drm_encoder_cleanup(encoder); 1998 kfree(encoder); 1999 } 2000 2001 static const struct drm_encoder_funcs 2002 nv50_pior_func = { 2003 .destroy = nv50_pior_destroy, 2004 }; 2005 2006 static int 2007 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 2008 { 2009 struct drm_device *dev = connector->dev; 2010 struct nouveau_drm *drm = nouveau_drm(dev); 2011 struct nv50_disp *disp = nv50_disp(dev); 2012 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 2013 struct nvkm_i2c_bus *bus = NULL; 2014 struct nvkm_i2c_aux *aux = NULL; 2015 struct i2c_adapter *ddc; 2016 struct nouveau_encoder *nv_encoder; 2017 struct drm_encoder *encoder; 2018 int type; 2019 2020 switch (dcbe->type) { 2021 case DCB_OUTPUT_TMDS: 2022 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 2023 ddc = bus ? &bus->i2c : NULL; 2024 type = DRM_MODE_ENCODER_TMDS; 2025 break; 2026 case DCB_OUTPUT_DP: 2027 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 2028 ddc = aux ? &aux->i2c : NULL; 2029 type = DRM_MODE_ENCODER_TMDS; 2030 break; 2031 default: 2032 return -ENODEV; 2033 } 2034 2035 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 2036 if (!nv_encoder) 2037 return -ENOMEM; 2038 nv_encoder->dcb = dcbe; 2039 nv_encoder->i2c = ddc; 2040 nv_encoder->aux = aux; 2041 2042 encoder = to_drm_encoder(nv_encoder); 2043 encoder->possible_crtcs = dcbe->heads; 2044 encoder->possible_clones = 0; 2045 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 2046 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 2047 drm_encoder_helper_add(encoder, &nv50_pior_help); 2048 2049 drm_connector_attach_encoder(connector, encoder); 2050 2051 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 2052 nv50_outp_dump_caps(drm, nv_encoder); 2053 2054 return 0; 2055 } 2056 2057 /****************************************************************************** 2058 * Atomic 2059 *****************************************************************************/ 2060 2061 static void 2062 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 2063 { 2064 struct nouveau_drm *drm = nouveau_drm(state->dev); 2065 struct nv50_disp *disp = nv50_disp(drm->dev); 2066 struct nv50_core *core = disp->core; 2067 struct nv50_mstm *mstm; 2068 struct drm_encoder *encoder; 2069 2070 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 2071 2072 drm_for_each_encoder(encoder, drm->dev) { 2073 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2074 mstm = nouveau_encoder(encoder)->dp.mstm; 2075 if (mstm && mstm->modified) 2076 nv50_mstm_prepare(mstm); 2077 } 2078 } 2079 2080 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 2081 core->func->update(core, interlock, true); 2082 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 2083 disp->core->chan.base.device)) 2084 NV_ERROR(drm, "core notifier timeout\n"); 2085 2086 drm_for_each_encoder(encoder, drm->dev) { 2087 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2088 mstm = nouveau_encoder(encoder)->dp.mstm; 2089 if (mstm && mstm->modified) 2090 nv50_mstm_cleanup(mstm); 2091 } 2092 } 2093 } 2094 2095 static void 2096 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 2097 { 2098 struct drm_plane_state *new_plane_state; 2099 struct drm_plane *plane; 2100 int i; 2101 2102 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2103 struct nv50_wndw *wndw = nv50_wndw(plane); 2104 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 2105 if (wndw->func->update) 2106 wndw->func->update(wndw, interlock); 2107 } 2108 } 2109 } 2110 2111 static void 2112 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 2113 { 2114 struct drm_device *dev = state->dev; 2115 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 2116 struct drm_crtc *crtc; 2117 struct drm_plane_state *new_plane_state; 2118 struct drm_plane *plane; 2119 struct nouveau_drm *drm = nouveau_drm(dev); 2120 struct nv50_disp *disp = nv50_disp(dev); 2121 struct nv50_atom *atom = nv50_atom(state); 2122 struct nv50_core *core = disp->core; 2123 struct nv50_outp_atom *outp, *outt; 2124 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 2125 int i; 2126 bool flushed = false; 2127 2128 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 2129 nv50_crc_atomic_stop_reporting(state); 2130 drm_atomic_helper_wait_for_fences(dev, state, false); 2131 drm_atomic_helper_wait_for_dependencies(state); 2132 drm_atomic_helper_update_legacy_modeset_state(dev, state); 2133 drm_atomic_helper_calc_timestamping_constants(state); 2134 2135 if (atom->lock_core) 2136 mutex_lock(&disp->mutex); 2137 2138 /* Disable head(s). */ 2139 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2140 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2141 struct nv50_head *head = nv50_head(crtc); 2142 2143 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 2144 asyh->clr.mask, asyh->set.mask); 2145 2146 if (old_crtc_state->active && !new_crtc_state->active) { 2147 pm_runtime_put_noidle(dev->dev); 2148 drm_crtc_vblank_off(crtc); 2149 } 2150 2151 if (asyh->clr.mask) { 2152 nv50_head_flush_clr(head, asyh, atom->flush_disable); 2153 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2154 } 2155 } 2156 2157 /* Disable plane(s). */ 2158 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2159 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2160 struct nv50_wndw *wndw = nv50_wndw(plane); 2161 2162 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2163 asyw->clr.mask, asyw->set.mask); 2164 if (!asyw->clr.mask) 2165 continue; 2166 2167 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 2168 } 2169 2170 /* Disable output path(s). */ 2171 list_for_each_entry(outp, &atom->outp, head) { 2172 const struct drm_encoder_helper_funcs *help; 2173 struct drm_encoder *encoder; 2174 2175 encoder = outp->encoder; 2176 help = encoder->helper_private; 2177 2178 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2179 outp->clr.mask, outp->set.mask); 2180 2181 if (outp->clr.mask) { 2182 help->atomic_disable(encoder, state); 2183 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2184 if (outp->flush_disable) { 2185 nv50_disp_atomic_commit_wndw(state, interlock); 2186 nv50_disp_atomic_commit_core(state, interlock); 2187 memset(interlock, 0x00, sizeof(interlock)); 2188 2189 flushed = true; 2190 } 2191 } 2192 } 2193 2194 /* Flush disable. */ 2195 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2196 if (atom->flush_disable) { 2197 nv50_disp_atomic_commit_wndw(state, interlock); 2198 nv50_disp_atomic_commit_core(state, interlock); 2199 memset(interlock, 0x00, sizeof(interlock)); 2200 2201 flushed = true; 2202 } 2203 } 2204 2205 if (flushed) 2206 nv50_crc_atomic_release_notifier_contexts(state); 2207 nv50_crc_atomic_init_notifier_contexts(state); 2208 2209 /* Update output path(s). */ 2210 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2211 const struct drm_encoder_helper_funcs *help; 2212 struct drm_encoder *encoder; 2213 2214 encoder = outp->encoder; 2215 help = encoder->helper_private; 2216 2217 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2218 outp->set.mask, outp->clr.mask); 2219 2220 if (outp->set.mask) { 2221 help->atomic_enable(encoder, state); 2222 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2223 } 2224 2225 list_del(&outp->head); 2226 kfree(outp); 2227 } 2228 2229 /* Update head(s). */ 2230 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2231 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2232 struct nv50_head *head = nv50_head(crtc); 2233 2234 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2235 asyh->set.mask, asyh->clr.mask); 2236 2237 if (asyh->set.mask) { 2238 nv50_head_flush_set(head, asyh); 2239 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2240 } 2241 2242 if (new_crtc_state->active) { 2243 if (!old_crtc_state->active) { 2244 drm_crtc_vblank_on(crtc); 2245 pm_runtime_get_noresume(dev->dev); 2246 } 2247 if (new_crtc_state->event) 2248 drm_crtc_vblank_get(crtc); 2249 } 2250 } 2251 2252 /* Update window->head assignment. 2253 * 2254 * This has to happen in an update that's not interlocked with 2255 * any window channels to avoid hitting HW error checks. 2256 * 2257 *TODO: Proper handling of window ownership (Turing apparently 2258 * supports non-fixed mappings). 2259 */ 2260 if (core->assign_windows) { 2261 core->func->wndw.owner(core); 2262 nv50_disp_atomic_commit_core(state, interlock); 2263 core->assign_windows = false; 2264 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2265 } 2266 2267 /* Update plane(s). */ 2268 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2269 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2270 struct nv50_wndw *wndw = nv50_wndw(plane); 2271 2272 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2273 asyw->set.mask, asyw->clr.mask); 2274 if ( !asyw->set.mask && 2275 (!asyw->clr.mask || atom->flush_disable)) 2276 continue; 2277 2278 nv50_wndw_flush_set(wndw, interlock, asyw); 2279 } 2280 2281 /* Flush update. */ 2282 nv50_disp_atomic_commit_wndw(state, interlock); 2283 2284 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2285 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2286 interlock[NV50_DISP_INTERLOCK_OVLY] || 2287 interlock[NV50_DISP_INTERLOCK_WNDW] || 2288 !atom->state.legacy_cursor_update) 2289 nv50_disp_atomic_commit_core(state, interlock); 2290 else 2291 disp->core->func->update(disp->core, interlock, false); 2292 } 2293 2294 if (atom->lock_core) 2295 mutex_unlock(&disp->mutex); 2296 2297 /* Wait for HW to signal completion. */ 2298 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2299 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2300 struct nv50_wndw *wndw = nv50_wndw(plane); 2301 int ret = nv50_wndw_wait_armed(wndw, asyw); 2302 if (ret) 2303 NV_ERROR(drm, "%s: timeout\n", plane->name); 2304 } 2305 2306 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2307 if (new_crtc_state->event) { 2308 unsigned long flags; 2309 /* Get correct count/ts if racing with vblank irq */ 2310 if (new_crtc_state->active) 2311 drm_crtc_accurate_vblank_count(crtc); 2312 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2313 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2314 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2315 2316 new_crtc_state->event = NULL; 2317 if (new_crtc_state->active) 2318 drm_crtc_vblank_put(crtc); 2319 } 2320 } 2321 2322 nv50_crc_atomic_start_reporting(state); 2323 if (!flushed) 2324 nv50_crc_atomic_release_notifier_contexts(state); 2325 2326 drm_atomic_helper_commit_hw_done(state); 2327 drm_atomic_helper_cleanup_planes(dev, state); 2328 drm_atomic_helper_commit_cleanup_done(state); 2329 drm_atomic_state_put(state); 2330 2331 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2332 pm_runtime_mark_last_busy(dev->dev); 2333 pm_runtime_put_autosuspend(dev->dev); 2334 } 2335 2336 static void 2337 nv50_disp_atomic_commit_work(struct work_struct *work) 2338 { 2339 struct drm_atomic_state *state = 2340 container_of(work, typeof(*state), commit_work); 2341 nv50_disp_atomic_commit_tail(state); 2342 } 2343 2344 static int 2345 nv50_disp_atomic_commit(struct drm_device *dev, 2346 struct drm_atomic_state *state, bool nonblock) 2347 { 2348 struct drm_plane_state *new_plane_state; 2349 struct drm_plane *plane; 2350 int ret, i; 2351 2352 ret = pm_runtime_get_sync(dev->dev); 2353 if (ret < 0 && ret != -EACCES) { 2354 pm_runtime_put_autosuspend(dev->dev); 2355 return ret; 2356 } 2357 2358 ret = drm_atomic_helper_setup_commit(state, nonblock); 2359 if (ret) 2360 goto done; 2361 2362 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2363 2364 ret = drm_atomic_helper_prepare_planes(dev, state); 2365 if (ret) 2366 goto done; 2367 2368 if (!nonblock) { 2369 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2370 if (ret) 2371 goto err_cleanup; 2372 } 2373 2374 ret = drm_atomic_helper_swap_state(state, true); 2375 if (ret) 2376 goto err_cleanup; 2377 2378 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2379 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2380 struct nv50_wndw *wndw = nv50_wndw(plane); 2381 2382 if (asyw->set.image) 2383 nv50_wndw_ntfy_enable(wndw, asyw); 2384 } 2385 2386 drm_atomic_state_get(state); 2387 2388 /* 2389 * Grab another RPM ref for the commit tail, which will release the 2390 * ref when it's finished 2391 */ 2392 pm_runtime_get_noresume(dev->dev); 2393 2394 if (nonblock) 2395 queue_work(system_unbound_wq, &state->commit_work); 2396 else 2397 nv50_disp_atomic_commit_tail(state); 2398 2399 err_cleanup: 2400 if (ret) 2401 drm_atomic_helper_cleanup_planes(dev, state); 2402 done: 2403 pm_runtime_put_autosuspend(dev->dev); 2404 return ret; 2405 } 2406 2407 static struct nv50_outp_atom * 2408 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2409 { 2410 struct nv50_outp_atom *outp; 2411 2412 list_for_each_entry(outp, &atom->outp, head) { 2413 if (outp->encoder == encoder) 2414 return outp; 2415 } 2416 2417 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2418 if (!outp) 2419 return ERR_PTR(-ENOMEM); 2420 2421 list_add(&outp->head, &atom->outp); 2422 outp->encoder = encoder; 2423 return outp; 2424 } 2425 2426 static int 2427 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2428 struct drm_connector_state *old_connector_state) 2429 { 2430 struct drm_encoder *encoder = old_connector_state->best_encoder; 2431 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2432 struct drm_crtc *crtc; 2433 struct nv50_outp_atom *outp; 2434 2435 if (!(crtc = old_connector_state->crtc)) 2436 return 0; 2437 2438 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2439 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2440 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2441 outp = nv50_disp_outp_atomic_add(atom, encoder); 2442 if (IS_ERR(outp)) 2443 return PTR_ERR(outp); 2444 2445 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2446 outp->flush_disable = true; 2447 atom->flush_disable = true; 2448 } 2449 outp->clr.ctrl = true; 2450 atom->lock_core = true; 2451 } 2452 2453 return 0; 2454 } 2455 2456 static int 2457 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2458 struct drm_connector_state *connector_state) 2459 { 2460 struct drm_encoder *encoder = connector_state->best_encoder; 2461 struct drm_crtc_state *new_crtc_state; 2462 struct drm_crtc *crtc; 2463 struct nv50_outp_atom *outp; 2464 2465 if (!(crtc = connector_state->crtc)) 2466 return 0; 2467 2468 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2469 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2470 outp = nv50_disp_outp_atomic_add(atom, encoder); 2471 if (IS_ERR(outp)) 2472 return PTR_ERR(outp); 2473 2474 outp->set.ctrl = true; 2475 atom->lock_core = true; 2476 } 2477 2478 return 0; 2479 } 2480 2481 static int 2482 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2483 { 2484 struct nv50_atom *atom = nv50_atom(state); 2485 struct nv50_core *core = nv50_disp(dev)->core; 2486 struct drm_connector_state *old_connector_state, *new_connector_state; 2487 struct drm_connector *connector; 2488 struct drm_crtc_state *new_crtc_state; 2489 struct drm_crtc *crtc; 2490 struct nv50_head *head; 2491 struct nv50_head_atom *asyh; 2492 int ret, i; 2493 2494 if (core->assign_windows && core->func->head->static_wndw_map) { 2495 drm_for_each_crtc(crtc, dev) { 2496 new_crtc_state = drm_atomic_get_crtc_state(state, 2497 crtc); 2498 if (IS_ERR(new_crtc_state)) 2499 return PTR_ERR(new_crtc_state); 2500 2501 head = nv50_head(crtc); 2502 asyh = nv50_head_atom(new_crtc_state); 2503 core->func->head->static_wndw_map(head, asyh); 2504 } 2505 } 2506 2507 /* We need to handle colour management on a per-plane basis. */ 2508 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2509 if (new_crtc_state->color_mgmt_changed) { 2510 ret = drm_atomic_add_affected_planes(state, crtc); 2511 if (ret) 2512 return ret; 2513 } 2514 } 2515 2516 ret = drm_atomic_helper_check(dev, state); 2517 if (ret) 2518 return ret; 2519 2520 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2521 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2522 if (ret) 2523 return ret; 2524 2525 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2526 if (ret) 2527 return ret; 2528 } 2529 2530 ret = drm_dp_mst_atomic_check(state); 2531 if (ret) 2532 return ret; 2533 2534 nv50_crc_atomic_check_outp(atom); 2535 2536 return 0; 2537 } 2538 2539 static void 2540 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2541 { 2542 struct nv50_atom *atom = nv50_atom(state); 2543 struct nv50_outp_atom *outp, *outt; 2544 2545 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2546 list_del(&outp->head); 2547 kfree(outp); 2548 } 2549 2550 drm_atomic_state_default_clear(state); 2551 } 2552 2553 static void 2554 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2555 { 2556 struct nv50_atom *atom = nv50_atom(state); 2557 drm_atomic_state_default_release(&atom->state); 2558 kfree(atom); 2559 } 2560 2561 static struct drm_atomic_state * 2562 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2563 { 2564 struct nv50_atom *atom; 2565 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2566 drm_atomic_state_init(dev, &atom->state) < 0) { 2567 kfree(atom); 2568 return NULL; 2569 } 2570 INIT_LIST_HEAD(&atom->outp); 2571 return &atom->state; 2572 } 2573 2574 static const struct drm_mode_config_funcs 2575 nv50_disp_func = { 2576 .fb_create = nouveau_user_framebuffer_create, 2577 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2578 .atomic_check = nv50_disp_atomic_check, 2579 .atomic_commit = nv50_disp_atomic_commit, 2580 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2581 .atomic_state_clear = nv50_disp_atomic_state_clear, 2582 .atomic_state_free = nv50_disp_atomic_state_free, 2583 }; 2584 2585 /****************************************************************************** 2586 * Init 2587 *****************************************************************************/ 2588 2589 static void 2590 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend) 2591 { 2592 struct nouveau_drm *drm = nouveau_drm(dev); 2593 struct drm_encoder *encoder; 2594 struct drm_plane *plane; 2595 2596 drm_for_each_plane(plane, dev) { 2597 struct nv50_wndw *wndw = nv50_wndw(plane); 2598 if (plane->funcs != &nv50_wndw) 2599 continue; 2600 nv50_wndw_fini(wndw); 2601 } 2602 2603 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2604 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 2605 nv50_mstm_fini(nouveau_encoder(encoder)); 2606 } 2607 2608 if (!runtime) 2609 cancel_work_sync(&drm->hpd_work); 2610 } 2611 2612 static int 2613 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2614 { 2615 struct nv50_core *core = nv50_disp(dev)->core; 2616 struct drm_encoder *encoder; 2617 struct drm_plane *plane; 2618 2619 if (resume || runtime) 2620 core->func->init(core); 2621 2622 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2623 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2624 struct nouveau_encoder *nv_encoder = 2625 nouveau_encoder(encoder); 2626 nv50_mstm_init(nv_encoder, runtime); 2627 } 2628 } 2629 2630 drm_for_each_plane(plane, dev) { 2631 struct nv50_wndw *wndw = nv50_wndw(plane); 2632 if (plane->funcs != &nv50_wndw) 2633 continue; 2634 nv50_wndw_init(wndw); 2635 } 2636 2637 return 0; 2638 } 2639 2640 static void 2641 nv50_display_destroy(struct drm_device *dev) 2642 { 2643 struct nv50_disp *disp = nv50_disp(dev); 2644 2645 nv50_audio_component_fini(nouveau_drm(dev)); 2646 2647 nvif_object_unmap(&disp->caps); 2648 nvif_object_dtor(&disp->caps); 2649 nv50_core_del(&disp->core); 2650 2651 nouveau_bo_unmap(disp->sync); 2652 if (disp->sync) 2653 nouveau_bo_unpin(disp->sync); 2654 nouveau_bo_ref(NULL, &disp->sync); 2655 2656 nouveau_display(dev)->priv = NULL; 2657 kfree(disp); 2658 } 2659 2660 int 2661 nv50_display_create(struct drm_device *dev) 2662 { 2663 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2664 struct nouveau_drm *drm = nouveau_drm(dev); 2665 struct dcb_table *dcb = &drm->vbios.dcb; 2666 struct drm_connector *connector, *tmp; 2667 struct nv50_disp *disp; 2668 struct dcb_output *dcbe; 2669 int crtcs, ret, i; 2670 bool has_mst = nv50_has_mst(drm); 2671 2672 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2673 if (!disp) 2674 return -ENOMEM; 2675 2676 mutex_init(&disp->mutex); 2677 2678 nouveau_display(dev)->priv = disp; 2679 nouveau_display(dev)->dtor = nv50_display_destroy; 2680 nouveau_display(dev)->init = nv50_display_init; 2681 nouveau_display(dev)->fini = nv50_display_fini; 2682 disp->disp = &nouveau_display(dev)->disp; 2683 dev->mode_config.funcs = &nv50_disp_func; 2684 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2685 dev->mode_config.normalize_zpos = true; 2686 2687 /* small shared memory area we use for notifiers and semaphores */ 2688 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, 2689 NOUVEAU_GEM_DOMAIN_VRAM, 2690 0, 0x0000, NULL, NULL, &disp->sync); 2691 if (!ret) { 2692 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true); 2693 if (!ret) { 2694 ret = nouveau_bo_map(disp->sync); 2695 if (ret) 2696 nouveau_bo_unpin(disp->sync); 2697 } 2698 if (ret) 2699 nouveau_bo_ref(NULL, &disp->sync); 2700 } 2701 2702 if (ret) 2703 goto out; 2704 2705 /* allocate master evo channel */ 2706 ret = nv50_core_new(drm, &disp->core); 2707 if (ret) 2708 goto out; 2709 2710 disp->core->func->init(disp->core); 2711 if (disp->core->func->caps_init) { 2712 ret = disp->core->func->caps_init(drm, disp); 2713 if (ret) 2714 goto out; 2715 } 2716 2717 /* Assign the correct format modifiers */ 2718 if (disp->disp->object.oclass >= TU102_DISP) 2719 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2720 else 2721 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) 2722 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2723 else 2724 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2725 2726 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later 2727 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The 2728 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to 2729 * small page allocations in prepare_fb(). When this is implemented, we should also force 2730 * large pages (128K) for ovly fbs in order to fix Kepler ovlys. 2731 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using 2732 * large pages. 2733 */ 2734 if (disp->disp->object.oclass >= GM107_DISP) { 2735 dev->mode_config.cursor_width = 256; 2736 dev->mode_config.cursor_height = 256; 2737 } else if (disp->disp->object.oclass >= GK104_DISP) { 2738 dev->mode_config.cursor_width = 128; 2739 dev->mode_config.cursor_height = 128; 2740 } else { 2741 dev->mode_config.cursor_width = 64; 2742 dev->mode_config.cursor_height = 64; 2743 } 2744 2745 /* create crtc objects to represent the hw heads */ 2746 if (disp->disp->object.oclass >= GV100_DISP) 2747 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2748 else 2749 if (disp->disp->object.oclass >= GF110_DISP) 2750 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2751 else 2752 crtcs = 0x3; 2753 2754 for (i = 0; i < fls(crtcs); i++) { 2755 struct nv50_head *head; 2756 2757 if (!(crtcs & (1 << i))) 2758 continue; 2759 2760 head = nv50_head_create(dev, i); 2761 if (IS_ERR(head)) { 2762 ret = PTR_ERR(head); 2763 goto out; 2764 } 2765 2766 if (has_mst) { 2767 head->msto = nv50_msto_new(dev, head, i); 2768 if (IS_ERR(head->msto)) { 2769 ret = PTR_ERR(head->msto); 2770 head->msto = NULL; 2771 goto out; 2772 } 2773 2774 /* 2775 * FIXME: This is a hack to workaround the following 2776 * issues: 2777 * 2778 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2779 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2780 * 2781 * Once these issues are closed, this should be 2782 * removed 2783 */ 2784 head->msto->encoder.possible_crtcs = crtcs; 2785 } 2786 } 2787 2788 /* create encoder/connector objects based on VBIOS DCB table */ 2789 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2790 connector = nouveau_connector_create(dev, dcbe); 2791 if (IS_ERR(connector)) 2792 continue; 2793 2794 if (dcbe->location == DCB_LOC_ON_CHIP) { 2795 switch (dcbe->type) { 2796 case DCB_OUTPUT_TMDS: 2797 case DCB_OUTPUT_LVDS: 2798 case DCB_OUTPUT_DP: 2799 ret = nv50_sor_create(connector, dcbe); 2800 break; 2801 case DCB_OUTPUT_ANALOG: 2802 ret = nv50_dac_create(connector, dcbe); 2803 break; 2804 default: 2805 ret = -ENODEV; 2806 break; 2807 } 2808 } else { 2809 ret = nv50_pior_create(connector, dcbe); 2810 } 2811 2812 if (ret) { 2813 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2814 dcbe->location, dcbe->type, 2815 ffs(dcbe->or) - 1, ret); 2816 ret = 0; 2817 } 2818 } 2819 2820 /* cull any connectors we created that don't have an encoder */ 2821 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2822 if (connector->possible_encoders) 2823 continue; 2824 2825 NV_WARN(drm, "%s has no encoders, removing\n", 2826 connector->name); 2827 connector->funcs->destroy(connector); 2828 } 2829 2830 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2831 dev->vblank_disable_immediate = true; 2832 2833 nv50_audio_component_init(drm); 2834 2835 out: 2836 if (ret) 2837 nv50_display_destroy(dev); 2838 return ret; 2839 } 2840 2841 /****************************************************************************** 2842 * Format modifiers 2843 *****************************************************************************/ 2844 2845 /**************************************************************** 2846 * Log2(block height) ----------------------------+ * 2847 * Page Kind ----------------------------------+ | * 2848 * Gob Height/Page Kind Generation ------+ | | * 2849 * Sector layout -------+ | | | * 2850 * Compression ------+ | | | | */ 2851 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2852 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2853 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2854 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2855 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2856 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2857 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2858 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2859 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2860 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2861 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2862 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2863 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2864 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2865 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2866 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2867 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2868 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2869 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2870 DRM_FORMAT_MOD_LINEAR, 2871 DRM_FORMAT_MOD_INVALID 2872 }; 2873 2874 /**************************************************************** 2875 * Log2(block height) ----------------------------+ * 2876 * Page Kind ----------------------------------+ | * 2877 * Gob Height/Page Kind Generation ------+ | | * 2878 * Sector layout -------+ | | | * 2879 * Compression ------+ | | | | */ 2880 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2881 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2882 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2883 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2884 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2885 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2886 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2887 DRM_FORMAT_MOD_LINEAR, 2888 DRM_FORMAT_MOD_INVALID 2889 }; 2890