1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 #include <linux/iopoll.h> 35 36 #include <drm/display/drm_dp_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_fb_helper.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_vblank.h> 44 45 #include <nvif/push507c.h> 46 47 #include <nvif/class.h> 48 #include <nvif/cl0002.h> 49 #include <nvif/event.h> 50 #include <nvif/if0012.h> 51 #include <nvif/if0014.h> 52 #include <nvif/timer.h> 53 54 #include <nvhw/class/cl507c.h> 55 #include <nvhw/class/cl507d.h> 56 #include <nvhw/class/cl837d.h> 57 #include <nvhw/class/cl887d.h> 58 #include <nvhw/class/cl907d.h> 59 #include <nvhw/class/cl917d.h> 60 61 #include "nouveau_drv.h" 62 #include "nouveau_dma.h" 63 #include "nouveau_gem.h" 64 #include "nouveau_connector.h" 65 #include "nouveau_encoder.h" 66 #include "nouveau_fence.h" 67 #include "nv50_display.h" 68 69 #include <subdev/bios/dp.h> 70 71 /****************************************************************************** 72 * EVO channel 73 *****************************************************************************/ 74 75 static int 76 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 77 const s32 *oclass, u8 head, void *data, u32 size, 78 struct nv50_chan *chan) 79 { 80 struct nvif_sclass *sclass; 81 int ret, i, n; 82 83 chan->device = device; 84 85 ret = n = nvif_object_sclass_get(disp, &sclass); 86 if (ret < 0) 87 return ret; 88 89 while (oclass[0]) { 90 for (i = 0; i < n; i++) { 91 if (sclass[i].oclass == oclass[0]) { 92 ret = nvif_object_ctor(disp, "kmsChan", 0, 93 oclass[0], data, size, 94 &chan->user); 95 if (ret == 0) 96 nvif_object_map(&chan->user, NULL, 0); 97 nvif_object_sclass_put(&sclass); 98 return ret; 99 } 100 } 101 oclass++; 102 } 103 104 nvif_object_sclass_put(&sclass); 105 return -ENOSYS; 106 } 107 108 static void 109 nv50_chan_destroy(struct nv50_chan *chan) 110 { 111 nvif_object_dtor(&chan->user); 112 } 113 114 /****************************************************************************** 115 * DMA EVO channel 116 *****************************************************************************/ 117 118 void 119 nv50_dmac_destroy(struct nv50_dmac *dmac) 120 { 121 nvif_object_dtor(&dmac->vram); 122 nvif_object_dtor(&dmac->sync); 123 124 nv50_chan_destroy(&dmac->base); 125 126 nvif_mem_dtor(&dmac->_push.mem); 127 } 128 129 static void 130 nv50_dmac_kick(struct nvif_push *push) 131 { 132 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 133 134 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr; 135 if (dmac->put != dmac->cur) { 136 /* Push buffer fetches are not coherent with BAR1, we need to ensure 137 * writes have been flushed right through to VRAM before writing PUT. 138 */ 139 if (dmac->push->mem.type & NVIF_MEM_VRAM) { 140 struct nvif_device *device = dmac->base.device; 141 nvif_wr32(&device->object, 0x070000, 0x00000001); 142 nvif_msec(device, 2000, 143 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 144 break; 145 ); 146 } 147 148 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); 149 dmac->put = dmac->cur; 150 } 151 152 push->bgn = push->cur; 153 } 154 155 static int 156 nv50_dmac_free(struct nv50_dmac *dmac) 157 { 158 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 159 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ 160 return get - dmac->cur - 5; 161 return dmac->max - dmac->cur; 162 } 163 164 static int 165 nv50_dmac_wind(struct nv50_dmac *dmac) 166 { 167 /* Wait for GET to depart from the beginning of the push buffer to 168 * prevent writing PUT == GET, which would be ignored by HW. 169 */ 170 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 171 if (get == 0) { 172 /* Corner-case, HW idle, but non-committed work pending. */ 173 if (dmac->put == 0) 174 nv50_dmac_kick(dmac->push); 175 176 if (nvif_msec(dmac->base.device, 2000, 177 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) 178 break; 179 ) < 0) 180 return -ETIMEDOUT; 181 } 182 183 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); 184 dmac->cur = 0; 185 return 0; 186 } 187 188 static int 189 nv50_dmac_wait(struct nvif_push *push, u32 size) 190 { 191 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 192 int free; 193 194 if (WARN_ON(size > dmac->max)) 195 return -EINVAL; 196 197 dmac->cur = push->cur - (u32 __iomem *)dmac->_push.mem.object.map.ptr; 198 if (dmac->cur + size >= dmac->max) { 199 int ret = nv50_dmac_wind(dmac); 200 if (ret) 201 return ret; 202 203 push->cur = dmac->_push.mem.object.map.ptr; 204 push->cur = push->cur + dmac->cur; 205 nv50_dmac_kick(push); 206 } 207 208 if (nvif_msec(dmac->base.device, 2000, 209 if ((free = nv50_dmac_free(dmac)) >= size) 210 break; 211 ) < 0) { 212 WARN_ON(1); 213 return -ETIMEDOUT; 214 } 215 216 push->bgn = dmac->_push.mem.object.map.ptr; 217 push->bgn = push->bgn + dmac->cur; 218 push->cur = push->bgn; 219 push->end = push->cur + free; 220 return 0; 221 } 222 223 MODULE_PARM_DESC(kms_vram_pushbuf, "Place EVO/NVD push buffers in VRAM (default: auto)"); 224 static int nv50_dmac_vram_pushbuf = -1; 225 module_param_named(kms_vram_pushbuf, nv50_dmac_vram_pushbuf, int, 0400); 226 227 int 228 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 229 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf, 230 struct nv50_dmac *dmac) 231 { 232 struct nouveau_cli *cli = (void *)device->object.client; 233 struct nvif_disp_chan_v0 *args = data; 234 u8 type = NVIF_MEM_COHERENT; 235 int ret; 236 237 mutex_init(&dmac->lock); 238 239 /* Pascal added support for 47-bit physical addresses, but some 240 * parts of EVO still only accept 40-bit PAs. 241 * 242 * To avoid issues on systems with large amounts of RAM, and on 243 * systems where an IOMMU maps pages at a high address, we need 244 * to allocate push buffers in VRAM instead. 245 * 246 * This appears to match NVIDIA's behaviour on Pascal. 247 */ 248 if ((nv50_dmac_vram_pushbuf > 0) || 249 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL)) 250 type |= NVIF_MEM_VRAM; 251 252 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, 253 &dmac->_push.mem); 254 if (ret) 255 return ret; 256 257 dmac->ptr = dmac->_push.mem.object.map.ptr; 258 dmac->_push.wait = nv50_dmac_wait; 259 dmac->_push.kick = nv50_dmac_kick; 260 dmac->push = &dmac->_push; 261 dmac->push->bgn = dmac->_push.mem.object.map.ptr; 262 dmac->push->cur = dmac->push->bgn; 263 dmac->push->end = dmac->push->bgn; 264 dmac->max = 0x1000/4 - 1; 265 266 /* EVO channels are affected by a HW bug where the last 12 DWORDs 267 * of the push buffer aren't able to be used safely. 268 */ 269 if (disp->oclass < GV100_DISP) 270 dmac->max -= 12; 271 272 args->pushbuf = nvif_handle(&dmac->_push.mem.object); 273 274 ret = nv50_chan_create(device, disp, oclass, head, data, size, 275 &dmac->base); 276 if (ret) 277 return ret; 278 279 if (syncbuf < 0) 280 return 0; 281 282 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, 283 NV_DMA_IN_MEMORY, 284 &(struct nv_dma_v0) { 285 .target = NV_DMA_V0_TARGET_VRAM, 286 .access = NV_DMA_V0_ACCESS_RDWR, 287 .start = syncbuf + 0x0000, 288 .limit = syncbuf + 0x0fff, 289 }, sizeof(struct nv_dma_v0), 290 &dmac->sync); 291 if (ret) 292 return ret; 293 294 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, 295 NV_DMA_IN_MEMORY, 296 &(struct nv_dma_v0) { 297 .target = NV_DMA_V0_TARGET_VRAM, 298 .access = NV_DMA_V0_ACCESS_RDWR, 299 .start = 0, 300 .limit = device->info.ram_user - 1, 301 }, sizeof(struct nv_dma_v0), 302 &dmac->vram); 303 if (ret) 304 return ret; 305 306 return ret; 307 } 308 309 /****************************************************************************** 310 * Output path helpers 311 *****************************************************************************/ 312 static void 313 nv50_outp_dump_caps(struct nouveau_drm *drm, 314 struct nouveau_encoder *outp) 315 { 316 NV_DEBUG(drm, "%s caps: dp_interlace=%d\n", 317 outp->base.base.name, outp->caps.dp_interlace); 318 } 319 320 static int 321 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 322 struct drm_crtc_state *crtc_state, 323 struct drm_connector_state *conn_state, 324 struct drm_display_mode *native_mode) 325 { 326 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 327 struct drm_display_mode *mode = &crtc_state->mode; 328 struct drm_connector *connector = conn_state->connector; 329 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 330 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 331 332 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 333 asyc->scaler.full = false; 334 if (!native_mode) 335 return 0; 336 337 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 338 switch (connector->connector_type) { 339 case DRM_MODE_CONNECTOR_LVDS: 340 case DRM_MODE_CONNECTOR_eDP: 341 /* Don't force scaler for EDID modes with 342 * same size as the native one (e.g. different 343 * refresh rate) 344 */ 345 if (mode->hdisplay == native_mode->hdisplay && 346 mode->vdisplay == native_mode->vdisplay && 347 mode->type & DRM_MODE_TYPE_DRIVER) 348 break; 349 mode = native_mode; 350 asyc->scaler.full = true; 351 break; 352 default: 353 break; 354 } 355 } else { 356 mode = native_mode; 357 } 358 359 if (!drm_mode_equal(adjusted_mode, mode)) { 360 drm_mode_copy(adjusted_mode, mode); 361 crtc_state->mode_changed = true; 362 } 363 364 return 0; 365 } 366 367 static void 368 nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state) 369 { 370 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 371 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 372 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 373 unsigned int max_rate, mode_rate; 374 375 switch (nv_encoder->dcb->type) { 376 case DCB_OUTPUT_DP: 377 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw; 378 379 /* we don't support more than 10 anyway */ 380 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10); 381 382 /* reduce the bpc until it works out */ 383 while (asyh->or.bpc > 6) { 384 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8); 385 if (mode_rate <= max_rate) 386 break; 387 388 asyh->or.bpc -= 2; 389 } 390 break; 391 default: 392 break; 393 } 394 } 395 396 static int 397 nv50_outp_atomic_check(struct drm_encoder *encoder, 398 struct drm_crtc_state *crtc_state, 399 struct drm_connector_state *conn_state) 400 { 401 struct drm_connector *connector = conn_state->connector; 402 struct nouveau_connector *nv_connector = nouveau_connector(connector); 403 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 404 int ret; 405 406 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 407 nv_connector->native_mode); 408 if (ret) 409 return ret; 410 411 if (crtc_state->mode_changed || crtc_state->connectors_changed) 412 asyh->or.bpc = connector->display_info.bpc; 413 414 /* We might have to reduce the bpc */ 415 nv50_outp_atomic_fix_depth(encoder, crtc_state); 416 417 return 0; 418 } 419 420 struct nouveau_connector * 421 nv50_outp_get_new_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 422 { 423 struct drm_connector *connector; 424 struct drm_connector_state *connector_state; 425 struct drm_encoder *encoder = to_drm_encoder(outp); 426 int i; 427 428 for_each_new_connector_in_state(state, connector, connector_state, i) { 429 if (connector_state->best_encoder == encoder) 430 return nouveau_connector(connector); 431 } 432 433 return NULL; 434 } 435 436 struct nouveau_connector * 437 nv50_outp_get_old_connector(struct drm_atomic_state *state, struct nouveau_encoder *outp) 438 { 439 struct drm_connector *connector; 440 struct drm_connector_state *connector_state; 441 struct drm_encoder *encoder = to_drm_encoder(outp); 442 int i; 443 444 for_each_old_connector_in_state(state, connector, connector_state, i) { 445 if (connector_state->best_encoder == encoder) 446 return nouveau_connector(connector); 447 } 448 449 return NULL; 450 } 451 452 static struct nouveau_crtc * 453 nv50_outp_get_new_crtc(const struct drm_atomic_state *state, const struct nouveau_encoder *outp) 454 { 455 struct drm_crtc *crtc; 456 struct drm_crtc_state *crtc_state; 457 const u32 mask = drm_encoder_mask(&outp->base.base); 458 int i; 459 460 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 461 if (crtc_state->encoder_mask & mask) 462 return nouveau_crtc(crtc); 463 } 464 465 return NULL; 466 } 467 468 /****************************************************************************** 469 * DAC 470 *****************************************************************************/ 471 static void 472 nv50_dac_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 473 { 474 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 475 struct nv50_core *core = nv50_disp(encoder->dev)->core; 476 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); 477 478 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL); 479 nv_encoder->crtc = NULL; 480 nvif_outp_release(&nv_encoder->outp); 481 } 482 483 static void 484 nv50_dac_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 485 { 486 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 487 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 488 struct nv50_head_atom *asyh = 489 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 490 struct nv50_core *core = nv50_disp(encoder->dev)->core; 491 u32 ctrl = 0; 492 493 switch (nv_crtc->index) { 494 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; 495 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; 496 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; 497 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; 498 default: 499 WARN_ON(1); 500 break; 501 } 502 503 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); 504 505 nvif_outp_acquire_rgb_crt(&nv_encoder->outp); 506 507 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh); 508 asyh->or.depth = 0; 509 510 nv_encoder->crtc = &nv_crtc->base; 511 } 512 513 static enum drm_connector_status 514 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 515 { 516 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 517 u32 loadval; 518 int ret; 519 520 loadval = nouveau_drm(encoder->dev)->vbios.dactestval; 521 if (loadval == 0) 522 loadval = 340; 523 524 ret = nvif_outp_load_detect(&nv_encoder->outp, loadval); 525 if (ret <= 0) 526 return connector_status_disconnected; 527 528 return connector_status_connected; 529 } 530 531 static const struct drm_encoder_helper_funcs 532 nv50_dac_help = { 533 .atomic_check = nv50_outp_atomic_check, 534 .atomic_enable = nv50_dac_atomic_enable, 535 .atomic_disable = nv50_dac_atomic_disable, 536 .detect = nv50_dac_detect 537 }; 538 539 static void 540 nv50_dac_destroy(struct drm_encoder *encoder) 541 { 542 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 543 544 nvif_outp_dtor(&nv_encoder->outp); 545 546 drm_encoder_cleanup(encoder); 547 kfree(encoder); 548 } 549 550 static const struct drm_encoder_funcs 551 nv50_dac_func = { 552 .destroy = nv50_dac_destroy, 553 }; 554 555 static int 556 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 557 { 558 struct nouveau_drm *drm = nouveau_drm(connector->dev); 559 struct nv50_disp *disp = nv50_disp(connector->dev); 560 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 561 struct nvkm_i2c_bus *bus; 562 struct nouveau_encoder *nv_encoder; 563 struct drm_encoder *encoder; 564 int type = DRM_MODE_ENCODER_DAC; 565 566 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 567 if (!nv_encoder) 568 return -ENOMEM; 569 nv_encoder->dcb = dcbe; 570 571 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 572 if (bus) 573 nv_encoder->i2c = &bus->i2c; 574 575 encoder = to_drm_encoder(nv_encoder); 576 encoder->possible_crtcs = dcbe->heads; 577 encoder->possible_clones = 0; 578 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 579 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 580 drm_encoder_helper_add(encoder, &nv50_dac_help); 581 582 drm_connector_attach_encoder(connector, encoder); 583 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 584 } 585 586 /* 587 * audio component binding for ELD notification 588 */ 589 static void 590 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 591 int dev_id) 592 { 593 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 594 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 595 port, dev_id); 596 } 597 598 static int 599 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 600 bool *enabled, unsigned char *buf, int max_bytes) 601 { 602 struct drm_device *drm_dev = dev_get_drvdata(kdev); 603 struct nouveau_drm *drm = nouveau_drm(drm_dev); 604 struct drm_encoder *encoder; 605 struct nouveau_encoder *nv_encoder; 606 struct nouveau_crtc *nv_crtc; 607 int ret = 0; 608 609 *enabled = false; 610 611 mutex_lock(&drm->audio.lock); 612 613 drm_for_each_encoder(encoder, drm->dev) { 614 struct nouveau_connector *nv_connector = NULL; 615 616 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) 617 continue; /* TODO */ 618 619 nv_encoder = nouveau_encoder(encoder); 620 nv_connector = nouveau_connector(nv_encoder->audio.connector); 621 nv_crtc = nouveau_crtc(nv_encoder->crtc); 622 623 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id) 624 continue; 625 626 *enabled = nv_encoder->audio.enabled; 627 if (*enabled) { 628 ret = drm_eld_size(nv_connector->base.eld); 629 memcpy(buf, nv_connector->base.eld, 630 min(max_bytes, ret)); 631 } 632 break; 633 } 634 635 mutex_unlock(&drm->audio.lock); 636 637 return ret; 638 } 639 640 static const struct drm_audio_component_ops nv50_audio_component_ops = { 641 .get_eld = nv50_audio_component_get_eld, 642 }; 643 644 static int 645 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 646 void *data) 647 { 648 struct drm_device *drm_dev = dev_get_drvdata(kdev); 649 struct nouveau_drm *drm = nouveau_drm(drm_dev); 650 struct drm_audio_component *acomp = data; 651 652 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 653 return -ENOMEM; 654 655 drm_modeset_lock_all(drm_dev); 656 acomp->ops = &nv50_audio_component_ops; 657 acomp->dev = kdev; 658 drm->audio.component = acomp; 659 drm_modeset_unlock_all(drm_dev); 660 return 0; 661 } 662 663 static void 664 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 665 void *data) 666 { 667 struct drm_device *drm_dev = dev_get_drvdata(kdev); 668 struct nouveau_drm *drm = nouveau_drm(drm_dev); 669 struct drm_audio_component *acomp = data; 670 671 drm_modeset_lock_all(drm_dev); 672 drm->audio.component = NULL; 673 acomp->ops = NULL; 674 acomp->dev = NULL; 675 drm_modeset_unlock_all(drm_dev); 676 } 677 678 static const struct component_ops nv50_audio_component_bind_ops = { 679 .bind = nv50_audio_component_bind, 680 .unbind = nv50_audio_component_unbind, 681 }; 682 683 static void 684 nv50_audio_component_init(struct nouveau_drm *drm) 685 { 686 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 687 return; 688 689 drm->audio.component_registered = true; 690 mutex_init(&drm->audio.lock); 691 } 692 693 static void 694 nv50_audio_component_fini(struct nouveau_drm *drm) 695 { 696 if (!drm->audio.component_registered) 697 return; 698 699 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 700 drm->audio.component_registered = false; 701 mutex_destroy(&drm->audio.lock); 702 } 703 704 /****************************************************************************** 705 * Audio 706 *****************************************************************************/ 707 static bool 708 nv50_audio_supported(struct drm_encoder *encoder) 709 { 710 struct nv50_disp *disp = nv50_disp(encoder->dev); 711 712 if (disp->disp->object.oclass <= GT200_DISP || 713 disp->disp->object.oclass == GT206_DISP) 714 return false; 715 716 return true; 717 } 718 719 static void 720 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 721 { 722 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 723 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 724 struct nvif_outp *outp = &nv_encoder->outp; 725 726 if (!nv50_audio_supported(encoder)) 727 return; 728 729 mutex_lock(&drm->audio.lock); 730 if (nv_encoder->audio.enabled) { 731 nv_encoder->audio.enabled = false; 732 nv_encoder->audio.connector = NULL; 733 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0); 734 } 735 mutex_unlock(&drm->audio.lock); 736 737 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index); 738 } 739 740 static void 741 nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 742 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 743 struct drm_display_mode *mode) 744 { 745 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 746 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 747 struct nvif_outp *outp = &nv_encoder->outp; 748 749 if (!nv50_audio_supported(encoder) || !drm_detect_monitor_audio(nv_connector->edid)) 750 return; 751 752 mutex_lock(&drm->audio.lock); 753 754 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, nv_connector->base.eld, 755 drm_eld_size(nv_connector->base.eld)); 756 nv_encoder->audio.enabled = true; 757 nv_encoder->audio.connector = &nv_connector->base; 758 759 mutex_unlock(&drm->audio.lock); 760 761 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index); 762 } 763 764 /****************************************************************************** 765 * HDMI 766 *****************************************************************************/ 767 static void 768 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc, 769 struct nouveau_connector *nv_connector, struct drm_atomic_state *state, 770 struct drm_display_mode *mode, bool hda) 771 { 772 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 773 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 774 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi; 775 union hdmi_infoframe infoframe = { 0 }; 776 const u8 rekey = 56; /* binary driver, and tegra, constant */ 777 u8 scdc = 0; 778 u32 max_ac_packet; 779 struct { 780 struct nvif_outp_infoframe_v0 infoframe; 781 u8 data[17]; 782 } args = { 0 }; 783 int ret, size; 784 785 max_ac_packet = mode->htotal - mode->hdisplay; 786 max_ac_packet -= rekey; 787 max_ac_packet -= 18; /* constant from tegra */ 788 max_ac_packet /= 32; 789 790 if (hdmi->scdc.scrambling.supported) { 791 const bool high_tmds_clock_ratio = mode->clock > 340000; 792 793 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc); 794 if (ret < 0) { 795 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 796 return; 797 } 798 799 scdc &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 800 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates) 801 scdc |= SCDC_SCRAMBLING_ENABLE; 802 if (high_tmds_clock_ratio) 803 scdc |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40; 804 805 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, scdc); 806 if (ret < 0) 807 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 808 scdc, ret); 809 } 810 811 ret = nvif_outp_acquire_tmds(&nv_encoder->outp, nv_crtc->index, true, 812 max_ac_packet, rekey, scdc, hda); 813 if (ret) 814 return; 815 816 /* AVI InfoFrame. */ 817 args.infoframe.version = 0; 818 args.infoframe.head = nv_crtc->index; 819 820 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) { 821 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode, 822 HDMI_QUANTIZATION_RANGE_FULL); 823 824 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data)); 825 } else { 826 size = 0; 827 } 828 829 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, &args.infoframe, size); 830 831 /* Vendor InfoFrame. */ 832 memset(&args.data, 0, sizeof(args.data)); 833 if (!drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi, 834 &nv_connector->base, mode)) 835 size = hdmi_infoframe_pack(&infoframe, args.data, ARRAY_SIZE(args.data)); 836 else 837 size = 0; 838 839 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, &args.infoframe, size); 840 841 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 842 } 843 844 /****************************************************************************** 845 * MST 846 *****************************************************************************/ 847 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 848 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 849 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 850 851 struct nv50_mstc { 852 struct nv50_mstm *mstm; 853 struct drm_dp_mst_port *port; 854 struct drm_connector connector; 855 856 struct drm_display_mode *native; 857 struct edid *edid; 858 }; 859 860 struct nv50_msto { 861 struct drm_encoder encoder; 862 863 /* head is statically assigned on msto creation */ 864 struct nv50_head *head; 865 struct nv50_mstc *mstc; 866 bool disabled; 867 bool enabled; 868 }; 869 870 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 871 { 872 struct nv50_msto *msto; 873 874 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 875 return nouveau_encoder(encoder); 876 877 msto = nv50_msto(encoder); 878 if (!msto->mstc) 879 return NULL; 880 return msto->mstc->mstm->outp; 881 } 882 883 static void 884 nv50_msto_cleanup(struct drm_atomic_state *state, 885 struct drm_dp_mst_topology_state *mst_state, 886 struct drm_dp_mst_topology_mgr *mgr, 887 struct nv50_msto *msto) 888 { 889 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 890 struct drm_dp_mst_atomic_payload *payload = 891 drm_atomic_get_mst_payload_state(mst_state, msto->mstc->port); 892 893 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 894 895 if (msto->disabled) { 896 msto->mstc = NULL; 897 msto->disabled = false; 898 } else if (msto->enabled) { 899 drm_dp_add_payload_part2(mgr, state, payload); 900 msto->enabled = false; 901 } 902 } 903 904 static void 905 nv50_msto_prepare(struct drm_atomic_state *state, 906 struct drm_dp_mst_topology_state *mst_state, 907 struct drm_dp_mst_topology_mgr *mgr, 908 struct nv50_msto *msto) 909 { 910 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 911 struct nv50_mstc *mstc = msto->mstc; 912 struct nv50_mstm *mstm = mstc->mstm; 913 struct drm_dp_mst_atomic_payload *payload; 914 915 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 916 917 payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port); 918 919 // TODO: Figure out if we want to do a better job of handling VCPI allocation failures here? 920 if (msto->disabled) { 921 drm_dp_remove_payload(mgr, mst_state, payload, payload); 922 923 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0); 924 } else { 925 if (msto->enabled) 926 drm_dp_add_payload_part1(mgr, mst_state, payload); 927 928 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 929 payload->vc_start_slot, payload->time_slots, 930 payload->pbn, payload->time_slots * mst_state->pbn_div); 931 } 932 } 933 934 static int 935 nv50_msto_atomic_check(struct drm_encoder *encoder, 936 struct drm_crtc_state *crtc_state, 937 struct drm_connector_state *conn_state) 938 { 939 struct drm_atomic_state *state = crtc_state->state; 940 struct drm_connector *connector = conn_state->connector; 941 struct drm_dp_mst_topology_state *mst_state; 942 struct nv50_mstc *mstc = nv50_mstc(connector); 943 struct nv50_mstm *mstm = mstc->mstm; 944 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 945 int slots; 946 int ret; 947 948 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 949 mstc->native); 950 if (ret) 951 return ret; 952 953 if (!drm_atomic_crtc_needs_modeset(crtc_state)) 954 return 0; 955 956 /* 957 * When restoring duplicated states, we need to make sure that the bw 958 * remains the same and avoid recalculating it, as the connector's bpc 959 * may have changed after the state was duplicated 960 */ 961 if (!state->duplicated) { 962 const int clock = crtc_state->adjusted_mode.clock; 963 964 asyh->or.bpc = connector->display_info.bpc; 965 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 966 false); 967 } 968 969 mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr); 970 if (IS_ERR(mst_state)) 971 return PTR_ERR(mst_state); 972 973 if (!mst_state->pbn_div) { 974 struct nouveau_encoder *outp = mstc->mstm->outp; 975 976 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&mstm->mgr, 977 outp->dp.link_bw, outp->dp.link_nr); 978 } 979 980 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn); 981 if (slots < 0) 982 return slots; 983 984 asyh->dp.tu = slots; 985 986 return 0; 987 } 988 989 static u8 990 nv50_dp_bpc_to_depth(unsigned int bpc) 991 { 992 switch (bpc) { 993 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; 994 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; 995 case 10: 996 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; 997 } 998 } 999 1000 static void 1001 nv50_msto_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1002 { 1003 struct nv50_msto *msto = nv50_msto(encoder); 1004 struct nv50_head *head = msto->head; 1005 struct nv50_head_atom *asyh = 1006 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base)); 1007 struct nv50_mstc *mstc = NULL; 1008 struct nv50_mstm *mstm = NULL; 1009 struct drm_connector *connector; 1010 struct drm_connector_list_iter conn_iter; 1011 u8 proto; 1012 1013 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 1014 drm_for_each_connector_iter(connector, &conn_iter) { 1015 if (connector->state->best_encoder == &msto->encoder) { 1016 mstc = nv50_mstc(connector); 1017 mstm = mstc->mstm; 1018 break; 1019 } 1020 } 1021 drm_connector_list_iter_end(&conn_iter); 1022 1023 if (WARN_ON(!mstc)) 1024 return; 1025 1026 if (!mstm->links++) { 1027 /*XXX: MST audio. */ 1028 nvif_outp_acquire_dp(&mstm->outp->outp, mstm->outp->dp.dpcd, 0, 0, false, true); 1029 } 1030 1031 if (mstm->outp->outp.or.link & 1) 1032 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1033 else 1034 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1035 1036 mstm->outp->update(mstm->outp, head->base.index, asyh, proto, 1037 nv50_dp_bpc_to_depth(asyh->or.bpc)); 1038 1039 msto->mstc = mstc; 1040 msto->enabled = true; 1041 mstm->modified = true; 1042 } 1043 1044 static void 1045 nv50_msto_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1046 { 1047 struct nv50_msto *msto = nv50_msto(encoder); 1048 struct nv50_mstc *mstc = msto->mstc; 1049 struct nv50_mstm *mstm = mstc->mstm; 1050 1051 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 1052 mstm->modified = true; 1053 if (!--mstm->links) 1054 mstm->disabled = true; 1055 msto->disabled = true; 1056 } 1057 1058 static const struct drm_encoder_helper_funcs 1059 nv50_msto_help = { 1060 .atomic_disable = nv50_msto_atomic_disable, 1061 .atomic_enable = nv50_msto_atomic_enable, 1062 .atomic_check = nv50_msto_atomic_check, 1063 }; 1064 1065 static void 1066 nv50_msto_destroy(struct drm_encoder *encoder) 1067 { 1068 struct nv50_msto *msto = nv50_msto(encoder); 1069 drm_encoder_cleanup(&msto->encoder); 1070 kfree(msto); 1071 } 1072 1073 static const struct drm_encoder_funcs 1074 nv50_msto = { 1075 .destroy = nv50_msto_destroy, 1076 }; 1077 1078 static struct nv50_msto * 1079 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1080 { 1081 struct nv50_msto *msto; 1082 int ret; 1083 1084 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1085 if (!msto) 1086 return ERR_PTR(-ENOMEM); 1087 1088 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1089 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1090 if (ret) { 1091 kfree(msto); 1092 return ERR_PTR(ret); 1093 } 1094 1095 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1096 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1097 msto->head = head; 1098 return msto; 1099 } 1100 1101 static struct drm_encoder * 1102 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1103 struct drm_atomic_state *state) 1104 { 1105 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 1106 connector); 1107 struct nv50_mstc *mstc = nv50_mstc(connector); 1108 struct drm_crtc *crtc = connector_state->crtc; 1109 1110 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1111 return NULL; 1112 1113 return &nv50_head(crtc)->msto->encoder; 1114 } 1115 1116 static enum drm_mode_status 1117 nv50_mstc_mode_valid(struct drm_connector *connector, 1118 struct drm_display_mode *mode) 1119 { 1120 struct nv50_mstc *mstc = nv50_mstc(connector); 1121 struct nouveau_encoder *outp = mstc->mstm->outp; 1122 1123 /* TODO: calculate the PBN from the dotclock and validate against the 1124 * MSTB's max possible PBN 1125 */ 1126 1127 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1128 } 1129 1130 static int 1131 nv50_mstc_get_modes(struct drm_connector *connector) 1132 { 1133 struct nv50_mstc *mstc = nv50_mstc(connector); 1134 int ret = 0; 1135 1136 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1137 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1138 if (mstc->edid) 1139 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1140 1141 /* 1142 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1143 * to 8 to save bandwidth on the topology. In the future, we'll want 1144 * to properly fix this by dynamically selecting the highest possible 1145 * bpc that would fit in the topology 1146 */ 1147 if (connector->display_info.bpc) 1148 connector->display_info.bpc = 1149 clamp(connector->display_info.bpc, 6U, 8U); 1150 else 1151 connector->display_info.bpc = 8; 1152 1153 if (mstc->native) 1154 drm_mode_destroy(mstc->connector.dev, mstc->native); 1155 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1156 return ret; 1157 } 1158 1159 static int 1160 nv50_mstc_atomic_check(struct drm_connector *connector, 1161 struct drm_atomic_state *state) 1162 { 1163 struct nv50_mstc *mstc = nv50_mstc(connector); 1164 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1165 1166 return drm_dp_atomic_release_time_slots(state, mgr, mstc->port); 1167 } 1168 1169 static int 1170 nv50_mstc_detect(struct drm_connector *connector, 1171 struct drm_modeset_acquire_ctx *ctx, bool force) 1172 { 1173 struct nv50_mstc *mstc = nv50_mstc(connector); 1174 int ret; 1175 1176 if (drm_connector_is_unregistered(connector)) 1177 return connector_status_disconnected; 1178 1179 ret = pm_runtime_get_sync(connector->dev->dev); 1180 if (ret < 0 && ret != -EACCES) { 1181 pm_runtime_put_autosuspend(connector->dev->dev); 1182 return connector_status_disconnected; 1183 } 1184 1185 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1186 mstc->port); 1187 if (ret != connector_status_connected) 1188 goto out; 1189 1190 out: 1191 pm_runtime_mark_last_busy(connector->dev->dev); 1192 pm_runtime_put_autosuspend(connector->dev->dev); 1193 return ret; 1194 } 1195 1196 static const struct drm_connector_helper_funcs 1197 nv50_mstc_help = { 1198 .get_modes = nv50_mstc_get_modes, 1199 .mode_valid = nv50_mstc_mode_valid, 1200 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1201 .atomic_check = nv50_mstc_atomic_check, 1202 .detect_ctx = nv50_mstc_detect, 1203 }; 1204 1205 static void 1206 nv50_mstc_destroy(struct drm_connector *connector) 1207 { 1208 struct nv50_mstc *mstc = nv50_mstc(connector); 1209 1210 drm_connector_cleanup(&mstc->connector); 1211 drm_dp_mst_put_port_malloc(mstc->port); 1212 1213 kfree(mstc); 1214 } 1215 1216 static const struct drm_connector_funcs 1217 nv50_mstc = { 1218 .reset = nouveau_conn_reset, 1219 .fill_modes = drm_helper_probe_single_connector_modes, 1220 .destroy = nv50_mstc_destroy, 1221 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1222 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1223 .atomic_set_property = nouveau_conn_atomic_set_property, 1224 .atomic_get_property = nouveau_conn_atomic_get_property, 1225 }; 1226 1227 static int 1228 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1229 const char *path, struct nv50_mstc **pmstc) 1230 { 1231 struct drm_device *dev = mstm->outp->base.base.dev; 1232 struct drm_crtc *crtc; 1233 struct nv50_mstc *mstc; 1234 int ret; 1235 1236 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1237 return -ENOMEM; 1238 mstc->mstm = mstm; 1239 mstc->port = port; 1240 1241 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1242 DRM_MODE_CONNECTOR_DisplayPort); 1243 if (ret) { 1244 kfree(*pmstc); 1245 *pmstc = NULL; 1246 return ret; 1247 } 1248 1249 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1250 1251 mstc->connector.funcs->reset(&mstc->connector); 1252 nouveau_conn_attach_properties(&mstc->connector); 1253 1254 drm_for_each_crtc(crtc, dev) { 1255 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1256 continue; 1257 1258 drm_connector_attach_encoder(&mstc->connector, 1259 &nv50_head(crtc)->msto->encoder); 1260 } 1261 1262 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1263 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1264 drm_connector_set_path_property(&mstc->connector, path); 1265 drm_dp_mst_get_port_malloc(port); 1266 return 0; 1267 } 1268 1269 static void 1270 nv50_mstm_cleanup(struct drm_atomic_state *state, 1271 struct drm_dp_mst_topology_state *mst_state, 1272 struct nv50_mstm *mstm) 1273 { 1274 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1275 struct drm_encoder *encoder; 1276 1277 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1278 drm_dp_check_act_status(&mstm->mgr); 1279 1280 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1281 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1282 struct nv50_msto *msto = nv50_msto(encoder); 1283 struct nv50_mstc *mstc = msto->mstc; 1284 if (mstc && mstc->mstm == mstm) 1285 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto); 1286 } 1287 } 1288 1289 mstm->modified = false; 1290 } 1291 1292 static void 1293 nv50_mstm_prepare(struct drm_atomic_state *state, 1294 struct drm_dp_mst_topology_state *mst_state, 1295 struct nv50_mstm *mstm) 1296 { 1297 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1298 struct drm_encoder *encoder; 1299 1300 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1301 1302 /* Disable payloads first */ 1303 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1304 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1305 struct nv50_msto *msto = nv50_msto(encoder); 1306 struct nv50_mstc *mstc = msto->mstc; 1307 if (mstc && mstc->mstm == mstm && msto->disabled) 1308 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto); 1309 } 1310 } 1311 1312 /* Add payloads for new heads, while also updating the start slots of any unmodified (but 1313 * active) heads that may have had their VC slots shifted left after the previous step 1314 */ 1315 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1316 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1317 struct nv50_msto *msto = nv50_msto(encoder); 1318 struct nv50_mstc *mstc = msto->mstc; 1319 if (mstc && mstc->mstm == mstm && !msto->disabled) 1320 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto); 1321 } 1322 } 1323 1324 if (mstm->disabled) { 1325 if (!mstm->links) 1326 nvif_outp_release(&mstm->outp->outp); 1327 mstm->disabled = false; 1328 } 1329 } 1330 1331 static struct drm_connector * 1332 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1333 struct drm_dp_mst_port *port, const char *path) 1334 { 1335 struct nv50_mstm *mstm = nv50_mstm(mgr); 1336 struct nv50_mstc *mstc; 1337 int ret; 1338 1339 ret = nv50_mstc_new(mstm, port, path, &mstc); 1340 if (ret) 1341 return NULL; 1342 1343 return &mstc->connector; 1344 } 1345 1346 static const struct drm_dp_mst_topology_cbs 1347 nv50_mstm = { 1348 .add_connector = nv50_mstm_add_connector, 1349 }; 1350 1351 bool 1352 nv50_mstm_service(struct nouveau_drm *drm, 1353 struct nouveau_connector *nv_connector, 1354 struct nv50_mstm *mstm) 1355 { 1356 struct drm_dp_aux *aux = &nv_connector->aux; 1357 bool handled = true, ret = true; 1358 int rc; 1359 u8 esi[8] = {}; 1360 1361 while (handled) { 1362 u8 ack[8] = {}; 1363 1364 rc = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1365 if (rc != 8) { 1366 ret = false; 1367 break; 1368 } 1369 1370 drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled); 1371 if (!handled) 1372 break; 1373 1374 rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]); 1375 1376 if (rc != 1) { 1377 ret = false; 1378 break; 1379 } 1380 1381 drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr); 1382 } 1383 1384 if (!ret) 1385 NV_DEBUG(drm, "Failed to handle ESI on %s: %d\n", 1386 nv_connector->base.name, rc); 1387 1388 return ret; 1389 } 1390 1391 void 1392 nv50_mstm_remove(struct nv50_mstm *mstm) 1393 { 1394 mstm->is_mst = false; 1395 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1396 } 1397 1398 int 1399 nv50_mstm_detect(struct nouveau_encoder *outp) 1400 { 1401 struct nv50_mstm *mstm = outp->dp.mstm; 1402 struct drm_dp_aux *aux; 1403 int ret; 1404 1405 if (!mstm || !mstm->can_mst) 1406 return 0; 1407 1408 aux = mstm->mgr.aux; 1409 1410 /* Clear any leftover MST state we didn't set ourselves by first 1411 * disabling MST if it was already enabled 1412 */ 1413 ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1414 if (ret < 0) 1415 return ret; 1416 1417 /* And start enabling */ 1418 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true); 1419 if (ret) 1420 return ret; 1421 1422 mstm->is_mst = true; 1423 return 1; 1424 } 1425 1426 static void 1427 nv50_mstm_fini(struct nouveau_encoder *outp) 1428 { 1429 struct nv50_mstm *mstm = outp->dp.mstm; 1430 1431 if (!mstm) 1432 return; 1433 1434 /* Don't change the MST state of this connector until we've finished 1435 * resuming, since we can't safely grab hpd_irq_lock in our resume 1436 * path to protect mstm->is_mst without potentially deadlocking 1437 */ 1438 mutex_lock(&outp->dp.hpd_irq_lock); 1439 mstm->suspended = true; 1440 mutex_unlock(&outp->dp.hpd_irq_lock); 1441 1442 if (mstm->is_mst) 1443 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1444 } 1445 1446 static void 1447 nv50_mstm_init(struct nouveau_encoder *outp, bool runtime) 1448 { 1449 struct nv50_mstm *mstm = outp->dp.mstm; 1450 int ret = 0; 1451 1452 if (!mstm) 1453 return; 1454 1455 if (mstm->is_mst) { 1456 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1457 if (ret == -1) 1458 nv50_mstm_remove(mstm); 1459 } 1460 1461 mutex_lock(&outp->dp.hpd_irq_lock); 1462 mstm->suspended = false; 1463 mutex_unlock(&outp->dp.hpd_irq_lock); 1464 1465 if (ret == -1) 1466 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1467 } 1468 1469 static void 1470 nv50_mstm_del(struct nv50_mstm **pmstm) 1471 { 1472 struct nv50_mstm *mstm = *pmstm; 1473 if (mstm) { 1474 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1475 kfree(*pmstm); 1476 *pmstm = NULL; 1477 } 1478 } 1479 1480 static int 1481 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1482 int conn_base_id, struct nv50_mstm **pmstm) 1483 { 1484 const int max_payloads = hweight8(outp->dcb->heads); 1485 struct drm_device *dev = outp->base.base.dev; 1486 struct nv50_mstm *mstm; 1487 int ret; 1488 1489 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1490 return -ENOMEM; 1491 mstm->outp = outp; 1492 mstm->mgr.cbs = &nv50_mstm; 1493 1494 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1495 max_payloads, conn_base_id); 1496 if (ret) 1497 return ret; 1498 1499 return 0; 1500 } 1501 1502 /****************************************************************************** 1503 * SOR 1504 *****************************************************************************/ 1505 static void 1506 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1507 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1508 { 1509 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1510 struct nv50_core *core = disp->core; 1511 1512 if (!asyh) { 1513 nv_encoder->ctrl &= ~BIT(head); 1514 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) 1515 nv_encoder->ctrl = 0; 1516 } else { 1517 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); 1518 nv_encoder->ctrl |= BIT(head); 1519 asyh->or.depth = depth; 1520 } 1521 1522 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh); 1523 } 1524 1525 /* TODO: Should we extend this to PWM-only backlights? 1526 * As well, should we add a DRM helper for waiting for the backlight to acknowledge 1527 * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a 1528 * fixed time delay from the vbios… 1529 */ 1530 static void 1531 nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1532 { 1533 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1534 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1535 struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder); 1536 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1537 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 1538 struct nouveau_backlight *backlight = nv_connector->backlight; 1539 #endif 1540 struct drm_dp_aux *aux = &nv_connector->aux; 1541 int ret; 1542 u8 pwr; 1543 1544 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1545 if (backlight && backlight->uses_dpcd) { 1546 ret = drm_edp_backlight_disable(aux, &backlight->edp_info); 1547 if (ret < 0) 1548 NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n", 1549 nv_connector->base.base.id, nv_connector->base.name, ret); 1550 } 1551 #endif 1552 1553 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 1554 ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr); 1555 1556 if (ret == 0) { 1557 pwr &= ~DP_SET_POWER_MASK; 1558 pwr |= DP_SET_POWER_D3; 1559 drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr); 1560 } 1561 } 1562 1563 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1564 nv50_audio_disable(encoder, nv_crtc); 1565 nvif_outp_release(&nv_encoder->outp); 1566 nv_encoder->crtc = NULL; 1567 } 1568 1569 static void 1570 nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1571 { 1572 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1573 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1574 struct nv50_head_atom *asyh = 1575 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1576 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1577 struct nv50_disp *disp = nv50_disp(encoder->dev); 1578 struct nvif_outp *outp = &nv_encoder->outp; 1579 struct drm_device *dev = encoder->dev; 1580 struct nouveau_drm *drm = nouveau_drm(dev); 1581 struct nouveau_connector *nv_connector; 1582 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1583 struct nouveau_backlight *backlight; 1584 #endif 1585 struct nvbios *bios = &drm->vbios; 1586 bool lvds_dual = false, lvds_8bpc = false, hda = false; 1587 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; 1588 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; 1589 1590 nv_connector = nv50_outp_get_new_connector(state, nv_encoder); 1591 nv_encoder->crtc = &nv_crtc->base; 1592 1593 if ((disp->disp->object.oclass == GT214_DISP || 1594 disp->disp->object.oclass >= GF110_DISP) && 1595 drm_detect_monitor_audio(nv_connector->edid)) 1596 hda = true; 1597 1598 switch (nv_encoder->dcb->type) { 1599 case DCB_OUTPUT_TMDS: 1600 if (disp->disp->object.oclass == NV50_DISP || 1601 !drm_detect_hdmi_monitor(nv_connector->edid)) 1602 nvif_outp_acquire_tmds(outp, nv_crtc->index, false, 0, 0, 0, false); 1603 else 1604 nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda); 1605 1606 if (nv_encoder->outp.or.link & 1) { 1607 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; 1608 /* Only enable dual-link if: 1609 * - Need to (i.e. rate > 165MHz) 1610 * - DCB says we can 1611 * - Not an HDMI monitor, since there's no dual-link 1612 * on HDMI. 1613 */ 1614 if (mode->clock >= 165000 && 1615 nv_encoder->dcb->duallink_possible && 1616 !drm_detect_hdmi_monitor(nv_connector->edid)) 1617 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; 1618 } else { 1619 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; 1620 } 1621 break; 1622 case DCB_OUTPUT_LVDS: 1623 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; 1624 1625 if (bios->fp_no_ddc) { 1626 lvds_dual = bios->fp.dual_link; 1627 lvds_8bpc = bios->fp.if_is_24bit; 1628 } else { 1629 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1630 if (((u8 *)nv_connector->edid)[121] == 2) 1631 lvds_dual = true; 1632 } else 1633 if (mode->clock >= bios->fp.duallink_transition_clk) { 1634 lvds_dual = true; 1635 } 1636 1637 if (lvds_dual) { 1638 if (bios->fp.strapless_is_24bit & 2) 1639 lvds_8bpc = true; 1640 } else { 1641 if (bios->fp.strapless_is_24bit & 1) 1642 lvds_8bpc = true; 1643 } 1644 1645 if (asyh->or.bpc == 8) 1646 lvds_8bpc = true; 1647 } 1648 1649 nvif_outp_acquire_lvds(&nv_encoder->outp, lvds_dual, lvds_8bpc); 1650 break; 1651 case DCB_OUTPUT_DP: 1652 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, hda, false); 1653 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1654 1655 if (nv_encoder->outp.or.link & 1) 1656 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1657 else 1658 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1659 1660 nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode); 1661 1662 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT 1663 backlight = nv_connector->backlight; 1664 if (backlight && backlight->uses_dpcd) 1665 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info, 1666 (u16)backlight->dev->props.brightness); 1667 #endif 1668 1669 break; 1670 default: 1671 BUG(); 1672 break; 1673 } 1674 1675 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1676 } 1677 1678 static const struct drm_encoder_helper_funcs 1679 nv50_sor_help = { 1680 .atomic_check = nv50_outp_atomic_check, 1681 .atomic_enable = nv50_sor_atomic_enable, 1682 .atomic_disable = nv50_sor_atomic_disable, 1683 }; 1684 1685 static void 1686 nv50_sor_destroy(struct drm_encoder *encoder) 1687 { 1688 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1689 1690 nvif_outp_dtor(&nv_encoder->outp); 1691 1692 nv50_mstm_del(&nv_encoder->dp.mstm); 1693 drm_encoder_cleanup(encoder); 1694 1695 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) 1696 mutex_destroy(&nv_encoder->dp.hpd_irq_lock); 1697 1698 kfree(encoder); 1699 } 1700 1701 static const struct drm_encoder_funcs 1702 nv50_sor_func = { 1703 .destroy = nv50_sor_destroy, 1704 }; 1705 1706 bool nv50_has_mst(struct nouveau_drm *drm) 1707 { 1708 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1709 u32 data; 1710 u8 ver, hdr, cnt, len; 1711 1712 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1713 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1714 } 1715 1716 static int 1717 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1718 { 1719 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1720 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1721 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1722 struct nouveau_encoder *nv_encoder; 1723 struct drm_encoder *encoder; 1724 struct nv50_disp *disp = nv50_disp(connector->dev); 1725 int type, ret; 1726 1727 switch (dcbe->type) { 1728 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1729 case DCB_OUTPUT_TMDS: 1730 case DCB_OUTPUT_DP: 1731 default: 1732 type = DRM_MODE_ENCODER_TMDS; 1733 break; 1734 } 1735 1736 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1737 if (!nv_encoder) 1738 return -ENOMEM; 1739 nv_encoder->dcb = dcbe; 1740 nv_encoder->update = nv50_sor_update; 1741 1742 encoder = to_drm_encoder(nv_encoder); 1743 encoder->possible_crtcs = dcbe->heads; 1744 encoder->possible_clones = 0; 1745 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1746 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1747 drm_encoder_helper_add(encoder, &nv50_sor_help); 1748 1749 drm_connector_attach_encoder(connector, encoder); 1750 1751 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1752 nv50_outp_dump_caps(drm, nv_encoder); 1753 1754 if (dcbe->type == DCB_OUTPUT_DP) { 1755 struct nvkm_i2c_aux *aux = 1756 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1757 1758 mutex_init(&nv_encoder->dp.hpd_irq_lock); 1759 1760 if (aux) { 1761 if (disp->disp->object.oclass < GF110_DISP) { 1762 /* HW has no support for address-only 1763 * transactions, so we're required to 1764 * use custom I2C-over-AUX code. 1765 */ 1766 nv_encoder->i2c = &aux->i2c; 1767 } else { 1768 nv_encoder->i2c = &nv_connector->aux.ddc; 1769 } 1770 nv_encoder->aux = aux; 1771 } 1772 1773 if (nv_connector->type != DCB_CONNECTOR_eDP && 1774 nv50_has_mst(drm)) { 1775 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1776 16, nv_connector->base.base.id, 1777 &nv_encoder->dp.mstm); 1778 if (ret) 1779 return ret; 1780 } 1781 } else { 1782 struct nvkm_i2c_bus *bus = 1783 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1784 if (bus) 1785 nv_encoder->i2c = &bus->i2c; 1786 } 1787 1788 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 1789 } 1790 1791 /****************************************************************************** 1792 * PIOR 1793 *****************************************************************************/ 1794 static int 1795 nv50_pior_atomic_check(struct drm_encoder *encoder, 1796 struct drm_crtc_state *crtc_state, 1797 struct drm_connector_state *conn_state) 1798 { 1799 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1800 if (ret) 1801 return ret; 1802 crtc_state->adjusted_mode.clock *= 2; 1803 return 0; 1804 } 1805 1806 static void 1807 nv50_pior_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1808 { 1809 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1810 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1811 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); 1812 1813 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL); 1814 nv_encoder->crtc = NULL; 1815 nvif_outp_release(&nv_encoder->outp); 1816 } 1817 1818 static void 1819 nv50_pior_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *state) 1820 { 1821 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1822 struct nouveau_crtc *nv_crtc = nv50_outp_get_new_crtc(state, nv_encoder); 1823 struct nv50_head_atom *asyh = 1824 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base)); 1825 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1826 u32 ctrl = 0; 1827 1828 switch (nv_crtc->index) { 1829 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; 1830 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; 1831 default: 1832 WARN_ON(1); 1833 break; 1834 } 1835 1836 switch (asyh->or.bpc) { 1837 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; 1838 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; 1839 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; 1840 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; 1841 } 1842 1843 switch (nv_encoder->dcb->type) { 1844 case DCB_OUTPUT_TMDS: 1845 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1846 nvif_outp_acquire_tmds(&nv_encoder->outp, false, false, 0, 0, 0, false); 1847 break; 1848 case DCB_OUTPUT_DP: 1849 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1850 nvif_outp_acquire_dp(&nv_encoder->outp, nv_encoder->dp.dpcd, 0, 0, false, false); 1851 break; 1852 default: 1853 BUG(); 1854 break; 1855 } 1856 1857 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh); 1858 nv_encoder->crtc = &nv_crtc->base; 1859 } 1860 1861 static const struct drm_encoder_helper_funcs 1862 nv50_pior_help = { 1863 .atomic_check = nv50_pior_atomic_check, 1864 .atomic_enable = nv50_pior_atomic_enable, 1865 .atomic_disable = nv50_pior_atomic_disable, 1866 }; 1867 1868 static void 1869 nv50_pior_destroy(struct drm_encoder *encoder) 1870 { 1871 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1872 1873 nvif_outp_dtor(&nv_encoder->outp); 1874 1875 drm_encoder_cleanup(encoder); 1876 kfree(encoder); 1877 } 1878 1879 static const struct drm_encoder_funcs 1880 nv50_pior_func = { 1881 .destroy = nv50_pior_destroy, 1882 }; 1883 1884 static int 1885 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1886 { 1887 struct drm_device *dev = connector->dev; 1888 struct nouveau_drm *drm = nouveau_drm(dev); 1889 struct nv50_disp *disp = nv50_disp(dev); 1890 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1891 struct nvkm_i2c_bus *bus = NULL; 1892 struct nvkm_i2c_aux *aux = NULL; 1893 struct i2c_adapter *ddc; 1894 struct nouveau_encoder *nv_encoder; 1895 struct drm_encoder *encoder; 1896 int type; 1897 1898 switch (dcbe->type) { 1899 case DCB_OUTPUT_TMDS: 1900 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1901 ddc = bus ? &bus->i2c : NULL; 1902 type = DRM_MODE_ENCODER_TMDS; 1903 break; 1904 case DCB_OUTPUT_DP: 1905 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1906 ddc = aux ? &aux->i2c : NULL; 1907 type = DRM_MODE_ENCODER_TMDS; 1908 break; 1909 default: 1910 return -ENODEV; 1911 } 1912 1913 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1914 if (!nv_encoder) 1915 return -ENOMEM; 1916 nv_encoder->dcb = dcbe; 1917 nv_encoder->i2c = ddc; 1918 nv_encoder->aux = aux; 1919 1920 encoder = to_drm_encoder(nv_encoder); 1921 encoder->possible_crtcs = dcbe->heads; 1922 encoder->possible_clones = 0; 1923 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1924 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1925 drm_encoder_helper_add(encoder, &nv50_pior_help); 1926 1927 drm_connector_attach_encoder(connector, encoder); 1928 1929 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1930 nv50_outp_dump_caps(drm, nv_encoder); 1931 1932 return nvif_outp_ctor(disp->disp, nv_encoder->base.base.name, dcbe->id, &nv_encoder->outp); 1933 } 1934 1935 /****************************************************************************** 1936 * Atomic 1937 *****************************************************************************/ 1938 1939 static void 1940 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1941 { 1942 struct drm_dp_mst_topology_mgr *mgr; 1943 struct drm_dp_mst_topology_state *mst_state; 1944 struct nouveau_drm *drm = nouveau_drm(state->dev); 1945 struct nv50_disp *disp = nv50_disp(drm->dev); 1946 struct nv50_core *core = disp->core; 1947 struct nv50_mstm *mstm; 1948 int i; 1949 1950 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1951 1952 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 1953 mstm = nv50_mstm(mgr); 1954 if (mstm->modified) 1955 nv50_mstm_prepare(state, mst_state, mstm); 1956 } 1957 1958 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1959 core->func->update(core, interlock, true); 1960 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1961 disp->core->chan.base.device)) 1962 NV_ERROR(drm, "core notifier timeout\n"); 1963 1964 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { 1965 mstm = nv50_mstm(mgr); 1966 if (mstm->modified) 1967 nv50_mstm_cleanup(state, mst_state, mstm); 1968 } 1969 } 1970 1971 static void 1972 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 1973 { 1974 struct drm_plane_state *new_plane_state; 1975 struct drm_plane *plane; 1976 int i; 1977 1978 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 1979 struct nv50_wndw *wndw = nv50_wndw(plane); 1980 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 1981 if (wndw->func->update) 1982 wndw->func->update(wndw, interlock); 1983 } 1984 } 1985 } 1986 1987 static void 1988 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 1989 { 1990 struct drm_device *dev = state->dev; 1991 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 1992 struct drm_crtc *crtc; 1993 struct drm_plane_state *new_plane_state; 1994 struct drm_plane *plane; 1995 struct nouveau_drm *drm = nouveau_drm(dev); 1996 struct nv50_disp *disp = nv50_disp(dev); 1997 struct nv50_atom *atom = nv50_atom(state); 1998 struct nv50_core *core = disp->core; 1999 struct nv50_outp_atom *outp, *outt; 2000 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 2001 int i; 2002 bool flushed = false; 2003 2004 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 2005 nv50_crc_atomic_stop_reporting(state); 2006 drm_atomic_helper_wait_for_fences(dev, state, false); 2007 drm_atomic_helper_wait_for_dependencies(state); 2008 drm_dp_mst_atomic_wait_for_dependencies(state); 2009 drm_atomic_helper_update_legacy_modeset_state(dev, state); 2010 drm_atomic_helper_calc_timestamping_constants(state); 2011 2012 if (atom->lock_core) 2013 mutex_lock(&disp->mutex); 2014 2015 /* Disable head(s). */ 2016 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2017 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2018 struct nv50_head *head = nv50_head(crtc); 2019 2020 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 2021 asyh->clr.mask, asyh->set.mask); 2022 2023 if (old_crtc_state->active && !new_crtc_state->active) { 2024 pm_runtime_put_noidle(dev->dev); 2025 drm_crtc_vblank_off(crtc); 2026 } 2027 2028 if (asyh->clr.mask) { 2029 nv50_head_flush_clr(head, asyh, atom->flush_disable); 2030 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2031 } 2032 } 2033 2034 /* Disable plane(s). */ 2035 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2036 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2037 struct nv50_wndw *wndw = nv50_wndw(plane); 2038 2039 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2040 asyw->clr.mask, asyw->set.mask); 2041 if (!asyw->clr.mask) 2042 continue; 2043 2044 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 2045 } 2046 2047 /* Disable output path(s). */ 2048 list_for_each_entry(outp, &atom->outp, head) { 2049 const struct drm_encoder_helper_funcs *help; 2050 struct drm_encoder *encoder; 2051 2052 encoder = outp->encoder; 2053 help = encoder->helper_private; 2054 2055 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2056 outp->clr.mask, outp->set.mask); 2057 2058 if (outp->clr.mask) { 2059 help->atomic_disable(encoder, state); 2060 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2061 if (outp->flush_disable) { 2062 nv50_disp_atomic_commit_wndw(state, interlock); 2063 nv50_disp_atomic_commit_core(state, interlock); 2064 memset(interlock, 0x00, sizeof(interlock)); 2065 2066 flushed = true; 2067 } 2068 } 2069 } 2070 2071 /* Flush disable. */ 2072 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2073 if (atom->flush_disable) { 2074 nv50_disp_atomic_commit_wndw(state, interlock); 2075 nv50_disp_atomic_commit_core(state, interlock); 2076 memset(interlock, 0x00, sizeof(interlock)); 2077 2078 flushed = true; 2079 } 2080 } 2081 2082 if (flushed) 2083 nv50_crc_atomic_release_notifier_contexts(state); 2084 nv50_crc_atomic_init_notifier_contexts(state); 2085 2086 /* Update output path(s). */ 2087 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2088 const struct drm_encoder_helper_funcs *help; 2089 struct drm_encoder *encoder; 2090 2091 encoder = outp->encoder; 2092 help = encoder->helper_private; 2093 2094 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2095 outp->set.mask, outp->clr.mask); 2096 2097 if (outp->set.mask) { 2098 help->atomic_enable(encoder, state); 2099 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2100 } 2101 2102 list_del(&outp->head); 2103 kfree(outp); 2104 } 2105 2106 /* Update head(s). */ 2107 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2108 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2109 struct nv50_head *head = nv50_head(crtc); 2110 2111 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2112 asyh->set.mask, asyh->clr.mask); 2113 2114 if (asyh->set.mask) { 2115 nv50_head_flush_set(head, asyh); 2116 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2117 } 2118 2119 if (new_crtc_state->active) { 2120 if (!old_crtc_state->active) { 2121 drm_crtc_vblank_on(crtc); 2122 pm_runtime_get_noresume(dev->dev); 2123 } 2124 if (new_crtc_state->event) 2125 drm_crtc_vblank_get(crtc); 2126 } 2127 } 2128 2129 /* Update window->head assignment. 2130 * 2131 * This has to happen in an update that's not interlocked with 2132 * any window channels to avoid hitting HW error checks. 2133 * 2134 *TODO: Proper handling of window ownership (Turing apparently 2135 * supports non-fixed mappings). 2136 */ 2137 if (core->assign_windows) { 2138 core->func->wndw.owner(core); 2139 nv50_disp_atomic_commit_core(state, interlock); 2140 core->assign_windows = false; 2141 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2142 } 2143 2144 /* Finish updating head(s)... 2145 * 2146 * NVD is rather picky about both where window assignments can change, 2147 * *and* about certain core and window channel states matching. 2148 * 2149 * The EFI GOP driver on newer GPUs configures window channels with a 2150 * different output format to what we do, and the core channel update 2151 * in the assign_windows case above would result in a state mismatch. 2152 * 2153 * Delay some of the head update until after that point to workaround 2154 * the issue. This only affects the initial modeset. 2155 * 2156 * TODO: handle this better when adding flexible window mapping 2157 */ 2158 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2159 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2160 struct nv50_head *head = nv50_head(crtc); 2161 2162 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2163 asyh->set.mask, asyh->clr.mask); 2164 2165 if (asyh->set.mask) { 2166 nv50_head_flush_set_wndw(head, asyh); 2167 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2168 } 2169 } 2170 2171 /* Update plane(s). */ 2172 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2173 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2174 struct nv50_wndw *wndw = nv50_wndw(plane); 2175 2176 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2177 asyw->set.mask, asyw->clr.mask); 2178 if ( !asyw->set.mask && 2179 (!asyw->clr.mask || atom->flush_disable)) 2180 continue; 2181 2182 nv50_wndw_flush_set(wndw, interlock, asyw); 2183 } 2184 2185 /* Flush update. */ 2186 nv50_disp_atomic_commit_wndw(state, interlock); 2187 2188 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2189 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2190 interlock[NV50_DISP_INTERLOCK_OVLY] || 2191 interlock[NV50_DISP_INTERLOCK_WNDW] || 2192 !atom->state.legacy_cursor_update) 2193 nv50_disp_atomic_commit_core(state, interlock); 2194 else 2195 disp->core->func->update(disp->core, interlock, false); 2196 } 2197 2198 if (atom->lock_core) 2199 mutex_unlock(&disp->mutex); 2200 2201 /* Wait for HW to signal completion. */ 2202 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2203 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2204 struct nv50_wndw *wndw = nv50_wndw(plane); 2205 int ret = nv50_wndw_wait_armed(wndw, asyw); 2206 if (ret) 2207 NV_ERROR(drm, "%s: timeout\n", plane->name); 2208 } 2209 2210 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2211 if (new_crtc_state->event) { 2212 unsigned long flags; 2213 /* Get correct count/ts if racing with vblank irq */ 2214 if (new_crtc_state->active) 2215 drm_crtc_accurate_vblank_count(crtc); 2216 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2217 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2218 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2219 2220 new_crtc_state->event = NULL; 2221 if (new_crtc_state->active) 2222 drm_crtc_vblank_put(crtc); 2223 } 2224 } 2225 2226 nv50_crc_atomic_start_reporting(state); 2227 if (!flushed) 2228 nv50_crc_atomic_release_notifier_contexts(state); 2229 2230 drm_atomic_helper_commit_hw_done(state); 2231 drm_atomic_helper_cleanup_planes(dev, state); 2232 drm_atomic_helper_commit_cleanup_done(state); 2233 drm_atomic_state_put(state); 2234 2235 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2236 pm_runtime_mark_last_busy(dev->dev); 2237 pm_runtime_put_autosuspend(dev->dev); 2238 } 2239 2240 static void 2241 nv50_disp_atomic_commit_work(struct work_struct *work) 2242 { 2243 struct drm_atomic_state *state = 2244 container_of(work, typeof(*state), commit_work); 2245 nv50_disp_atomic_commit_tail(state); 2246 } 2247 2248 static int 2249 nv50_disp_atomic_commit(struct drm_device *dev, 2250 struct drm_atomic_state *state, bool nonblock) 2251 { 2252 struct drm_plane_state *new_plane_state; 2253 struct drm_plane *plane; 2254 int ret, i; 2255 2256 ret = pm_runtime_get_sync(dev->dev); 2257 if (ret < 0 && ret != -EACCES) { 2258 pm_runtime_put_autosuspend(dev->dev); 2259 return ret; 2260 } 2261 2262 ret = drm_atomic_helper_setup_commit(state, nonblock); 2263 if (ret) 2264 goto done; 2265 2266 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2267 2268 ret = drm_atomic_helper_prepare_planes(dev, state); 2269 if (ret) 2270 goto done; 2271 2272 if (!nonblock) { 2273 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2274 if (ret) 2275 goto err_cleanup; 2276 } 2277 2278 ret = drm_atomic_helper_swap_state(state, true); 2279 if (ret) 2280 goto err_cleanup; 2281 2282 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2283 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2284 struct nv50_wndw *wndw = nv50_wndw(plane); 2285 2286 if (asyw->set.image) 2287 nv50_wndw_ntfy_enable(wndw, asyw); 2288 } 2289 2290 drm_atomic_state_get(state); 2291 2292 /* 2293 * Grab another RPM ref for the commit tail, which will release the 2294 * ref when it's finished 2295 */ 2296 pm_runtime_get_noresume(dev->dev); 2297 2298 if (nonblock) 2299 queue_work(system_unbound_wq, &state->commit_work); 2300 else 2301 nv50_disp_atomic_commit_tail(state); 2302 2303 err_cleanup: 2304 if (ret) 2305 drm_atomic_helper_cleanup_planes(dev, state); 2306 done: 2307 pm_runtime_put_autosuspend(dev->dev); 2308 return ret; 2309 } 2310 2311 static struct nv50_outp_atom * 2312 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2313 { 2314 struct nv50_outp_atom *outp; 2315 2316 list_for_each_entry(outp, &atom->outp, head) { 2317 if (outp->encoder == encoder) 2318 return outp; 2319 } 2320 2321 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2322 if (!outp) 2323 return ERR_PTR(-ENOMEM); 2324 2325 list_add(&outp->head, &atom->outp); 2326 outp->encoder = encoder; 2327 return outp; 2328 } 2329 2330 static int 2331 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2332 struct drm_connector_state *old_connector_state) 2333 { 2334 struct drm_encoder *encoder = old_connector_state->best_encoder; 2335 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2336 struct drm_crtc *crtc; 2337 struct nv50_outp_atom *outp; 2338 2339 if (!(crtc = old_connector_state->crtc)) 2340 return 0; 2341 2342 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2343 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2344 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2345 outp = nv50_disp_outp_atomic_add(atom, encoder); 2346 if (IS_ERR(outp)) 2347 return PTR_ERR(outp); 2348 2349 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2350 outp->flush_disable = true; 2351 atom->flush_disable = true; 2352 } 2353 outp->clr.ctrl = true; 2354 atom->lock_core = true; 2355 } 2356 2357 return 0; 2358 } 2359 2360 static int 2361 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2362 struct drm_connector_state *connector_state) 2363 { 2364 struct drm_encoder *encoder = connector_state->best_encoder; 2365 struct drm_crtc_state *new_crtc_state; 2366 struct drm_crtc *crtc; 2367 struct nv50_outp_atom *outp; 2368 2369 if (!(crtc = connector_state->crtc)) 2370 return 0; 2371 2372 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2373 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2374 outp = nv50_disp_outp_atomic_add(atom, encoder); 2375 if (IS_ERR(outp)) 2376 return PTR_ERR(outp); 2377 2378 outp->set.ctrl = true; 2379 atom->lock_core = true; 2380 } 2381 2382 return 0; 2383 } 2384 2385 static int 2386 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2387 { 2388 struct nv50_atom *atom = nv50_atom(state); 2389 struct nv50_core *core = nv50_disp(dev)->core; 2390 struct drm_connector_state *old_connector_state, *new_connector_state; 2391 struct drm_connector *connector; 2392 struct drm_crtc_state *new_crtc_state; 2393 struct drm_crtc *crtc; 2394 struct nv50_head *head; 2395 struct nv50_head_atom *asyh; 2396 int ret, i; 2397 2398 if (core->assign_windows && core->func->head->static_wndw_map) { 2399 drm_for_each_crtc(crtc, dev) { 2400 new_crtc_state = drm_atomic_get_crtc_state(state, 2401 crtc); 2402 if (IS_ERR(new_crtc_state)) 2403 return PTR_ERR(new_crtc_state); 2404 2405 head = nv50_head(crtc); 2406 asyh = nv50_head_atom(new_crtc_state); 2407 core->func->head->static_wndw_map(head, asyh); 2408 } 2409 } 2410 2411 /* We need to handle colour management on a per-plane basis. */ 2412 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2413 if (new_crtc_state->color_mgmt_changed) { 2414 ret = drm_atomic_add_affected_planes(state, crtc); 2415 if (ret) 2416 return ret; 2417 } 2418 } 2419 2420 ret = drm_atomic_helper_check(dev, state); 2421 if (ret) 2422 return ret; 2423 2424 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2425 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2426 if (ret) 2427 return ret; 2428 2429 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2430 if (ret) 2431 return ret; 2432 } 2433 2434 ret = drm_dp_mst_atomic_check(state); 2435 if (ret) 2436 return ret; 2437 2438 nv50_crc_atomic_check_outp(atom); 2439 2440 return 0; 2441 } 2442 2443 static void 2444 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2445 { 2446 struct nv50_atom *atom = nv50_atom(state); 2447 struct nv50_outp_atom *outp, *outt; 2448 2449 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2450 list_del(&outp->head); 2451 kfree(outp); 2452 } 2453 2454 drm_atomic_state_default_clear(state); 2455 } 2456 2457 static void 2458 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2459 { 2460 struct nv50_atom *atom = nv50_atom(state); 2461 drm_atomic_state_default_release(&atom->state); 2462 kfree(atom); 2463 } 2464 2465 static struct drm_atomic_state * 2466 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2467 { 2468 struct nv50_atom *atom; 2469 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2470 drm_atomic_state_init(dev, &atom->state) < 0) { 2471 kfree(atom); 2472 return NULL; 2473 } 2474 INIT_LIST_HEAD(&atom->outp); 2475 return &atom->state; 2476 } 2477 2478 static const struct drm_mode_config_funcs 2479 nv50_disp_func = { 2480 .fb_create = nouveau_user_framebuffer_create, 2481 .output_poll_changed = drm_fb_helper_output_poll_changed, 2482 .atomic_check = nv50_disp_atomic_check, 2483 .atomic_commit = nv50_disp_atomic_commit, 2484 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2485 .atomic_state_clear = nv50_disp_atomic_state_clear, 2486 .atomic_state_free = nv50_disp_atomic_state_free, 2487 }; 2488 2489 static const struct drm_mode_config_helper_funcs 2490 nv50_disp_helper_func = { 2491 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 2492 }; 2493 2494 /****************************************************************************** 2495 * Init 2496 *****************************************************************************/ 2497 2498 static void 2499 nv50_display_fini(struct drm_device *dev, bool runtime, bool suspend) 2500 { 2501 struct nouveau_drm *drm = nouveau_drm(dev); 2502 struct drm_encoder *encoder; 2503 2504 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2505 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 2506 nv50_mstm_fini(nouveau_encoder(encoder)); 2507 } 2508 2509 if (!runtime) 2510 cancel_work_sync(&drm->hpd_work); 2511 } 2512 2513 static int 2514 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2515 { 2516 struct nv50_core *core = nv50_disp(dev)->core; 2517 struct drm_encoder *encoder; 2518 2519 if (resume || runtime) 2520 core->func->init(core); 2521 2522 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2523 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2524 struct nouveau_encoder *nv_encoder = 2525 nouveau_encoder(encoder); 2526 nv50_mstm_init(nv_encoder, runtime); 2527 } 2528 } 2529 2530 return 0; 2531 } 2532 2533 static void 2534 nv50_display_destroy(struct drm_device *dev) 2535 { 2536 struct nv50_disp *disp = nv50_disp(dev); 2537 2538 nv50_audio_component_fini(nouveau_drm(dev)); 2539 2540 nvif_object_unmap(&disp->caps); 2541 nvif_object_dtor(&disp->caps); 2542 nv50_core_del(&disp->core); 2543 2544 nouveau_bo_unmap(disp->sync); 2545 if (disp->sync) 2546 nouveau_bo_unpin(disp->sync); 2547 nouveau_bo_ref(NULL, &disp->sync); 2548 2549 nouveau_display(dev)->priv = NULL; 2550 kfree(disp); 2551 } 2552 2553 int 2554 nv50_display_create(struct drm_device *dev) 2555 { 2556 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2557 struct nouveau_drm *drm = nouveau_drm(dev); 2558 struct dcb_table *dcb = &drm->vbios.dcb; 2559 struct drm_connector *connector, *tmp; 2560 struct nv50_disp *disp; 2561 struct dcb_output *dcbe; 2562 int crtcs, ret, i; 2563 bool has_mst = nv50_has_mst(drm); 2564 2565 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2566 if (!disp) 2567 return -ENOMEM; 2568 2569 mutex_init(&disp->mutex); 2570 2571 nouveau_display(dev)->priv = disp; 2572 nouveau_display(dev)->dtor = nv50_display_destroy; 2573 nouveau_display(dev)->init = nv50_display_init; 2574 nouveau_display(dev)->fini = nv50_display_fini; 2575 disp->disp = &nouveau_display(dev)->disp; 2576 dev->mode_config.funcs = &nv50_disp_func; 2577 dev->mode_config.helper_private = &nv50_disp_helper_func; 2578 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2579 dev->mode_config.normalize_zpos = true; 2580 2581 /* small shared memory area we use for notifiers and semaphores */ 2582 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, 2583 NOUVEAU_GEM_DOMAIN_VRAM, 2584 0, 0x0000, NULL, NULL, &disp->sync); 2585 if (!ret) { 2586 ret = nouveau_bo_pin(disp->sync, NOUVEAU_GEM_DOMAIN_VRAM, true); 2587 if (!ret) { 2588 ret = nouveau_bo_map(disp->sync); 2589 if (ret) 2590 nouveau_bo_unpin(disp->sync); 2591 } 2592 if (ret) 2593 nouveau_bo_ref(NULL, &disp->sync); 2594 } 2595 2596 if (ret) 2597 goto out; 2598 2599 /* allocate master evo channel */ 2600 ret = nv50_core_new(drm, &disp->core); 2601 if (ret) 2602 goto out; 2603 2604 disp->core->func->init(disp->core); 2605 if (disp->core->func->caps_init) { 2606 ret = disp->core->func->caps_init(drm, disp); 2607 if (ret) 2608 goto out; 2609 } 2610 2611 /* Assign the correct format modifiers */ 2612 if (disp->disp->object.oclass >= TU102_DISP) 2613 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2614 else 2615 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) 2616 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2617 else 2618 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2619 2620 /* FIXME: 256x256 cursors are supported on Kepler, however unlike Maxwell and later 2621 * generations Kepler requires that we use small pages (4K) for cursor scanout surfaces. The 2622 * proper fix for this is to teach nouveau to migrate fbs being used for the cursor plane to 2623 * small page allocations in prepare_fb(). When this is implemented, we should also force 2624 * large pages (128K) for ovly fbs in order to fix Kepler ovlys. 2625 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using 2626 * large pages. 2627 */ 2628 if (disp->disp->object.oclass >= GM107_DISP) { 2629 dev->mode_config.cursor_width = 256; 2630 dev->mode_config.cursor_height = 256; 2631 } else if (disp->disp->object.oclass >= GK104_DISP) { 2632 dev->mode_config.cursor_width = 128; 2633 dev->mode_config.cursor_height = 128; 2634 } else { 2635 dev->mode_config.cursor_width = 64; 2636 dev->mode_config.cursor_height = 64; 2637 } 2638 2639 /* create crtc objects to represent the hw heads */ 2640 if (disp->disp->object.oclass >= GV100_DISP) 2641 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2642 else 2643 if (disp->disp->object.oclass >= GF110_DISP) 2644 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2645 else 2646 crtcs = 0x3; 2647 2648 for (i = 0; i < fls(crtcs); i++) { 2649 struct nv50_head *head; 2650 2651 if (!(crtcs & (1 << i))) 2652 continue; 2653 2654 head = nv50_head_create(dev, i); 2655 if (IS_ERR(head)) { 2656 ret = PTR_ERR(head); 2657 goto out; 2658 } 2659 2660 if (has_mst) { 2661 head->msto = nv50_msto_new(dev, head, i); 2662 if (IS_ERR(head->msto)) { 2663 ret = PTR_ERR(head->msto); 2664 head->msto = NULL; 2665 goto out; 2666 } 2667 2668 /* 2669 * FIXME: This is a hack to workaround the following 2670 * issues: 2671 * 2672 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2673 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2674 * 2675 * Once these issues are closed, this should be 2676 * removed 2677 */ 2678 head->msto->encoder.possible_crtcs = crtcs; 2679 } 2680 } 2681 2682 /* create encoder/connector objects based on VBIOS DCB table */ 2683 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2684 connector = nouveau_connector_create(dev, dcbe); 2685 if (IS_ERR(connector)) 2686 continue; 2687 2688 if (dcbe->location == DCB_LOC_ON_CHIP) { 2689 switch (dcbe->type) { 2690 case DCB_OUTPUT_TMDS: 2691 case DCB_OUTPUT_LVDS: 2692 case DCB_OUTPUT_DP: 2693 ret = nv50_sor_create(connector, dcbe); 2694 break; 2695 case DCB_OUTPUT_ANALOG: 2696 ret = nv50_dac_create(connector, dcbe); 2697 break; 2698 default: 2699 ret = -ENODEV; 2700 break; 2701 } 2702 } else { 2703 ret = nv50_pior_create(connector, dcbe); 2704 } 2705 2706 if (ret) { 2707 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2708 dcbe->location, dcbe->type, 2709 ffs(dcbe->or) - 1, ret); 2710 ret = 0; 2711 } 2712 } 2713 2714 /* cull any connectors we created that don't have an encoder */ 2715 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2716 if (connector->possible_encoders) 2717 continue; 2718 2719 NV_WARN(drm, "%s has no encoders, removing\n", 2720 connector->name); 2721 connector->funcs->destroy(connector); 2722 } 2723 2724 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2725 dev->vblank_disable_immediate = true; 2726 2727 nv50_audio_component_init(drm); 2728 2729 out: 2730 if (ret) 2731 nv50_display_destroy(dev); 2732 return ret; 2733 } 2734 2735 /****************************************************************************** 2736 * Format modifiers 2737 *****************************************************************************/ 2738 2739 /**************************************************************** 2740 * Log2(block height) ----------------------------+ * 2741 * Page Kind ----------------------------------+ | * 2742 * Gob Height/Page Kind Generation ------+ | | * 2743 * Sector layout -------+ | | | * 2744 * Compression ------+ | | | | */ 2745 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2746 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2747 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2748 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2749 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2750 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2751 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2752 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2753 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2754 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2755 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2756 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2757 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2758 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2759 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2760 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2761 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2762 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2763 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2764 DRM_FORMAT_MOD_LINEAR, 2765 DRM_FORMAT_MOD_INVALID 2766 }; 2767 2768 /**************************************************************** 2769 * Log2(block height) ----------------------------+ * 2770 * Page Kind ----------------------------------+ | * 2771 * Gob Height/Page Kind Generation ------+ | | * 2772 * Sector layout -------+ | | | * 2773 * Compression ------+ | | | | */ 2774 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2775 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2776 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2777 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2778 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2779 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2780 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2781 DRM_FORMAT_MOD_LINEAR, 2782 DRM_FORMAT_MOD_INVALID 2783 }; 2784