1 /* 2 * Copyright 2011 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "disp.h" 25 #include "atom.h" 26 #include "core.h" 27 #include "head.h" 28 #include "wndw.h" 29 #include "handles.h" 30 31 #include <linux/dma-mapping.h> 32 #include <linux/hdmi.h> 33 #include <linux/component.h> 34 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_dp_helper.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_fb_helper.h> 39 #include <drm/drm_plane_helper.h> 40 #include <drm/drm_probe_helper.h> 41 #include <drm/drm_scdc_helper.h> 42 #include <drm/drm_vblank.h> 43 44 #include <nvif/push507c.h> 45 46 #include <nvif/class.h> 47 #include <nvif/cl0002.h> 48 #include <nvif/cl5070.h> 49 #include <nvif/cl507d.h> 50 #include <nvif/event.h> 51 #include <nvif/timer.h> 52 53 #include <nvhw/class/cl507c.h> 54 #include <nvhw/class/cl507d.h> 55 #include <nvhw/class/cl837d.h> 56 #include <nvhw/class/cl887d.h> 57 #include <nvhw/class/cl907d.h> 58 #include <nvhw/class/cl917d.h> 59 60 #include "nouveau_drv.h" 61 #include "nouveau_dma.h" 62 #include "nouveau_gem.h" 63 #include "nouveau_connector.h" 64 #include "nouveau_encoder.h" 65 #include "nouveau_fence.h" 66 #include "nouveau_fbcon.h" 67 68 #include <subdev/bios/dp.h> 69 70 /****************************************************************************** 71 * EVO channel 72 *****************************************************************************/ 73 74 static int 75 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, 76 const s32 *oclass, u8 head, void *data, u32 size, 77 struct nv50_chan *chan) 78 { 79 struct nvif_sclass *sclass; 80 int ret, i, n; 81 82 chan->device = device; 83 84 ret = n = nvif_object_sclass_get(disp, &sclass); 85 if (ret < 0) 86 return ret; 87 88 while (oclass[0]) { 89 for (i = 0; i < n; i++) { 90 if (sclass[i].oclass == oclass[0]) { 91 ret = nvif_object_ctor(disp, "kmsChan", 0, 92 oclass[0], data, size, 93 &chan->user); 94 if (ret == 0) 95 nvif_object_map(&chan->user, NULL, 0); 96 nvif_object_sclass_put(&sclass); 97 return ret; 98 } 99 } 100 oclass++; 101 } 102 103 nvif_object_sclass_put(&sclass); 104 return -ENOSYS; 105 } 106 107 static void 108 nv50_chan_destroy(struct nv50_chan *chan) 109 { 110 nvif_object_dtor(&chan->user); 111 } 112 113 /****************************************************************************** 114 * DMA EVO channel 115 *****************************************************************************/ 116 117 void 118 nv50_dmac_destroy(struct nv50_dmac *dmac) 119 { 120 nvif_object_dtor(&dmac->vram); 121 nvif_object_dtor(&dmac->sync); 122 123 nv50_chan_destroy(&dmac->base); 124 125 nvif_mem_dtor(&dmac->_push.mem); 126 } 127 128 static void 129 nv50_dmac_kick(struct nvif_push *push) 130 { 131 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 132 133 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 134 if (dmac->put != dmac->cur) { 135 /* Push buffer fetches are not coherent with BAR1, we need to ensure 136 * writes have been flushed right through to VRAM before writing PUT. 137 */ 138 if (dmac->push->mem.type & NVIF_MEM_VRAM) { 139 struct nvif_device *device = dmac->base.device; 140 nvif_wr32(&device->object, 0x070000, 0x00000001); 141 nvif_msec(device, 2000, 142 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) 143 break; 144 ); 145 } 146 147 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); 148 dmac->put = dmac->cur; 149 } 150 151 push->bgn = push->cur; 152 } 153 154 static int 155 nv50_dmac_free(struct nv50_dmac *dmac) 156 { 157 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 158 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ 159 return get - dmac->cur - 5; 160 return dmac->max - dmac->cur; 161 } 162 163 static int 164 nv50_dmac_wind(struct nv50_dmac *dmac) 165 { 166 /* Wait for GET to depart from the beginning of the push buffer to 167 * prevent writing PUT == GET, which would be ignored by HW. 168 */ 169 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); 170 if (get == 0) { 171 /* Corner-case, HW idle, but non-committed work pending. */ 172 if (dmac->put == 0) 173 nv50_dmac_kick(dmac->push); 174 175 if (nvif_msec(dmac->base.device, 2000, 176 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) 177 break; 178 ) < 0) 179 return -ETIMEDOUT; 180 } 181 182 PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); 183 dmac->cur = 0; 184 return 0; 185 } 186 187 static int 188 nv50_dmac_wait(struct nvif_push *push, u32 size) 189 { 190 struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); 191 int free; 192 193 if (WARN_ON(size > dmac->max)) 194 return -EINVAL; 195 196 dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; 197 if (dmac->cur + size >= dmac->max) { 198 int ret = nv50_dmac_wind(dmac); 199 if (ret) 200 return ret; 201 202 push->cur = dmac->_push.mem.object.map.ptr; 203 push->cur = push->cur + dmac->cur; 204 nv50_dmac_kick(push); 205 } 206 207 if (nvif_msec(dmac->base.device, 2000, 208 if ((free = nv50_dmac_free(dmac)) >= size) 209 break; 210 ) < 0) { 211 WARN_ON(1); 212 return -ETIMEDOUT; 213 } 214 215 push->bgn = dmac->_push.mem.object.map.ptr; 216 push->bgn = push->bgn + dmac->cur; 217 push->cur = push->bgn; 218 push->end = push->cur + free; 219 return 0; 220 } 221 222 int 223 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, 224 const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, 225 struct nv50_dmac *dmac) 226 { 227 struct nouveau_cli *cli = (void *)device->object.client; 228 struct nv50_disp_core_channel_dma_v0 *args = data; 229 u8 type = NVIF_MEM_COHERENT; 230 int ret; 231 232 mutex_init(&dmac->lock); 233 234 /* Pascal added support for 47-bit physical addresses, but some 235 * parts of EVO still only accept 40-bit PAs. 236 * 237 * To avoid issues on systems with large amounts of RAM, and on 238 * systems where an IOMMU maps pages at a high address, we need 239 * to allocate push buffers in VRAM instead. 240 * 241 * This appears to match NVIDIA's behaviour on Pascal. 242 */ 243 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) 244 type |= NVIF_MEM_VRAM; 245 246 ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, 247 &dmac->_push.mem); 248 if (ret) 249 return ret; 250 251 dmac->ptr = dmac->_push.mem.object.map.ptr; 252 dmac->_push.wait = nv50_dmac_wait; 253 dmac->_push.kick = nv50_dmac_kick; 254 dmac->push = &dmac->_push; 255 dmac->push->bgn = dmac->_push.mem.object.map.ptr; 256 dmac->push->cur = dmac->push->bgn; 257 dmac->push->end = dmac->push->bgn; 258 dmac->max = 0x1000/4 - 1; 259 260 /* EVO channels are affected by a HW bug where the last 12 DWORDs 261 * of the push buffer aren't able to be used safely. 262 */ 263 if (disp->oclass < GV100_DISP) 264 dmac->max -= 12; 265 266 args->pushbuf = nvif_handle(&dmac->_push.mem.object); 267 268 ret = nv50_chan_create(device, disp, oclass, head, data, size, 269 &dmac->base); 270 if (ret) 271 return ret; 272 273 if (!syncbuf) 274 return 0; 275 276 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, 277 NV_DMA_IN_MEMORY, 278 &(struct nv_dma_v0) { 279 .target = NV_DMA_V0_TARGET_VRAM, 280 .access = NV_DMA_V0_ACCESS_RDWR, 281 .start = syncbuf + 0x0000, 282 .limit = syncbuf + 0x0fff, 283 }, sizeof(struct nv_dma_v0), 284 &dmac->sync); 285 if (ret) 286 return ret; 287 288 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, 289 NV_DMA_IN_MEMORY, 290 &(struct nv_dma_v0) { 291 .target = NV_DMA_V0_TARGET_VRAM, 292 .access = NV_DMA_V0_ACCESS_RDWR, 293 .start = 0, 294 .limit = device->info.ram_user - 1, 295 }, sizeof(struct nv_dma_v0), 296 &dmac->vram); 297 if (ret) 298 return ret; 299 300 return ret; 301 } 302 303 /****************************************************************************** 304 * Output path helpers 305 *****************************************************************************/ 306 static void 307 nv50_outp_release(struct nouveau_encoder *nv_encoder) 308 { 309 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 310 struct { 311 struct nv50_disp_mthd_v1 base; 312 } args = { 313 .base.version = 1, 314 .base.method = NV50_DISP_MTHD_V1_RELEASE, 315 .base.hasht = nv_encoder->dcb->hasht, 316 .base.hashm = nv_encoder->dcb->hashm, 317 }; 318 319 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 320 nv_encoder->or = -1; 321 nv_encoder->link = 0; 322 } 323 324 static int 325 nv50_outp_acquire(struct nouveau_encoder *nv_encoder, bool hda) 326 { 327 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); 328 struct nv50_disp *disp = nv50_disp(drm->dev); 329 struct { 330 struct nv50_disp_mthd_v1 base; 331 struct nv50_disp_acquire_v0 info; 332 } args = { 333 .base.version = 1, 334 .base.method = NV50_DISP_MTHD_V1_ACQUIRE, 335 .base.hasht = nv_encoder->dcb->hasht, 336 .base.hashm = nv_encoder->dcb->hashm, 337 .info.hda = hda, 338 }; 339 int ret; 340 341 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 342 if (ret) { 343 NV_ERROR(drm, "error acquiring output path: %d\n", ret); 344 return ret; 345 } 346 347 nv_encoder->or = args.info.or; 348 nv_encoder->link = args.info.link; 349 return 0; 350 } 351 352 static int 353 nv50_outp_atomic_check_view(struct drm_encoder *encoder, 354 struct drm_crtc_state *crtc_state, 355 struct drm_connector_state *conn_state, 356 struct drm_display_mode *native_mode) 357 { 358 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 359 struct drm_display_mode *mode = &crtc_state->mode; 360 struct drm_connector *connector = conn_state->connector; 361 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); 362 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 363 364 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); 365 asyc->scaler.full = false; 366 if (!native_mode) 367 return 0; 368 369 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { 370 switch (connector->connector_type) { 371 case DRM_MODE_CONNECTOR_LVDS: 372 case DRM_MODE_CONNECTOR_eDP: 373 /* Don't force scaler for EDID modes with 374 * same size as the native one (e.g. different 375 * refresh rate) 376 */ 377 if (mode->hdisplay == native_mode->hdisplay && 378 mode->vdisplay == native_mode->vdisplay && 379 mode->type & DRM_MODE_TYPE_DRIVER) 380 break; 381 mode = native_mode; 382 asyc->scaler.full = true; 383 break; 384 default: 385 break; 386 } 387 } else { 388 mode = native_mode; 389 } 390 391 if (!drm_mode_equal(adjusted_mode, mode)) { 392 drm_mode_copy(adjusted_mode, mode); 393 crtc_state->mode_changed = true; 394 } 395 396 return 0; 397 } 398 399 static int 400 nv50_outp_atomic_check(struct drm_encoder *encoder, 401 struct drm_crtc_state *crtc_state, 402 struct drm_connector_state *conn_state) 403 { 404 struct drm_connector *connector = conn_state->connector; 405 struct nouveau_connector *nv_connector = nouveau_connector(connector); 406 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 407 int ret; 408 409 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 410 nv_connector->native_mode); 411 if (ret) 412 return ret; 413 414 if (crtc_state->mode_changed || crtc_state->connectors_changed) 415 asyh->or.bpc = connector->display_info.bpc; 416 417 return 0; 418 } 419 420 /****************************************************************************** 421 * DAC 422 *****************************************************************************/ 423 static void 424 nv50_dac_disable(struct drm_encoder *encoder) 425 { 426 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 427 struct nv50_core *core = nv50_disp(encoder->dev)->core; 428 const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); 429 if (nv_encoder->crtc) 430 core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL); 431 nv_encoder->crtc = NULL; 432 nv50_outp_release(nv_encoder); 433 } 434 435 static void 436 nv50_dac_enable(struct drm_encoder *encoder) 437 { 438 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 439 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 440 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 441 struct nv50_core *core = nv50_disp(encoder->dev)->core; 442 u32 ctrl = 0; 443 444 switch (nv_crtc->index) { 445 case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; 446 case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; 447 case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; 448 case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; 449 default: 450 WARN_ON(1); 451 break; 452 } 453 454 ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); 455 456 nv50_outp_acquire(nv_encoder, false); 457 458 core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh); 459 asyh->or.depth = 0; 460 461 nv_encoder->crtc = encoder->crtc; 462 } 463 464 static enum drm_connector_status 465 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 466 { 467 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 468 struct nv50_disp *disp = nv50_disp(encoder->dev); 469 struct { 470 struct nv50_disp_mthd_v1 base; 471 struct nv50_disp_dac_load_v0 load; 472 } args = { 473 .base.version = 1, 474 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, 475 .base.hasht = nv_encoder->dcb->hasht, 476 .base.hashm = nv_encoder->dcb->hashm, 477 }; 478 int ret; 479 480 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; 481 if (args.load.data == 0) 482 args.load.data = 340; 483 484 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 485 if (ret || !args.load.load) 486 return connector_status_disconnected; 487 488 return connector_status_connected; 489 } 490 491 static const struct drm_encoder_helper_funcs 492 nv50_dac_help = { 493 .atomic_check = nv50_outp_atomic_check, 494 .enable = nv50_dac_enable, 495 .disable = nv50_dac_disable, 496 .detect = nv50_dac_detect 497 }; 498 499 static void 500 nv50_dac_destroy(struct drm_encoder *encoder) 501 { 502 drm_encoder_cleanup(encoder); 503 kfree(encoder); 504 } 505 506 static const struct drm_encoder_funcs 507 nv50_dac_func = { 508 .destroy = nv50_dac_destroy, 509 }; 510 511 static int 512 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) 513 { 514 struct nouveau_drm *drm = nouveau_drm(connector->dev); 515 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 516 struct nvkm_i2c_bus *bus; 517 struct nouveau_encoder *nv_encoder; 518 struct drm_encoder *encoder; 519 int type = DRM_MODE_ENCODER_DAC; 520 521 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 522 if (!nv_encoder) 523 return -ENOMEM; 524 nv_encoder->dcb = dcbe; 525 526 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 527 if (bus) 528 nv_encoder->i2c = &bus->i2c; 529 530 encoder = to_drm_encoder(nv_encoder); 531 encoder->possible_crtcs = dcbe->heads; 532 encoder->possible_clones = 0; 533 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, 534 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); 535 drm_encoder_helper_add(encoder, &nv50_dac_help); 536 537 drm_connector_attach_encoder(connector, encoder); 538 return 0; 539 } 540 541 /* 542 * audio component binding for ELD notification 543 */ 544 static void 545 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port, 546 int dev_id) 547 { 548 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 549 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, 550 port, dev_id); 551 } 552 553 static int 554 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id, 555 bool *enabled, unsigned char *buf, int max_bytes) 556 { 557 struct drm_device *drm_dev = dev_get_drvdata(kdev); 558 struct nouveau_drm *drm = nouveau_drm(drm_dev); 559 struct drm_encoder *encoder; 560 struct nouveau_encoder *nv_encoder; 561 struct nouveau_connector *nv_connector; 562 struct nouveau_crtc *nv_crtc; 563 int ret = 0; 564 565 *enabled = false; 566 drm_for_each_encoder(encoder, drm->dev) { 567 nv_encoder = nouveau_encoder(encoder); 568 nv_connector = nouveau_encoder_connector_get(nv_encoder); 569 nv_crtc = nouveau_crtc(encoder->crtc); 570 if (!nv_connector || !nv_crtc || nv_encoder->or != port || 571 nv_crtc->index != dev_id) 572 continue; 573 *enabled = nv_encoder->audio; 574 if (*enabled) { 575 ret = drm_eld_size(nv_connector->base.eld); 576 memcpy(buf, nv_connector->base.eld, 577 min(max_bytes, ret)); 578 } 579 break; 580 } 581 return ret; 582 } 583 584 static const struct drm_audio_component_ops nv50_audio_component_ops = { 585 .get_eld = nv50_audio_component_get_eld, 586 }; 587 588 static int 589 nv50_audio_component_bind(struct device *kdev, struct device *hda_kdev, 590 void *data) 591 { 592 struct drm_device *drm_dev = dev_get_drvdata(kdev); 593 struct nouveau_drm *drm = nouveau_drm(drm_dev); 594 struct drm_audio_component *acomp = data; 595 596 if (WARN_ON(!device_link_add(hda_kdev, kdev, DL_FLAG_STATELESS))) 597 return -ENOMEM; 598 599 drm_modeset_lock_all(drm_dev); 600 acomp->ops = &nv50_audio_component_ops; 601 acomp->dev = kdev; 602 drm->audio.component = acomp; 603 drm_modeset_unlock_all(drm_dev); 604 return 0; 605 } 606 607 static void 608 nv50_audio_component_unbind(struct device *kdev, struct device *hda_kdev, 609 void *data) 610 { 611 struct drm_device *drm_dev = dev_get_drvdata(kdev); 612 struct nouveau_drm *drm = nouveau_drm(drm_dev); 613 struct drm_audio_component *acomp = data; 614 615 drm_modeset_lock_all(drm_dev); 616 drm->audio.component = NULL; 617 acomp->ops = NULL; 618 acomp->dev = NULL; 619 drm_modeset_unlock_all(drm_dev); 620 } 621 622 static const struct component_ops nv50_audio_component_bind_ops = { 623 .bind = nv50_audio_component_bind, 624 .unbind = nv50_audio_component_unbind, 625 }; 626 627 static void 628 nv50_audio_component_init(struct nouveau_drm *drm) 629 { 630 if (!component_add(drm->dev->dev, &nv50_audio_component_bind_ops)) 631 drm->audio.component_registered = true; 632 } 633 634 static void 635 nv50_audio_component_fini(struct nouveau_drm *drm) 636 { 637 if (drm->audio.component_registered) { 638 component_del(drm->dev->dev, &nv50_audio_component_bind_ops); 639 drm->audio.component_registered = false; 640 } 641 } 642 643 /****************************************************************************** 644 * Audio 645 *****************************************************************************/ 646 static void 647 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 648 { 649 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 650 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 651 struct nv50_disp *disp = nv50_disp(encoder->dev); 652 struct { 653 struct nv50_disp_mthd_v1 base; 654 struct nv50_disp_sor_hda_eld_v0 eld; 655 } args = { 656 .base.version = 1, 657 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 658 .base.hasht = nv_encoder->dcb->hasht, 659 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 660 (0x0100 << nv_crtc->index), 661 }; 662 663 if (!nv_encoder->audio) 664 return; 665 666 nv_encoder->audio = false; 667 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 668 669 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 670 nv_crtc->index); 671 } 672 673 static void 674 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 675 { 676 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 677 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 678 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 679 struct nouveau_connector *nv_connector; 680 struct nv50_disp *disp = nv50_disp(encoder->dev); 681 struct __packed { 682 struct { 683 struct nv50_disp_mthd_v1 mthd; 684 struct nv50_disp_sor_hda_eld_v0 eld; 685 } base; 686 u8 data[sizeof(nv_connector->base.eld)]; 687 } args = { 688 .base.mthd.version = 1, 689 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, 690 .base.mthd.hasht = nv_encoder->dcb->hasht, 691 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 692 (0x0100 << nv_crtc->index), 693 }; 694 695 nv_connector = nouveau_encoder_connector_get(nv_encoder); 696 if (!drm_detect_monitor_audio(nv_connector->edid)) 697 return; 698 699 memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); 700 701 nvif_mthd(&disp->disp->object, 0, &args, 702 sizeof(args.base) + drm_eld_size(args.data)); 703 nv_encoder->audio = true; 704 705 nv50_audio_component_eld_notify(drm->audio.component, nv_encoder->or, 706 nv_crtc->index); 707 } 708 709 /****************************************************************************** 710 * HDMI 711 *****************************************************************************/ 712 static void 713 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) 714 { 715 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 716 struct nv50_disp *disp = nv50_disp(encoder->dev); 717 struct { 718 struct nv50_disp_mthd_v1 base; 719 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 720 } args = { 721 .base.version = 1, 722 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 723 .base.hasht = nv_encoder->dcb->hasht, 724 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 725 (0x0100 << nv_crtc->index), 726 }; 727 728 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args)); 729 } 730 731 static void 732 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) 733 { 734 struct nouveau_drm *drm = nouveau_drm(encoder->dev); 735 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 736 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 737 struct nv50_disp *disp = nv50_disp(encoder->dev); 738 struct { 739 struct nv50_disp_mthd_v1 base; 740 struct nv50_disp_sor_hdmi_pwr_v0 pwr; 741 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */ 742 } args = { 743 .base.version = 1, 744 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, 745 .base.hasht = nv_encoder->dcb->hasht, 746 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | 747 (0x0100 << nv_crtc->index), 748 .pwr.state = 1, 749 .pwr.rekey = 56, /* binary driver, and tegra, constant */ 750 }; 751 struct nouveau_connector *nv_connector; 752 struct drm_hdmi_info *hdmi; 753 u32 max_ac_packet; 754 union hdmi_infoframe avi_frame; 755 union hdmi_infoframe vendor_frame; 756 bool high_tmds_clock_ratio = false, scrambling = false; 757 u8 config; 758 int ret; 759 int size; 760 761 nv_connector = nouveau_encoder_connector_get(nv_encoder); 762 if (!drm_detect_hdmi_monitor(nv_connector->edid)) 763 return; 764 765 hdmi = &nv_connector->base.display_info.hdmi; 766 767 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, 768 &nv_connector->base, mode); 769 if (!ret) { 770 /* We have an AVI InfoFrame, populate it to the display */ 771 args.pwr.avi_infoframe_length 772 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17); 773 } 774 775 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi, 776 &nv_connector->base, mode); 777 if (!ret) { 778 /* We have a Vendor InfoFrame, populate it to the display */ 779 args.pwr.vendor_infoframe_length 780 = hdmi_infoframe_pack(&vendor_frame, 781 args.infoframes 782 + args.pwr.avi_infoframe_length, 783 17); 784 } 785 786 max_ac_packet = mode->htotal - mode->hdisplay; 787 max_ac_packet -= args.pwr.rekey; 788 max_ac_packet -= 18; /* constant from tegra */ 789 args.pwr.max_ac_packet = max_ac_packet / 32; 790 791 if (hdmi->scdc.scrambling.supported) { 792 high_tmds_clock_ratio = mode->clock > 340000; 793 scrambling = high_tmds_clock_ratio || 794 hdmi->scdc.scrambling.low_rates; 795 } 796 797 args.pwr.scdc = 798 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | 799 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; 800 801 size = sizeof(args.base) 802 + sizeof(args.pwr) 803 + args.pwr.avi_infoframe_length 804 + args.pwr.vendor_infoframe_length; 805 nvif_mthd(&disp->disp->object, 0, &args, size); 806 807 nv50_audio_enable(encoder, mode); 808 809 /* If SCDC is supported by the downstream monitor, update 810 * divider / scrambling settings to what we programmed above. 811 */ 812 if (!hdmi->scdc.scrambling.supported) 813 return; 814 815 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); 816 if (ret < 0) { 817 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); 818 return; 819 } 820 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); 821 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; 822 config |= SCDC_SCRAMBLING_ENABLE * scrambling; 823 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); 824 if (ret < 0) 825 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", 826 config, ret); 827 } 828 829 /****************************************************************************** 830 * MST 831 *****************************************************************************/ 832 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) 833 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) 834 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) 835 836 struct nv50_mstm { 837 struct nouveau_encoder *outp; 838 839 struct drm_dp_mst_topology_mgr mgr; 840 841 bool modified; 842 bool disabled; 843 int links; 844 }; 845 846 struct nv50_mstc { 847 struct nv50_mstm *mstm; 848 struct drm_dp_mst_port *port; 849 struct drm_connector connector; 850 851 struct drm_display_mode *native; 852 struct edid *edid; 853 }; 854 855 struct nv50_msto { 856 struct drm_encoder encoder; 857 858 struct nv50_head *head; 859 struct nv50_mstc *mstc; 860 bool disabled; 861 }; 862 863 struct nouveau_encoder *nv50_real_outp(struct drm_encoder *encoder) 864 { 865 struct nv50_msto *msto; 866 867 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) 868 return nouveau_encoder(encoder); 869 870 msto = nv50_msto(encoder); 871 if (!msto->mstc) 872 return NULL; 873 return msto->mstc->mstm->outp; 874 } 875 876 static struct drm_dp_payload * 877 nv50_msto_payload(struct nv50_msto *msto) 878 { 879 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 880 struct nv50_mstc *mstc = msto->mstc; 881 struct nv50_mstm *mstm = mstc->mstm; 882 int vcpi = mstc->port->vcpi.vcpi, i; 883 884 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock)); 885 886 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); 887 for (i = 0; i < mstm->mgr.max_payloads; i++) { 888 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 889 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", 890 mstm->outp->base.base.name, i, payload->vcpi, 891 payload->start_slot, payload->num_slots); 892 } 893 894 for (i = 0; i < mstm->mgr.max_payloads; i++) { 895 struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; 896 if (payload->vcpi == vcpi) 897 return payload; 898 } 899 900 return NULL; 901 } 902 903 static void 904 nv50_msto_cleanup(struct nv50_msto *msto) 905 { 906 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 907 struct nv50_mstc *mstc = msto->mstc; 908 struct nv50_mstm *mstm = mstc->mstm; 909 910 if (!msto->disabled) 911 return; 912 913 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); 914 915 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); 916 917 msto->mstc = NULL; 918 msto->disabled = false; 919 } 920 921 static void 922 nv50_msto_prepare(struct nv50_msto *msto) 923 { 924 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); 925 struct nv50_mstc *mstc = msto->mstc; 926 struct nv50_mstm *mstm = mstc->mstm; 927 struct { 928 struct nv50_disp_mthd_v1 base; 929 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; 930 } args = { 931 .base.version = 1, 932 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, 933 .base.hasht = mstm->outp->dcb->hasht, 934 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | 935 (0x0100 << msto->head->base.index), 936 }; 937 938 mutex_lock(&mstm->mgr.payload_lock); 939 940 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); 941 if (mstc->port->vcpi.vcpi > 0) { 942 struct drm_dp_payload *payload = nv50_msto_payload(msto); 943 if (payload) { 944 args.vcpi.start_slot = payload->start_slot; 945 args.vcpi.num_slots = payload->num_slots; 946 args.vcpi.pbn = mstc->port->vcpi.pbn; 947 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; 948 } 949 } 950 951 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", 952 msto->encoder.name, msto->head->base.base.name, 953 args.vcpi.start_slot, args.vcpi.num_slots, 954 args.vcpi.pbn, args.vcpi.aligned_pbn); 955 956 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args)); 957 mutex_unlock(&mstm->mgr.payload_lock); 958 } 959 960 static int 961 nv50_msto_atomic_check(struct drm_encoder *encoder, 962 struct drm_crtc_state *crtc_state, 963 struct drm_connector_state *conn_state) 964 { 965 struct drm_atomic_state *state = crtc_state->state; 966 struct drm_connector *connector = conn_state->connector; 967 struct nv50_mstc *mstc = nv50_mstc(connector); 968 struct nv50_mstm *mstm = mstc->mstm; 969 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); 970 int slots; 971 int ret; 972 973 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, 974 mstc->native); 975 if (ret) 976 return ret; 977 978 if (!crtc_state->mode_changed && !crtc_state->connectors_changed) 979 return 0; 980 981 /* 982 * When restoring duplicated states, we need to make sure that the bw 983 * remains the same and avoid recalculating it, as the connector's bpc 984 * may have changed after the state was duplicated 985 */ 986 if (!state->duplicated) { 987 const int clock = crtc_state->adjusted_mode.clock; 988 989 asyh->or.bpc = connector->display_info.bpc; 990 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, 991 false); 992 } 993 994 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port, 995 asyh->dp.pbn, 0); 996 if (slots < 0) 997 return slots; 998 999 asyh->dp.tu = slots; 1000 1001 return 0; 1002 } 1003 1004 static u8 1005 nv50_dp_bpc_to_depth(unsigned int bpc) 1006 { 1007 switch (bpc) { 1008 case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; 1009 case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; 1010 case 10: 1011 default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; 1012 } 1013 } 1014 1015 static void 1016 nv50_msto_enable(struct drm_encoder *encoder) 1017 { 1018 struct nv50_head *head = nv50_head(encoder->crtc); 1019 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state); 1020 struct nv50_msto *msto = nv50_msto(encoder); 1021 struct nv50_mstc *mstc = NULL; 1022 struct nv50_mstm *mstm = NULL; 1023 struct drm_connector *connector; 1024 struct drm_connector_list_iter conn_iter; 1025 u8 proto; 1026 bool r; 1027 1028 drm_connector_list_iter_begin(encoder->dev, &conn_iter); 1029 drm_for_each_connector_iter(connector, &conn_iter) { 1030 if (connector->state->best_encoder == &msto->encoder) { 1031 mstc = nv50_mstc(connector); 1032 mstm = mstc->mstm; 1033 break; 1034 } 1035 } 1036 drm_connector_list_iter_end(&conn_iter); 1037 1038 if (WARN_ON(!mstc)) 1039 return; 1040 1041 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn, 1042 armh->dp.tu); 1043 if (!r) 1044 DRM_DEBUG_KMS("Failed to allocate VCPI\n"); 1045 1046 if (!mstm->links++) 1047 nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); 1048 1049 if (mstm->outp->link & 1) 1050 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1051 else 1052 proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1053 1054 mstm->outp->update(mstm->outp, head->base.index, armh, proto, 1055 nv50_dp_bpc_to_depth(armh->or.bpc)); 1056 1057 msto->mstc = mstc; 1058 mstm->modified = true; 1059 } 1060 1061 static void 1062 nv50_msto_disable(struct drm_encoder *encoder) 1063 { 1064 struct nv50_msto *msto = nv50_msto(encoder); 1065 struct nv50_mstc *mstc = msto->mstc; 1066 struct nv50_mstm *mstm = mstc->mstm; 1067 1068 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); 1069 1070 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); 1071 mstm->modified = true; 1072 if (!--mstm->links) 1073 mstm->disabled = true; 1074 msto->disabled = true; 1075 } 1076 1077 static const struct drm_encoder_helper_funcs 1078 nv50_msto_help = { 1079 .disable = nv50_msto_disable, 1080 .enable = nv50_msto_enable, 1081 .atomic_check = nv50_msto_atomic_check, 1082 }; 1083 1084 static void 1085 nv50_msto_destroy(struct drm_encoder *encoder) 1086 { 1087 struct nv50_msto *msto = nv50_msto(encoder); 1088 drm_encoder_cleanup(&msto->encoder); 1089 kfree(msto); 1090 } 1091 1092 static const struct drm_encoder_funcs 1093 nv50_msto = { 1094 .destroy = nv50_msto_destroy, 1095 }; 1096 1097 static struct nv50_msto * 1098 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) 1099 { 1100 struct nv50_msto *msto; 1101 int ret; 1102 1103 msto = kzalloc(sizeof(*msto), GFP_KERNEL); 1104 if (!msto) 1105 return ERR_PTR(-ENOMEM); 1106 1107 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, 1108 DRM_MODE_ENCODER_DPMST, "mst-%d", id); 1109 if (ret) { 1110 kfree(msto); 1111 return ERR_PTR(ret); 1112 } 1113 1114 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); 1115 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base); 1116 msto->head = head; 1117 return msto; 1118 } 1119 1120 static struct drm_encoder * 1121 nv50_mstc_atomic_best_encoder(struct drm_connector *connector, 1122 struct drm_connector_state *connector_state) 1123 { 1124 struct nv50_mstc *mstc = nv50_mstc(connector); 1125 struct drm_crtc *crtc = connector_state->crtc; 1126 1127 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1128 return NULL; 1129 1130 return &nv50_head(crtc)->msto->encoder; 1131 } 1132 1133 static enum drm_mode_status 1134 nv50_mstc_mode_valid(struct drm_connector *connector, 1135 struct drm_display_mode *mode) 1136 { 1137 struct nv50_mstc *mstc = nv50_mstc(connector); 1138 struct nouveau_encoder *outp = mstc->mstm->outp; 1139 1140 /* TODO: calculate the PBN from the dotclock and validate against the 1141 * MSTB's max possible PBN 1142 */ 1143 1144 return nv50_dp_mode_valid(connector, outp, mode, NULL); 1145 } 1146 1147 static int 1148 nv50_mstc_get_modes(struct drm_connector *connector) 1149 { 1150 struct nv50_mstc *mstc = nv50_mstc(connector); 1151 int ret = 0; 1152 1153 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); 1154 drm_connector_update_edid_property(&mstc->connector, mstc->edid); 1155 if (mstc->edid) 1156 ret = drm_add_edid_modes(&mstc->connector, mstc->edid); 1157 1158 /* 1159 * XXX: Since we don't use HDR in userspace quite yet, limit the bpc 1160 * to 8 to save bandwidth on the topology. In the future, we'll want 1161 * to properly fix this by dynamically selecting the highest possible 1162 * bpc that would fit in the topology 1163 */ 1164 if (connector->display_info.bpc) 1165 connector->display_info.bpc = 1166 clamp(connector->display_info.bpc, 6U, 8U); 1167 else 1168 connector->display_info.bpc = 8; 1169 1170 if (mstc->native) 1171 drm_mode_destroy(mstc->connector.dev, mstc->native); 1172 mstc->native = nouveau_conn_native_mode(&mstc->connector); 1173 return ret; 1174 } 1175 1176 static int 1177 nv50_mstc_atomic_check(struct drm_connector *connector, 1178 struct drm_atomic_state *state) 1179 { 1180 struct nv50_mstc *mstc = nv50_mstc(connector); 1181 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr; 1182 struct drm_connector_state *new_conn_state = 1183 drm_atomic_get_new_connector_state(state, connector); 1184 struct drm_connector_state *old_conn_state = 1185 drm_atomic_get_old_connector_state(state, connector); 1186 struct drm_crtc_state *crtc_state; 1187 struct drm_crtc *new_crtc = new_conn_state->crtc; 1188 1189 if (!old_conn_state->crtc) 1190 return 0; 1191 1192 /* We only want to free VCPI if this state disables the CRTC on this 1193 * connector 1194 */ 1195 if (new_crtc) { 1196 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); 1197 1198 if (!crtc_state || 1199 !drm_atomic_crtc_needs_modeset(crtc_state) || 1200 crtc_state->enable) 1201 return 0; 1202 } 1203 1204 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port); 1205 } 1206 1207 static int 1208 nv50_mstc_detect(struct drm_connector *connector, 1209 struct drm_modeset_acquire_ctx *ctx, bool force) 1210 { 1211 struct nv50_mstc *mstc = nv50_mstc(connector); 1212 int ret; 1213 1214 if (drm_connector_is_unregistered(connector)) 1215 return connector_status_disconnected; 1216 1217 ret = pm_runtime_get_sync(connector->dev->dev); 1218 if (ret < 0 && ret != -EACCES) { 1219 pm_runtime_put_autosuspend(connector->dev->dev); 1220 return connector_status_disconnected; 1221 } 1222 1223 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr, 1224 mstc->port); 1225 1226 pm_runtime_mark_last_busy(connector->dev->dev); 1227 pm_runtime_put_autosuspend(connector->dev->dev); 1228 return ret; 1229 } 1230 1231 static const struct drm_connector_helper_funcs 1232 nv50_mstc_help = { 1233 .get_modes = nv50_mstc_get_modes, 1234 .mode_valid = nv50_mstc_mode_valid, 1235 .atomic_best_encoder = nv50_mstc_atomic_best_encoder, 1236 .atomic_check = nv50_mstc_atomic_check, 1237 .detect_ctx = nv50_mstc_detect, 1238 }; 1239 1240 static void 1241 nv50_mstc_destroy(struct drm_connector *connector) 1242 { 1243 struct nv50_mstc *mstc = nv50_mstc(connector); 1244 1245 drm_connector_cleanup(&mstc->connector); 1246 drm_dp_mst_put_port_malloc(mstc->port); 1247 1248 kfree(mstc); 1249 } 1250 1251 static const struct drm_connector_funcs 1252 nv50_mstc = { 1253 .reset = nouveau_conn_reset, 1254 .fill_modes = drm_helper_probe_single_connector_modes, 1255 .destroy = nv50_mstc_destroy, 1256 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, 1257 .atomic_destroy_state = nouveau_conn_atomic_destroy_state, 1258 .atomic_set_property = nouveau_conn_atomic_set_property, 1259 .atomic_get_property = nouveau_conn_atomic_get_property, 1260 }; 1261 1262 static int 1263 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, 1264 const char *path, struct nv50_mstc **pmstc) 1265 { 1266 struct drm_device *dev = mstm->outp->base.base.dev; 1267 struct drm_crtc *crtc; 1268 struct nv50_mstc *mstc; 1269 int ret; 1270 1271 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) 1272 return -ENOMEM; 1273 mstc->mstm = mstm; 1274 mstc->port = port; 1275 1276 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, 1277 DRM_MODE_CONNECTOR_DisplayPort); 1278 if (ret) { 1279 kfree(*pmstc); 1280 *pmstc = NULL; 1281 return ret; 1282 } 1283 1284 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); 1285 1286 mstc->connector.funcs->reset(&mstc->connector); 1287 nouveau_conn_attach_properties(&mstc->connector); 1288 1289 drm_for_each_crtc(crtc, dev) { 1290 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc))) 1291 continue; 1292 1293 drm_connector_attach_encoder(&mstc->connector, 1294 &nv50_head(crtc)->msto->encoder); 1295 } 1296 1297 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); 1298 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); 1299 drm_connector_set_path_property(&mstc->connector, path); 1300 drm_dp_mst_get_port_malloc(port); 1301 return 0; 1302 } 1303 1304 static void 1305 nv50_mstm_cleanup(struct nv50_mstm *mstm) 1306 { 1307 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1308 struct drm_encoder *encoder; 1309 int ret; 1310 1311 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); 1312 ret = drm_dp_check_act_status(&mstm->mgr); 1313 1314 ret = drm_dp_update_payload_part2(&mstm->mgr); 1315 1316 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1317 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1318 struct nv50_msto *msto = nv50_msto(encoder); 1319 struct nv50_mstc *mstc = msto->mstc; 1320 if (mstc && mstc->mstm == mstm) 1321 nv50_msto_cleanup(msto); 1322 } 1323 } 1324 1325 mstm->modified = false; 1326 } 1327 1328 static void 1329 nv50_mstm_prepare(struct nv50_mstm *mstm) 1330 { 1331 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); 1332 struct drm_encoder *encoder; 1333 int ret; 1334 1335 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); 1336 ret = drm_dp_update_payload_part1(&mstm->mgr); 1337 1338 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { 1339 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 1340 struct nv50_msto *msto = nv50_msto(encoder); 1341 struct nv50_mstc *mstc = msto->mstc; 1342 if (mstc && mstc->mstm == mstm) 1343 nv50_msto_prepare(msto); 1344 } 1345 } 1346 1347 if (mstm->disabled) { 1348 if (!mstm->links) 1349 nv50_outp_release(mstm->outp); 1350 mstm->disabled = false; 1351 } 1352 } 1353 1354 static struct drm_connector * 1355 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1356 struct drm_dp_mst_port *port, const char *path) 1357 { 1358 struct nv50_mstm *mstm = nv50_mstm(mgr); 1359 struct nv50_mstc *mstc; 1360 int ret; 1361 1362 ret = nv50_mstc_new(mstm, port, path, &mstc); 1363 if (ret) 1364 return NULL; 1365 1366 return &mstc->connector; 1367 } 1368 1369 static const struct drm_dp_mst_topology_cbs 1370 nv50_mstm = { 1371 .add_connector = nv50_mstm_add_connector, 1372 }; 1373 1374 void 1375 nv50_mstm_service(struct nv50_mstm *mstm) 1376 { 1377 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL; 1378 bool handled = true; 1379 int ret; 1380 u8 esi[8] = {}; 1381 1382 if (!aux) 1383 return; 1384 1385 while (handled) { 1386 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); 1387 if (ret != 8) { 1388 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1389 return; 1390 } 1391 1392 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); 1393 if (!handled) 1394 break; 1395 1396 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); 1397 } 1398 } 1399 1400 void 1401 nv50_mstm_remove(struct nv50_mstm *mstm) 1402 { 1403 if (mstm) 1404 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1405 } 1406 1407 static int 1408 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) 1409 { 1410 struct nouveau_encoder *outp = mstm->outp; 1411 struct { 1412 struct nv50_disp_mthd_v1 base; 1413 struct nv50_disp_sor_dp_mst_link_v0 mst; 1414 } args = { 1415 .base.version = 1, 1416 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, 1417 .base.hasht = outp->dcb->hasht, 1418 .base.hashm = outp->dcb->hashm, 1419 .mst.state = state, 1420 }; 1421 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); 1422 struct nvif_object *disp = &drm->display->disp.object; 1423 int ret; 1424 1425 if (dpcd >= 0x12) { 1426 /* Even if we're enabling MST, start with disabling the 1427 * branching unit to clear any sink-side MST topology state 1428 * that wasn't set by us 1429 */ 1430 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0); 1431 if (ret < 0) 1432 return ret; 1433 1434 if (state) { 1435 /* Now, start initializing */ 1436 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 1437 DP_MST_EN); 1438 if (ret < 0) 1439 return ret; 1440 } 1441 } 1442 1443 return nvif_mthd(disp, 0, &args, sizeof(args)); 1444 } 1445 1446 int 1447 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) 1448 { 1449 struct drm_dp_aux *aux; 1450 int ret; 1451 bool old_state, new_state; 1452 u8 mstm_ctrl; 1453 1454 if (!mstm) 1455 return 0; 1456 1457 mutex_lock(&mstm->mgr.lock); 1458 1459 old_state = mstm->mgr.mst_state; 1460 new_state = old_state; 1461 aux = mstm->mgr.aux; 1462 1463 if (old_state) { 1464 /* Just check that the MST hub is still as we expect it */ 1465 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl); 1466 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) { 1467 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n"); 1468 new_state = false; 1469 } 1470 } else if (dpcd[0] >= 0x12) { 1471 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); 1472 if (ret < 0) 1473 goto probe_error; 1474 1475 if (!(dpcd[1] & DP_MST_CAP)) 1476 dpcd[0] = 0x11; 1477 else 1478 new_state = allow; 1479 } 1480 1481 if (new_state == old_state) { 1482 mutex_unlock(&mstm->mgr.lock); 1483 return new_state; 1484 } 1485 1486 ret = nv50_mstm_enable(mstm, dpcd[0], new_state); 1487 if (ret) 1488 goto probe_error; 1489 1490 mutex_unlock(&mstm->mgr.lock); 1491 1492 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state); 1493 if (ret) 1494 return nv50_mstm_enable(mstm, dpcd[0], 0); 1495 1496 return new_state; 1497 1498 probe_error: 1499 mutex_unlock(&mstm->mgr.lock); 1500 return ret; 1501 } 1502 1503 static void 1504 nv50_mstm_fini(struct nv50_mstm *mstm) 1505 { 1506 if (mstm && mstm->mgr.mst_state) 1507 drm_dp_mst_topology_mgr_suspend(&mstm->mgr); 1508 } 1509 1510 static void 1511 nv50_mstm_init(struct nv50_mstm *mstm, bool runtime) 1512 { 1513 int ret; 1514 1515 if (!mstm || !mstm->mgr.mst_state) 1516 return; 1517 1518 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime); 1519 if (ret == -1) { 1520 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); 1521 drm_kms_helper_hotplug_event(mstm->mgr.dev); 1522 } 1523 } 1524 1525 static void 1526 nv50_mstm_del(struct nv50_mstm **pmstm) 1527 { 1528 struct nv50_mstm *mstm = *pmstm; 1529 if (mstm) { 1530 drm_dp_mst_topology_mgr_destroy(&mstm->mgr); 1531 kfree(*pmstm); 1532 *pmstm = NULL; 1533 } 1534 } 1535 1536 static int 1537 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, 1538 int conn_base_id, struct nv50_mstm **pmstm) 1539 { 1540 const int max_payloads = hweight8(outp->dcb->heads); 1541 struct drm_device *dev = outp->base.base.dev; 1542 struct nv50_mstm *mstm; 1543 int ret; 1544 u8 dpcd; 1545 1546 /* This is a workaround for some monitors not functioning 1547 * correctly in MST mode on initial module load. I think 1548 * some bad interaction with the VBIOS may be responsible. 1549 * 1550 * A good ol' off and on again seems to work here ;) 1551 */ 1552 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); 1553 if (ret >= 0 && dpcd >= 0x12) 1554 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); 1555 1556 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) 1557 return -ENOMEM; 1558 mstm->outp = outp; 1559 mstm->mgr.cbs = &nv50_mstm; 1560 1561 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, 1562 max_payloads, conn_base_id); 1563 if (ret) 1564 return ret; 1565 1566 return 0; 1567 } 1568 1569 /****************************************************************************** 1570 * SOR 1571 *****************************************************************************/ 1572 static void 1573 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, 1574 struct nv50_head_atom *asyh, u8 proto, u8 depth) 1575 { 1576 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev); 1577 struct nv50_core *core = disp->core; 1578 1579 if (!asyh) { 1580 nv_encoder->ctrl &= ~BIT(head); 1581 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) 1582 nv_encoder->ctrl = 0; 1583 } else { 1584 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); 1585 nv_encoder->ctrl |= BIT(head); 1586 asyh->or.depth = depth; 1587 } 1588 1589 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh); 1590 } 1591 1592 static void 1593 nv50_sor_disable(struct drm_encoder *encoder) 1594 { 1595 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1596 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1597 1598 nv_encoder->crtc = NULL; 1599 1600 if (nv_crtc) { 1601 struct nvkm_i2c_aux *aux = nv_encoder->aux; 1602 u8 pwr; 1603 1604 if (aux) { 1605 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); 1606 if (ret == 0) { 1607 pwr &= ~DP_SET_POWER_MASK; 1608 pwr |= DP_SET_POWER_D3; 1609 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); 1610 } 1611 } 1612 1613 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); 1614 nv50_audio_disable(encoder, nv_crtc); 1615 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); 1616 nv50_outp_release(nv_encoder); 1617 } 1618 } 1619 1620 static void 1621 nv50_sor_enable(struct drm_encoder *encoder) 1622 { 1623 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1624 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1625 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1626 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 1627 struct { 1628 struct nv50_disp_mthd_v1 base; 1629 struct nv50_disp_sor_lvds_script_v0 lvds; 1630 } lvds = { 1631 .base.version = 1, 1632 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, 1633 .base.hasht = nv_encoder->dcb->hasht, 1634 .base.hashm = nv_encoder->dcb->hashm, 1635 }; 1636 struct nv50_disp *disp = nv50_disp(encoder->dev); 1637 struct drm_device *dev = encoder->dev; 1638 struct nouveau_drm *drm = nouveau_drm(dev); 1639 struct nouveau_connector *nv_connector; 1640 struct nvbios *bios = &drm->vbios; 1641 bool hda = false; 1642 u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; 1643 u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; 1644 1645 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1646 nv_encoder->crtc = encoder->crtc; 1647 1648 if ((disp->disp->object.oclass == GT214_DISP || 1649 disp->disp->object.oclass >= GF110_DISP) && 1650 drm_detect_monitor_audio(nv_connector->edid)) 1651 hda = true; 1652 nv50_outp_acquire(nv_encoder, hda); 1653 1654 switch (nv_encoder->dcb->type) { 1655 case DCB_OUTPUT_TMDS: 1656 if (nv_encoder->link & 1) { 1657 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; 1658 /* Only enable dual-link if: 1659 * - Need to (i.e. rate > 165MHz) 1660 * - DCB says we can 1661 * - Not an HDMI monitor, since there's no dual-link 1662 * on HDMI. 1663 */ 1664 if (mode->clock >= 165000 && 1665 nv_encoder->dcb->duallink_possible && 1666 !drm_detect_hdmi_monitor(nv_connector->edid)) 1667 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; 1668 } else { 1669 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; 1670 } 1671 1672 nv50_hdmi_enable(&nv_encoder->base.base, mode); 1673 break; 1674 case DCB_OUTPUT_LVDS: 1675 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; 1676 1677 if (bios->fp_no_ddc) { 1678 if (bios->fp.dual_link) 1679 lvds.lvds.script |= 0x0100; 1680 if (bios->fp.if_is_24bit) 1681 lvds.lvds.script |= 0x0200; 1682 } else { 1683 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1684 if (((u8 *)nv_connector->edid)[121] == 2) 1685 lvds.lvds.script |= 0x0100; 1686 } else 1687 if (mode->clock >= bios->fp.duallink_transition_clk) { 1688 lvds.lvds.script |= 0x0100; 1689 } 1690 1691 if (lvds.lvds.script & 0x0100) { 1692 if (bios->fp.strapless_is_24bit & 2) 1693 lvds.lvds.script |= 0x0200; 1694 } else { 1695 if (bios->fp.strapless_is_24bit & 1) 1696 lvds.lvds.script |= 0x0200; 1697 } 1698 1699 if (asyh->or.bpc == 8) 1700 lvds.lvds.script |= 0x0200; 1701 } 1702 1703 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds)); 1704 break; 1705 case DCB_OUTPUT_DP: 1706 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); 1707 1708 if (nv_encoder->link & 1) 1709 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; 1710 else 1711 proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; 1712 1713 nv50_audio_enable(encoder, mode); 1714 break; 1715 default: 1716 BUG(); 1717 break; 1718 } 1719 1720 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); 1721 } 1722 1723 static const struct drm_encoder_helper_funcs 1724 nv50_sor_help = { 1725 .atomic_check = nv50_outp_atomic_check, 1726 .enable = nv50_sor_enable, 1727 .disable = nv50_sor_disable, 1728 }; 1729 1730 static void 1731 nv50_sor_destroy(struct drm_encoder *encoder) 1732 { 1733 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1734 nv50_mstm_del(&nv_encoder->dp.mstm); 1735 drm_encoder_cleanup(encoder); 1736 kfree(encoder); 1737 } 1738 1739 static const struct drm_encoder_funcs 1740 nv50_sor_func = { 1741 .destroy = nv50_sor_destroy, 1742 }; 1743 1744 static bool nv50_has_mst(struct nouveau_drm *drm) 1745 { 1746 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 1747 u32 data; 1748 u8 ver, hdr, cnt, len; 1749 1750 data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len); 1751 return data && ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04); 1752 } 1753 1754 static int 1755 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) 1756 { 1757 struct nouveau_connector *nv_connector = nouveau_connector(connector); 1758 struct nouveau_drm *drm = nouveau_drm(connector->dev); 1759 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1760 struct nouveau_encoder *nv_encoder; 1761 struct drm_encoder *encoder; 1762 struct nv50_disp *disp = nv50_disp(connector->dev); 1763 int type, ret; 1764 1765 switch (dcbe->type) { 1766 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; 1767 case DCB_OUTPUT_TMDS: 1768 case DCB_OUTPUT_DP: 1769 default: 1770 type = DRM_MODE_ENCODER_TMDS; 1771 break; 1772 } 1773 1774 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1775 if (!nv_encoder) 1776 return -ENOMEM; 1777 nv_encoder->dcb = dcbe; 1778 nv_encoder->update = nv50_sor_update; 1779 1780 encoder = to_drm_encoder(nv_encoder); 1781 encoder->possible_crtcs = dcbe->heads; 1782 encoder->possible_clones = 0; 1783 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, 1784 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); 1785 drm_encoder_helper_add(encoder, &nv50_sor_help); 1786 1787 drm_connector_attach_encoder(connector, encoder); 1788 1789 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1790 1791 if (dcbe->type == DCB_OUTPUT_DP) { 1792 struct nvkm_i2c_aux *aux = 1793 nvkm_i2c_aux_find(i2c, dcbe->i2c_index); 1794 1795 if (aux) { 1796 if (disp->disp->object.oclass < GF110_DISP) { 1797 /* HW has no support for address-only 1798 * transactions, so we're required to 1799 * use custom I2C-over-AUX code. 1800 */ 1801 nv_encoder->i2c = &aux->i2c; 1802 } else { 1803 nv_encoder->i2c = &nv_connector->aux.ddc; 1804 } 1805 nv_encoder->aux = aux; 1806 } 1807 1808 if (nv_connector->type != DCB_CONNECTOR_eDP && 1809 nv50_has_mst(drm)) { 1810 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 1811 16, nv_connector->base.base.id, 1812 &nv_encoder->dp.mstm); 1813 if (ret) 1814 return ret; 1815 } 1816 } else { 1817 struct nvkm_i2c_bus *bus = 1818 nvkm_i2c_bus_find(i2c, dcbe->i2c_index); 1819 if (bus) 1820 nv_encoder->i2c = &bus->i2c; 1821 } 1822 1823 return 0; 1824 } 1825 1826 /****************************************************************************** 1827 * PIOR 1828 *****************************************************************************/ 1829 static int 1830 nv50_pior_atomic_check(struct drm_encoder *encoder, 1831 struct drm_crtc_state *crtc_state, 1832 struct drm_connector_state *conn_state) 1833 { 1834 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); 1835 if (ret) 1836 return ret; 1837 crtc_state->adjusted_mode.clock *= 2; 1838 return 0; 1839 } 1840 1841 static void 1842 nv50_pior_disable(struct drm_encoder *encoder) 1843 { 1844 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1845 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1846 const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); 1847 if (nv_encoder->crtc) 1848 core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL); 1849 nv_encoder->crtc = NULL; 1850 nv50_outp_release(nv_encoder); 1851 } 1852 1853 static void 1854 nv50_pior_enable(struct drm_encoder *encoder) 1855 { 1856 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1857 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1858 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); 1859 struct nv50_core *core = nv50_disp(encoder->dev)->core; 1860 u32 ctrl = 0; 1861 1862 switch (nv_crtc->index) { 1863 case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; 1864 case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; 1865 default: 1866 WARN_ON(1); 1867 break; 1868 } 1869 1870 nv50_outp_acquire(nv_encoder, false); 1871 1872 switch (asyh->or.bpc) { 1873 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; 1874 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; 1875 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; 1876 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; 1877 } 1878 1879 switch (nv_encoder->dcb->type) { 1880 case DCB_OUTPUT_TMDS: 1881 case DCB_OUTPUT_DP: 1882 ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); 1883 break; 1884 default: 1885 BUG(); 1886 break; 1887 } 1888 1889 core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh); 1890 nv_encoder->crtc = encoder->crtc; 1891 } 1892 1893 static const struct drm_encoder_helper_funcs 1894 nv50_pior_help = { 1895 .atomic_check = nv50_pior_atomic_check, 1896 .enable = nv50_pior_enable, 1897 .disable = nv50_pior_disable, 1898 }; 1899 1900 static void 1901 nv50_pior_destroy(struct drm_encoder *encoder) 1902 { 1903 drm_encoder_cleanup(encoder); 1904 kfree(encoder); 1905 } 1906 1907 static const struct drm_encoder_funcs 1908 nv50_pior_func = { 1909 .destroy = nv50_pior_destroy, 1910 }; 1911 1912 static int 1913 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) 1914 { 1915 struct drm_device *dev = connector->dev; 1916 struct nouveau_drm *drm = nouveau_drm(dev); 1917 struct nv50_disp *disp = nv50_disp(dev); 1918 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); 1919 struct nvkm_i2c_bus *bus = NULL; 1920 struct nvkm_i2c_aux *aux = NULL; 1921 struct i2c_adapter *ddc; 1922 struct nouveau_encoder *nv_encoder; 1923 struct drm_encoder *encoder; 1924 int type; 1925 1926 switch (dcbe->type) { 1927 case DCB_OUTPUT_TMDS: 1928 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); 1929 ddc = bus ? &bus->i2c : NULL; 1930 type = DRM_MODE_ENCODER_TMDS; 1931 break; 1932 case DCB_OUTPUT_DP: 1933 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); 1934 ddc = aux ? &aux->i2c : NULL; 1935 type = DRM_MODE_ENCODER_TMDS; 1936 break; 1937 default: 1938 return -ENODEV; 1939 } 1940 1941 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); 1942 if (!nv_encoder) 1943 return -ENOMEM; 1944 nv_encoder->dcb = dcbe; 1945 nv_encoder->i2c = ddc; 1946 nv_encoder->aux = aux; 1947 1948 encoder = to_drm_encoder(nv_encoder); 1949 encoder->possible_crtcs = dcbe->heads; 1950 encoder->possible_clones = 0; 1951 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, 1952 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); 1953 drm_encoder_helper_add(encoder, &nv50_pior_help); 1954 1955 drm_connector_attach_encoder(connector, encoder); 1956 1957 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1); 1958 1959 return 0; 1960 } 1961 1962 /****************************************************************************** 1963 * Atomic 1964 *****************************************************************************/ 1965 1966 static void 1967 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock) 1968 { 1969 struct nouveau_drm *drm = nouveau_drm(state->dev); 1970 struct nv50_disp *disp = nv50_disp(drm->dev); 1971 struct nv50_core *core = disp->core; 1972 struct nv50_mstm *mstm; 1973 struct drm_encoder *encoder; 1974 1975 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]); 1976 1977 drm_for_each_encoder(encoder, drm->dev) { 1978 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1979 mstm = nouveau_encoder(encoder)->dp.mstm; 1980 if (mstm && mstm->modified) 1981 nv50_mstm_prepare(mstm); 1982 } 1983 } 1984 1985 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY); 1986 core->func->update(core, interlock, true); 1987 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY, 1988 disp->core->chan.base.device)) 1989 NV_ERROR(drm, "core notifier timeout\n"); 1990 1991 drm_for_each_encoder(encoder, drm->dev) { 1992 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 1993 mstm = nouveau_encoder(encoder)->dp.mstm; 1994 if (mstm && mstm->modified) 1995 nv50_mstm_cleanup(mstm); 1996 } 1997 } 1998 } 1999 2000 static void 2001 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock) 2002 { 2003 struct drm_plane_state *new_plane_state; 2004 struct drm_plane *plane; 2005 int i; 2006 2007 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2008 struct nv50_wndw *wndw = nv50_wndw(plane); 2009 if (interlock[wndw->interlock.type] & wndw->interlock.data) { 2010 if (wndw->func->update) 2011 wndw->func->update(wndw, interlock); 2012 } 2013 } 2014 } 2015 2016 static void 2017 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) 2018 { 2019 struct drm_device *dev = state->dev; 2020 struct drm_crtc_state *new_crtc_state, *old_crtc_state; 2021 struct drm_crtc *crtc; 2022 struct drm_plane_state *new_plane_state; 2023 struct drm_plane *plane; 2024 struct nouveau_drm *drm = nouveau_drm(dev); 2025 struct nv50_disp *disp = nv50_disp(dev); 2026 struct nv50_atom *atom = nv50_atom(state); 2027 struct nv50_core *core = disp->core; 2028 struct nv50_outp_atom *outp, *outt; 2029 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {}; 2030 int i; 2031 bool flushed = false; 2032 2033 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); 2034 nv50_crc_atomic_stop_reporting(state); 2035 drm_atomic_helper_wait_for_fences(dev, state, false); 2036 drm_atomic_helper_wait_for_dependencies(state); 2037 drm_atomic_helper_update_legacy_modeset_state(dev, state); 2038 2039 if (atom->lock_core) 2040 mutex_lock(&disp->mutex); 2041 2042 /* Disable head(s). */ 2043 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2044 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2045 struct nv50_head *head = nv50_head(crtc); 2046 2047 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, 2048 asyh->clr.mask, asyh->set.mask); 2049 2050 if (old_crtc_state->active && !new_crtc_state->active) { 2051 pm_runtime_put_noidle(dev->dev); 2052 drm_crtc_vblank_off(crtc); 2053 } 2054 2055 if (asyh->clr.mask) { 2056 nv50_head_flush_clr(head, asyh, atom->flush_disable); 2057 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2058 } 2059 } 2060 2061 /* Disable plane(s). */ 2062 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2063 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2064 struct nv50_wndw *wndw = nv50_wndw(plane); 2065 2066 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, 2067 asyw->clr.mask, asyw->set.mask); 2068 if (!asyw->clr.mask) 2069 continue; 2070 2071 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw); 2072 } 2073 2074 /* Disable output path(s). */ 2075 list_for_each_entry(outp, &atom->outp, head) { 2076 const struct drm_encoder_helper_funcs *help; 2077 struct drm_encoder *encoder; 2078 2079 encoder = outp->encoder; 2080 help = encoder->helper_private; 2081 2082 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, 2083 outp->clr.mask, outp->set.mask); 2084 2085 if (outp->clr.mask) { 2086 help->disable(encoder); 2087 interlock[NV50_DISP_INTERLOCK_CORE] |= 1; 2088 if (outp->flush_disable) { 2089 nv50_disp_atomic_commit_wndw(state, interlock); 2090 nv50_disp_atomic_commit_core(state, interlock); 2091 memset(interlock, 0x00, sizeof(interlock)); 2092 2093 flushed = true; 2094 } 2095 } 2096 } 2097 2098 /* Flush disable. */ 2099 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2100 if (atom->flush_disable) { 2101 nv50_disp_atomic_commit_wndw(state, interlock); 2102 nv50_disp_atomic_commit_core(state, interlock); 2103 memset(interlock, 0x00, sizeof(interlock)); 2104 2105 flushed = true; 2106 } 2107 } 2108 2109 if (flushed) 2110 nv50_crc_atomic_release_notifier_contexts(state); 2111 nv50_crc_atomic_init_notifier_contexts(state); 2112 2113 /* Update output path(s). */ 2114 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2115 const struct drm_encoder_helper_funcs *help; 2116 struct drm_encoder *encoder; 2117 2118 encoder = outp->encoder; 2119 help = encoder->helper_private; 2120 2121 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, 2122 outp->set.mask, outp->clr.mask); 2123 2124 if (outp->set.mask) { 2125 help->enable(encoder); 2126 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2127 } 2128 2129 list_del(&outp->head); 2130 kfree(outp); 2131 } 2132 2133 /* Update head(s). */ 2134 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 2135 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); 2136 struct nv50_head *head = nv50_head(crtc); 2137 2138 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, 2139 asyh->set.mask, asyh->clr.mask); 2140 2141 if (asyh->set.mask) { 2142 nv50_head_flush_set(head, asyh); 2143 interlock[NV50_DISP_INTERLOCK_CORE] = 1; 2144 } 2145 2146 if (new_crtc_state->active) { 2147 if (!old_crtc_state->active) { 2148 drm_crtc_vblank_on(crtc); 2149 pm_runtime_get_noresume(dev->dev); 2150 } 2151 if (new_crtc_state->event) 2152 drm_crtc_vblank_get(crtc); 2153 } 2154 } 2155 2156 /* Update window->head assignment. 2157 * 2158 * This has to happen in an update that's not interlocked with 2159 * any window channels to avoid hitting HW error checks. 2160 * 2161 *TODO: Proper handling of window ownership (Turing apparently 2162 * supports non-fixed mappings). 2163 */ 2164 if (core->assign_windows) { 2165 core->func->wndw.owner(core); 2166 nv50_disp_atomic_commit_core(state, interlock); 2167 core->assign_windows = false; 2168 interlock[NV50_DISP_INTERLOCK_CORE] = 0; 2169 } 2170 2171 /* Update plane(s). */ 2172 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2173 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2174 struct nv50_wndw *wndw = nv50_wndw(plane); 2175 2176 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, 2177 asyw->set.mask, asyw->clr.mask); 2178 if ( !asyw->set.mask && 2179 (!asyw->clr.mask || atom->flush_disable)) 2180 continue; 2181 2182 nv50_wndw_flush_set(wndw, interlock, asyw); 2183 } 2184 2185 /* Flush update. */ 2186 nv50_disp_atomic_commit_wndw(state, interlock); 2187 2188 if (interlock[NV50_DISP_INTERLOCK_CORE]) { 2189 if (interlock[NV50_DISP_INTERLOCK_BASE] || 2190 interlock[NV50_DISP_INTERLOCK_OVLY] || 2191 interlock[NV50_DISP_INTERLOCK_WNDW] || 2192 !atom->state.legacy_cursor_update) 2193 nv50_disp_atomic_commit_core(state, interlock); 2194 else 2195 disp->core->func->update(disp->core, interlock, false); 2196 } 2197 2198 if (atom->lock_core) 2199 mutex_unlock(&disp->mutex); 2200 2201 /* Wait for HW to signal completion. */ 2202 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2203 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2204 struct nv50_wndw *wndw = nv50_wndw(plane); 2205 int ret = nv50_wndw_wait_armed(wndw, asyw); 2206 if (ret) 2207 NV_ERROR(drm, "%s: timeout\n", plane->name); 2208 } 2209 2210 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2211 if (new_crtc_state->event) { 2212 unsigned long flags; 2213 /* Get correct count/ts if racing with vblank irq */ 2214 if (new_crtc_state->active) 2215 drm_crtc_accurate_vblank_count(crtc); 2216 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2217 drm_crtc_send_vblank_event(crtc, new_crtc_state->event); 2218 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2219 2220 new_crtc_state->event = NULL; 2221 if (new_crtc_state->active) 2222 drm_crtc_vblank_put(crtc); 2223 } 2224 } 2225 2226 nv50_crc_atomic_start_reporting(state); 2227 if (!flushed) 2228 nv50_crc_atomic_release_notifier_contexts(state); 2229 drm_atomic_helper_commit_hw_done(state); 2230 drm_atomic_helper_cleanup_planes(dev, state); 2231 drm_atomic_helper_commit_cleanup_done(state); 2232 drm_atomic_state_put(state); 2233 2234 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ 2235 pm_runtime_mark_last_busy(dev->dev); 2236 pm_runtime_put_autosuspend(dev->dev); 2237 } 2238 2239 static void 2240 nv50_disp_atomic_commit_work(struct work_struct *work) 2241 { 2242 struct drm_atomic_state *state = 2243 container_of(work, typeof(*state), commit_work); 2244 nv50_disp_atomic_commit_tail(state); 2245 } 2246 2247 static int 2248 nv50_disp_atomic_commit(struct drm_device *dev, 2249 struct drm_atomic_state *state, bool nonblock) 2250 { 2251 struct drm_plane_state *new_plane_state; 2252 struct drm_plane *plane; 2253 int ret, i; 2254 2255 ret = pm_runtime_get_sync(dev->dev); 2256 if (ret < 0 && ret != -EACCES) { 2257 pm_runtime_put_autosuspend(dev->dev); 2258 return ret; 2259 } 2260 2261 ret = drm_atomic_helper_setup_commit(state, nonblock); 2262 if (ret) 2263 goto done; 2264 2265 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); 2266 2267 ret = drm_atomic_helper_prepare_planes(dev, state); 2268 if (ret) 2269 goto done; 2270 2271 if (!nonblock) { 2272 ret = drm_atomic_helper_wait_for_fences(dev, state, true); 2273 if (ret) 2274 goto err_cleanup; 2275 } 2276 2277 ret = drm_atomic_helper_swap_state(state, true); 2278 if (ret) 2279 goto err_cleanup; 2280 2281 for_each_new_plane_in_state(state, plane, new_plane_state, i) { 2282 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state); 2283 struct nv50_wndw *wndw = nv50_wndw(plane); 2284 2285 if (asyw->set.image) 2286 nv50_wndw_ntfy_enable(wndw, asyw); 2287 } 2288 2289 drm_atomic_state_get(state); 2290 2291 /* 2292 * Grab another RPM ref for the commit tail, which will release the 2293 * ref when it's finished 2294 */ 2295 pm_runtime_get_noresume(dev->dev); 2296 2297 if (nonblock) 2298 queue_work(system_unbound_wq, &state->commit_work); 2299 else 2300 nv50_disp_atomic_commit_tail(state); 2301 2302 err_cleanup: 2303 if (ret) 2304 drm_atomic_helper_cleanup_planes(dev, state); 2305 done: 2306 pm_runtime_put_autosuspend(dev->dev); 2307 return ret; 2308 } 2309 2310 static struct nv50_outp_atom * 2311 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) 2312 { 2313 struct nv50_outp_atom *outp; 2314 2315 list_for_each_entry(outp, &atom->outp, head) { 2316 if (outp->encoder == encoder) 2317 return outp; 2318 } 2319 2320 outp = kzalloc(sizeof(*outp), GFP_KERNEL); 2321 if (!outp) 2322 return ERR_PTR(-ENOMEM); 2323 2324 list_add(&outp->head, &atom->outp); 2325 outp->encoder = encoder; 2326 return outp; 2327 } 2328 2329 static int 2330 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, 2331 struct drm_connector_state *old_connector_state) 2332 { 2333 struct drm_encoder *encoder = old_connector_state->best_encoder; 2334 struct drm_crtc_state *old_crtc_state, *new_crtc_state; 2335 struct drm_crtc *crtc; 2336 struct nv50_outp_atom *outp; 2337 2338 if (!(crtc = old_connector_state->crtc)) 2339 return 0; 2340 2341 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc); 2342 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2343 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2344 outp = nv50_disp_outp_atomic_add(atom, encoder); 2345 if (IS_ERR(outp)) 2346 return PTR_ERR(outp); 2347 2348 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { 2349 outp->flush_disable = true; 2350 atom->flush_disable = true; 2351 } 2352 outp->clr.ctrl = true; 2353 atom->lock_core = true; 2354 } 2355 2356 return 0; 2357 } 2358 2359 static int 2360 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, 2361 struct drm_connector_state *connector_state) 2362 { 2363 struct drm_encoder *encoder = connector_state->best_encoder; 2364 struct drm_crtc_state *new_crtc_state; 2365 struct drm_crtc *crtc; 2366 struct nv50_outp_atom *outp; 2367 2368 if (!(crtc = connector_state->crtc)) 2369 return 0; 2370 2371 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc); 2372 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) { 2373 outp = nv50_disp_outp_atomic_add(atom, encoder); 2374 if (IS_ERR(outp)) 2375 return PTR_ERR(outp); 2376 2377 outp->set.ctrl = true; 2378 atom->lock_core = true; 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int 2385 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 2386 { 2387 struct nv50_atom *atom = nv50_atom(state); 2388 struct nv50_core *core = nv50_disp(dev)->core; 2389 struct drm_connector_state *old_connector_state, *new_connector_state; 2390 struct drm_connector *connector; 2391 struct drm_crtc_state *new_crtc_state; 2392 struct drm_crtc *crtc; 2393 struct nv50_head *head; 2394 struct nv50_head_atom *asyh; 2395 int ret, i; 2396 2397 if (core->assign_windows && core->func->head->static_wndw_map) { 2398 drm_for_each_crtc(crtc, dev) { 2399 new_crtc_state = drm_atomic_get_crtc_state(state, 2400 crtc); 2401 if (IS_ERR(new_crtc_state)) 2402 return PTR_ERR(new_crtc_state); 2403 2404 head = nv50_head(crtc); 2405 asyh = nv50_head_atom(new_crtc_state); 2406 core->func->head->static_wndw_map(head, asyh); 2407 } 2408 } 2409 2410 /* We need to handle colour management on a per-plane basis. */ 2411 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 2412 if (new_crtc_state->color_mgmt_changed) { 2413 ret = drm_atomic_add_affected_planes(state, crtc); 2414 if (ret) 2415 return ret; 2416 } 2417 } 2418 2419 ret = drm_atomic_helper_check(dev, state); 2420 if (ret) 2421 return ret; 2422 2423 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) { 2424 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state); 2425 if (ret) 2426 return ret; 2427 2428 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state); 2429 if (ret) 2430 return ret; 2431 } 2432 2433 ret = drm_dp_mst_atomic_check(state); 2434 if (ret) 2435 return ret; 2436 2437 nv50_crc_atomic_check_outp(atom); 2438 2439 return 0; 2440 } 2441 2442 static void 2443 nv50_disp_atomic_state_clear(struct drm_atomic_state *state) 2444 { 2445 struct nv50_atom *atom = nv50_atom(state); 2446 struct nv50_outp_atom *outp, *outt; 2447 2448 list_for_each_entry_safe(outp, outt, &atom->outp, head) { 2449 list_del(&outp->head); 2450 kfree(outp); 2451 } 2452 2453 drm_atomic_state_default_clear(state); 2454 } 2455 2456 static void 2457 nv50_disp_atomic_state_free(struct drm_atomic_state *state) 2458 { 2459 struct nv50_atom *atom = nv50_atom(state); 2460 drm_atomic_state_default_release(&atom->state); 2461 kfree(atom); 2462 } 2463 2464 static struct drm_atomic_state * 2465 nv50_disp_atomic_state_alloc(struct drm_device *dev) 2466 { 2467 struct nv50_atom *atom; 2468 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || 2469 drm_atomic_state_init(dev, &atom->state) < 0) { 2470 kfree(atom); 2471 return NULL; 2472 } 2473 INIT_LIST_HEAD(&atom->outp); 2474 return &atom->state; 2475 } 2476 2477 static const struct drm_mode_config_funcs 2478 nv50_disp_func = { 2479 .fb_create = nouveau_user_framebuffer_create, 2480 .output_poll_changed = nouveau_fbcon_output_poll_changed, 2481 .atomic_check = nv50_disp_atomic_check, 2482 .atomic_commit = nv50_disp_atomic_commit, 2483 .atomic_state_alloc = nv50_disp_atomic_state_alloc, 2484 .atomic_state_clear = nv50_disp_atomic_state_clear, 2485 .atomic_state_free = nv50_disp_atomic_state_free, 2486 }; 2487 2488 /****************************************************************************** 2489 * Init 2490 *****************************************************************************/ 2491 2492 static void 2493 nv50_display_fini(struct drm_device *dev, bool suspend) 2494 { 2495 struct nouveau_encoder *nv_encoder; 2496 struct drm_encoder *encoder; 2497 struct drm_plane *plane; 2498 2499 drm_for_each_plane(plane, dev) { 2500 struct nv50_wndw *wndw = nv50_wndw(plane); 2501 if (plane->funcs != &nv50_wndw) 2502 continue; 2503 nv50_wndw_fini(wndw); 2504 } 2505 2506 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2507 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2508 nv_encoder = nouveau_encoder(encoder); 2509 nv50_mstm_fini(nv_encoder->dp.mstm); 2510 } 2511 } 2512 } 2513 2514 static int 2515 nv50_display_init(struct drm_device *dev, bool resume, bool runtime) 2516 { 2517 struct nv50_core *core = nv50_disp(dev)->core; 2518 struct drm_encoder *encoder; 2519 struct drm_plane *plane; 2520 2521 if (resume || runtime) 2522 core->func->init(core); 2523 2524 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2525 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { 2526 struct nouveau_encoder *nv_encoder = 2527 nouveau_encoder(encoder); 2528 nv50_mstm_init(nv_encoder->dp.mstm, runtime); 2529 } 2530 } 2531 2532 drm_for_each_plane(plane, dev) { 2533 struct nv50_wndw *wndw = nv50_wndw(plane); 2534 if (plane->funcs != &nv50_wndw) 2535 continue; 2536 nv50_wndw_init(wndw); 2537 } 2538 2539 return 0; 2540 } 2541 2542 static void 2543 nv50_display_destroy(struct drm_device *dev) 2544 { 2545 struct nv50_disp *disp = nv50_disp(dev); 2546 2547 nv50_audio_component_fini(nouveau_drm(dev)); 2548 2549 nvif_object_unmap(&disp->caps); 2550 nvif_object_dtor(&disp->caps); 2551 nv50_core_del(&disp->core); 2552 2553 nouveau_bo_unmap(disp->sync); 2554 if (disp->sync) 2555 nouveau_bo_unpin(disp->sync); 2556 nouveau_bo_ref(NULL, &disp->sync); 2557 2558 nouveau_display(dev)->priv = NULL; 2559 kfree(disp); 2560 } 2561 2562 int 2563 nv50_display_create(struct drm_device *dev) 2564 { 2565 struct nvif_device *device = &nouveau_drm(dev)->client.device; 2566 struct nouveau_drm *drm = nouveau_drm(dev); 2567 struct dcb_table *dcb = &drm->vbios.dcb; 2568 struct drm_connector *connector, *tmp; 2569 struct nv50_disp *disp; 2570 struct dcb_output *dcbe; 2571 int crtcs, ret, i; 2572 bool has_mst = nv50_has_mst(drm); 2573 2574 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2575 if (!disp) 2576 return -ENOMEM; 2577 2578 mutex_init(&disp->mutex); 2579 2580 nouveau_display(dev)->priv = disp; 2581 nouveau_display(dev)->dtor = nv50_display_destroy; 2582 nouveau_display(dev)->init = nv50_display_init; 2583 nouveau_display(dev)->fini = nv50_display_fini; 2584 disp->disp = &nouveau_display(dev)->disp; 2585 dev->mode_config.funcs = &nv50_disp_func; 2586 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; 2587 dev->mode_config.normalize_zpos = true; 2588 2589 /* small shared memory area we use for notifiers and semaphores */ 2590 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2591 0, 0x0000, NULL, NULL, &disp->sync); 2592 if (!ret) { 2593 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); 2594 if (!ret) { 2595 ret = nouveau_bo_map(disp->sync); 2596 if (ret) 2597 nouveau_bo_unpin(disp->sync); 2598 } 2599 if (ret) 2600 nouveau_bo_ref(NULL, &disp->sync); 2601 } 2602 2603 if (ret) 2604 goto out; 2605 2606 /* allocate master evo channel */ 2607 ret = nv50_core_new(drm, &disp->core); 2608 if (ret) 2609 goto out; 2610 2611 disp->core->func->init(disp->core); 2612 if (disp->core->func->caps_init) { 2613 ret = disp->core->func->caps_init(drm, disp); 2614 if (ret) 2615 goto out; 2616 } 2617 2618 /* Assign the correct format modifiers */ 2619 if (disp->disp->object.oclass >= TU102_DISP) 2620 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers; 2621 else 2622 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI) 2623 nouveau_display(dev)->format_modifiers = disp90xx_modifiers; 2624 else 2625 nouveau_display(dev)->format_modifiers = disp50xx_modifiers; 2626 2627 /* create crtc objects to represent the hw heads */ 2628 if (disp->disp->object.oclass >= GV100_DISP) 2629 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff; 2630 else 2631 if (disp->disp->object.oclass >= GF110_DISP) 2632 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf; 2633 else 2634 crtcs = 0x3; 2635 2636 for (i = 0; i < fls(crtcs); i++) { 2637 struct nv50_head *head; 2638 2639 if (!(crtcs & (1 << i))) 2640 continue; 2641 2642 head = nv50_head_create(dev, i); 2643 if (IS_ERR(head)) { 2644 ret = PTR_ERR(head); 2645 goto out; 2646 } 2647 2648 if (has_mst) { 2649 head->msto = nv50_msto_new(dev, head, i); 2650 if (IS_ERR(head->msto)) { 2651 ret = PTR_ERR(head->msto); 2652 head->msto = NULL; 2653 goto out; 2654 } 2655 2656 /* 2657 * FIXME: This is a hack to workaround the following 2658 * issues: 2659 * 2660 * https://gitlab.gnome.org/GNOME/mutter/issues/759 2661 * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277 2662 * 2663 * Once these issues are closed, this should be 2664 * removed 2665 */ 2666 head->msto->encoder.possible_crtcs = crtcs; 2667 } 2668 } 2669 2670 /* create encoder/connector objects based on VBIOS DCB table */ 2671 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { 2672 connector = nouveau_connector_create(dev, dcbe); 2673 if (IS_ERR(connector)) 2674 continue; 2675 2676 if (dcbe->location == DCB_LOC_ON_CHIP) { 2677 switch (dcbe->type) { 2678 case DCB_OUTPUT_TMDS: 2679 case DCB_OUTPUT_LVDS: 2680 case DCB_OUTPUT_DP: 2681 ret = nv50_sor_create(connector, dcbe); 2682 break; 2683 case DCB_OUTPUT_ANALOG: 2684 ret = nv50_dac_create(connector, dcbe); 2685 break; 2686 default: 2687 ret = -ENODEV; 2688 break; 2689 } 2690 } else { 2691 ret = nv50_pior_create(connector, dcbe); 2692 } 2693 2694 if (ret) { 2695 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", 2696 dcbe->location, dcbe->type, 2697 ffs(dcbe->or) - 1, ret); 2698 ret = 0; 2699 } 2700 } 2701 2702 /* cull any connectors we created that don't have an encoder */ 2703 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { 2704 if (connector->possible_encoders) 2705 continue; 2706 2707 NV_WARN(drm, "%s has no encoders, removing\n", 2708 connector->name); 2709 connector->funcs->destroy(connector); 2710 } 2711 2712 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */ 2713 dev->vblank_disable_immediate = true; 2714 2715 nv50_audio_component_init(drm); 2716 2717 out: 2718 if (ret) 2719 nv50_display_destroy(dev); 2720 return ret; 2721 } 2722 2723 /****************************************************************************** 2724 * Format modifiers 2725 *****************************************************************************/ 2726 2727 /**************************************************************** 2728 * Log2(block height) ----------------------------+ * 2729 * Page Kind ----------------------------------+ | * 2730 * Gob Height/Page Kind Generation ------+ | | * 2731 * Sector layout -------+ | | | * 2732 * Compression ------+ | | | | */ 2733 const u64 disp50xx_modifiers[] = { /* | | | | | */ 2734 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 0), 2735 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 1), 2736 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 2), 2737 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 3), 2738 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 4), 2739 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x7a, 5), 2740 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 0), 2741 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 1), 2742 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 2), 2743 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 3), 2744 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 4), 2745 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x78, 5), 2746 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 0), 2747 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 1), 2748 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 2), 2749 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 3), 2750 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 4), 2751 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 1, 0x70, 5), 2752 DRM_FORMAT_MOD_LINEAR, 2753 DRM_FORMAT_MOD_INVALID 2754 }; 2755 2756 /**************************************************************** 2757 * Log2(block height) ----------------------------+ * 2758 * Page Kind ----------------------------------+ | * 2759 * Gob Height/Page Kind Generation ------+ | | * 2760 * Sector layout -------+ | | | * 2761 * Compression ------+ | | | | */ 2762 const u64 disp90xx_modifiers[] = { /* | | | | | */ 2763 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 0), 2764 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 1), 2765 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 2), 2766 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 3), 2767 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 4), 2768 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 1, 0, 0xfe, 5), 2769 DRM_FORMAT_MOD_LINEAR, 2770 DRM_FORMAT_MOD_INVALID 2771 }; 2772